Spartan-6 LX9 MicroBoard Embedded Tutorial 1
Spartan-6 LX9 MicroBoard Embedded Tutorial 1
Tutorial 1
Creating an AXI-based Embedded System
Version 13.1.01
Revision History
Version
13.1.01
Description
Initial release for EDK 13.1
Date
5/15/2011
Table of Contents
Revision History.............................................................................................................................. 2
Table of Contents ........................................................................................................................... 2
Table of Figures.............................................................................................................................. 2
Overview......................................................................................................................................... 3
Objectives ....................................................................................................................................... 3
Requirements ................................................................................................................................. 4
Software ...................................................................................................................................... 4
Hardware .................................................................................................................................... 4
Recommended Reading ............................................................................................................. 4
I. Create the Hardware Platform ..................................................................................................... 5
II. Understanding the System ......................................................................................................... 7
III. Compiling a Test Application Using SDK ................................................................................... 8
IV. Test the Generated System with the Test Application ............................................................. 11
Getting Help and Support ............................................................................................................. 15
Table of Figures
Figure 1 - Hardware Platform ......................................................................................................... 3
Figure 2 - Base System Builder Peripherals ................................................................................... 6
Figure 3 - System Assembly View .................................................................................................. 7
Figure 4 - Workspace Launcher ..................................................................................................... 9
Figure 5 - SDK Project Explorer ................................................................................................... 10
Figure 6 - Linker Script Configuration ........................................................................................... 11
Figure 7 - Connect LX9 MicroBoard to host PC............................................................................ 12
Figure 8 - FPGA Programming ..................................................................................................... 13
Figure 9 - Run Configurations....................................................................................................... 13
Figure 10 - STDIO Configuration .................................................................................................. 14
Figure 11 - Console View ............................................................................................................. 14
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Overview
This is the first tutorial in a series of training material dedicated to introducing engineers to creating their
first embedded designs featuring the new AXI interface. These tutorials will cover all the required steps
for creating a complete MicroBlaze design in the Spartan-6 LX9 MicroBoard. While dedicated to this
platform, the information learned here can be used with any Xilinx FPGA.
The tutorial is divided into four main steps: creating the hardware platform, understanding what was
created, using SDK to compile a software application and testing the system on the FPGA. The test
application will reside in Block memory inside the FPGA. Below is a block diagram of the hardware
platform. The General Purpose I/O (GPIO) core will be used for the LEDs on the board.
Objectives
This tutorial demonstrates how to create an embedded hardware platform for MicroBlaze using the Xilinx
Platform Studio (XPS) Base System Builder (BSB). The lab will show
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Requirements
The following items are required for proper completion of this tutorial.
Software
The following software setup is required for this reference design:
WindowsXP 32-bit Service Pack 2
Xilinx ISE WebPack with the EDK add-on or ISE Embedded Edition version 13.1
Installed Digilent Adept and Xilinx 3rd-party USB Cable driver (see Spartan-6 LX9 MicroBoard
Configuration Guide, listed in Recommended Reading, below)
Installed Silicon Labs CP210x USB-to-UART Bridge Driver (see Silicon Labs CP210x USB-toUART Setup Guide, listed in Recommended Reading, below)
Installation of the Spartan-6 LX9 MicroBoard IPXACT files (Available from Avnet:
http://em.avnet.com/s6microboard)
Hardware
The hardware setup used by this reference design includes:
Computer with a minimum of 300-900 MB (depending on O/S) to complete an XC6SLX9 design1
Avnet Spartan-6 LX9 MicroBoard Kit
o Avnet Spartan-6 LX9 MicroBoard
o USB Extension cable (if necessary)
o USB A-to-MicroB cable
Recommended Reading
Available from Avnet: http://em.avnet.com/s6microboard
The hardware used on the Spartan-6 LX9 MicroBoard is described in detail in Avnet document,
Spartan-6 LX9 MicroBoard User Guide.
An overview of the configuration options available on the Spartan-6 LX9 MicroBoard, as well as
Digilent driver installation instructions can be found in the Avnet document, Spartan-6 LX9
MicroBoard Configuration Guide.
Instructions on installing the Silicon Labs CP210x USB-to-UART drivers can be found in the
Avnet document, Silicon Labs CP210x USB-to-UART Setup Guide.
Refer to www.xilinx.com/ise/products/memory.htm
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Click Next
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Click Next.
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13. In the Cache Configuration window, For the Instruction Cache and the Data Cache, using the
drop-down list, select 2 KB for each. Click Next.
14. In the Summary Window, click on the Finish button to create the project. Click OK in the constraints
pop-up window.
MHS File. The Microprocessor Hardware Specification file contains the hardware
specification of the entire system. The MHS file contains the bus architecture, list of
peripherals, connectivity for the system, interrupt request priorities, and address space.
The MHS file can also call out custom IP.
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UCF File. The User Constraints File contains the timing and placement constraints for
the FPGA.
In previous versions of Platfrom Studio, several other key files were listed under Project Files; the MSS
file, Download.cmd, Fast_rutime.opt and Bitgen.ut. The MSS file is now managed by SDK in 13.1. The
other three files are managed by ISE in 13.1 since ISE is recommended to be the top-level design entry
tool.
3. The Addresses tab in the System Assembly View shows the address map for the system. The Bus
Interfaces tab show peripheral connections to the processor via the AXI interface. And the Ports tab
lists internal and external connections.
4. Click on the Block Diagram tab to view the block diagram for the project. The block diagram shows
the connections between the different busses and components in the system. Also, you can export
this Block Diagram to a jpeg image by clicking Project > Generate Block Diagram Image. This
image gets saved in your under your project in a folder named blockdiagram
5. A datasheet of the system can also be generated. Go to Project > Generate and View Design
Report to view the design report. This is an html file that is generated in a report subfolder.
6. To view the general project options go to Project > Project Options Click Cancel to close the
window.
7. To start a software project in SDK, the hardware design information needs to be exported. Go to
Project > Export Hardware Design to SDK Select Export Only.
The exported files are located in the SDK\SDK_Export\hw directory inside the XPS project directory. We
will use the files to create a new C application for our system.
8. Close XPS when finished.
9. Return to Project Navigator and Go to Project > Add Copy of Source to add the FPGA constraints
to the project.
10. Select mb_system.ucf in the mb_system\data directory. Click OK.
11. Select mb_system in the hierarchy window.
12. Double-click on Generate Top HDL Source in the Processes window. This is a new step in ISE
13.1. It creates a HDL instantiation template for your MicroBlaze processor subsystem and
instantiates into a new created top-level HDL entity, or module if using Verilog.
13. Select mb_system_top in the hierarchy window.
14. Double-click on Generate Programming File in the Processes window to implement the system.
Project Navigator may show files out of date after running, you can ignore this.
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More time will be spent on the different features of the SDK in the next tutorials. The steps below can be
done while Project Navigator is building the hardware.
1. Start Xilinx SDK. Start Programs Xilinx ISE Design Suite 13.1 EDK Xilinx Software
Development Kit.
2. Create a Workspace named WorkSpace in the EDK_Tutorial directory. Click OK.
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10. The Project Explorer View in SDK contains 3 projects: the hardware platform, the Board Support
Package, and the C application as shown below.
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16. Use the drop-down list to select the internal BRAM memory,
microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl, for all the code sections.
Click Generate then Yes.
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2. Plug the USB-UART cable between the MicroBoard and the PC.
Click OK.
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Click on Program
10. In the SDK Project Explorer View, right-click on the peripheral_tests_0 project and select Run As >
Run Configurations.
11. Select Xilinx C/C++ ELF and click on the New Launch Configuration icon.
The Run Configuration contains settings to run the application on the target board. We will change the
default settings to enable STDIO inputs and outputs on the SDK console.
12. In the SDK Run Configurations window, select the STDIO Connection tab.
13. Check the Connect STDIO to Console box.
14. Select the COM port from step 5 above and leave the BAUD Rate at 9600.
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