Static Timing Analysis

Techniques for FPGAs

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Static Timing Analysis

Techniques for FPGAs

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Why STA?

Verify the design meets timing constraints

Faster than timing-driven, gate-level simulation
Ease design debugging

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Timing In FPGAs
LatticeECP2/M Slice Diagram

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Agenda

Introduction to Static Timing Analysis

Elements of Timing Verification
Timing in FPGAs
Analysis Examples

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Overview

Design Flow
Dynamic Versus Static Simulation
Key Definitions

Critical Path
Arrival Time
Required Time
Slack

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Design Flow

New
Design

RTL
Development

Functional
Simulation

Synthesis

Post-Synthesis
STA

Place & Route

Post-PAR
STA

Timing
Simulation

Program
Device

Design
Complete

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Dynamic Versus Static Verification

Dynamic

Static

Difficult to cover all paths

9 Checks every path for timing violations

Typically time and compute intensive

9 Typical runtime is fast

Confirms function and timing

9 Confirms timing only

Supports asynchronous designs

9 Synchronous designs only

Simple timing checks

9 Min/Max, clock skew, exceptions

Ex: Mentor Graphics ModelSim

9Ex: Lattice Semiconductor trace program

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STA Compute Method

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Timing Paths

Path 1

Path 3

Path 2

Path 4

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Delay Calculation

Intrinsic

Extrinsic

Intrinsic

Intrinsic vs. Extrinsic Delay

Logic Gate Delay
Net Delay
y = mx + b

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Synchronous Circuit Delay Calculation

Skew

Skew

Skew

CLK

Time
remaining
for signal
propagation

Tsetup

Tpropagation = Tperiod - Tsetup

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Path Measurements
g2 to g8

Path

Signal Route

Delay

g2 to g8

g2(Tq) n3 g5 n5 g6 n6

12 + Tdq + Ts

g2 to g9

g2(Tq) n3 g5 n5 g7 n7

12 + Tdq + Ts

g4 to g8

g4(Tq) n4 g5 n5 g6 n6

12 + Tdq + Ts

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Constraint Checks

Min/Max Delay
Setup/Hold
Recovery/Removal
Clock Definitions

Gated Clocks
Clock Skews and Multiple Clock Groups
Multi-frequency Clocks
Multi-phase Clocks

False Paths
Multi-cycle Path Analysis

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Min/Max Delay

Path 4: primary input to primary output (Tpd)

================================================================================
Preference: MAXDELAY FROM PORT "in1" TO PORT "op1" 9.000000 ns ;
1 item scored, 0 timing errors detected.
-------------------------------------------------------------------------------Logical Details: Cell type Pin type
Cell/ASIC name (clock net +/-)
Source:
Port
Pad
in1
Destination:
Port
Pad
op1
Delay:

3.541ns

(63.2% logic, 36.8% route), 3 logic levels.

Constraint Details:
3.541ns physical path delay in1 to op1 meets
9.000ns delay constraint by 5.459ns
:
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Setup/Hold Basics
data

FF

clk

clk
t_m

ts

t_m

th

data

ts

th

Valid

Valid

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Setup/Hold Checking for Flip-Flops

PCBclk
Hold
check

Setup
check

Hold
check

FPGAclk

Primary input to reg (Ts)

PCB
?

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PCB Requirements for Setup/Hold

PDMAXb = 3 ns
PDMINb = 500 ns

PDMAXp = 9 ns
PDMINp = 1.5 ns

Lattice
FPGA

Port
Controller

9 pf input capacitance.
60 pf AC load
3 ns to 18 ns clk to out,
5 ns setup, 3 ns hold
P = 15 ns

Tskew = 500 ps
5 pf parasitic board capacitance

INPUT_SETUP = P (PDMAXp + PDMAXb + Tskew) = 15 (9 + 3 + 0.5) = 15 12.5 = 2.5 ns

HOLD = PDMINp + PDMINb - Tskew = 1.5 + 0.5 0.5 = 1.5 ns
PERIOD PORT "clk" 15 nS ;
INPUT_SETUP GROUP "ina" 2.5 ns HOLD 1.5 ns CLKPORT "clk" ;
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I/O Setup Analysis Example

Preference: INPUT_SETUP GROUP "ina" 2.500000 ns HOLD 1.500000 ns CLKPORT "clk" ; Setup Analysis.
16 items scored, 0 timing errors detected.
Passed:

The following path meets requirements by 2.582ns

Logical Details:
Source:
Destination:

Cell type
Port
FF

Max Data Path Delay:

Min Clock Path Delay:

Pin type
Pad
Unknown
0.542ns
1.527ns

Cell/ASIC name (clock net +/-)

ina(0)
GA_0 (to clk_int +)

(100.0% logic, 0.0% route), 1 logic levels.

(30.2% logic, 69.8% route), 1 logic levels.

Constraint Details:
0.542ns delay ina(0) to ina(0)_MGIOL less
2.500ns offset ina(0) to clk (totaling -1.958ns) meets
1.527ns delay clk to ina(0)_MGIOL less
0.903ns DI_SET requirement (totaling 0.624ns) by 2.582ns
Physical Path Details:
Data path ina(0) to ina(0)_MGIOL:
Name
PADI_DEL
ROUTE

Fanout
--2

Delay (ns)
Site
Resource
0.542
32.PAD to
32.PADDI ina(0)
0.000
32.PADDI to
IOL_B8A.DI ina_int(0) (to clk_int)
-------0.542
(100.0% logic, 0.0% route), 1 logic levels.

Clock path clk to ina(0)_MGIOL:

Name
PADI_DEL
ROUTE

Fanout
--24

Delay (ns)
Site
Resource
0.461
90.PAD to
90.PADDI clk
1.066
90.PADDI to
IOL_B8A.CLK clk_int
-------1.527
(30.2% logic, 69.8% route), 1 logic levels.

Report: There is no minimum offset greater than zero for this preference.

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I/O Hold Analysis Example

Preference: INPUT_SETUP GROUP "ina" 2.500000 ns HOLD 1.500000 ns CLKPORT "clk" ; Hold Analysis.
16 items scored, 16 timing errors detected.
Error:

The following path exceeds requirements by 0.631ns

Logical Details:
Source:
Destination:

Cell type
Port
FF

Min Data Path Delay:

Max Clock Path Delay:

Pin type
Pad
Unknown
0.461ns
2.014ns

Cell/ASIC name (clock net +/-)

ina(0)
GA_0 (to clk_int +)

(100.0% logic, 0.0% route), 1 logic levels.

(26.9% logic, 73.1% route), 1 logic levels.

Constraint Details:
0.461ns delay ina(0) to ina(0)_MGIOL plus
1.500ns hold offset ina(0) to clk (totaling 1.961ns) violates
2.014ns delay clk to ina(0)_MGIOL plus
0.578ns DI_HLD requirement (totaling 2.592ns) by 0.631ns
Physical Path Details:
Data path ina(0) to ina(0)_MGIOL:
Name
PADI_DEL
ROUTE

Fanout
--2

Delay (ns)
Site
Resource
0.461
32.PAD to
32.PADDI ina(0)
0.000
32.PADDI to
IOL_B8A.DI ina_int(0) (to clk_int)
-------0.461
(100.0% logic, 0.0% route), 1 logic levels.

Clock path clk to ina(0)_MGIOL:

Name
PADI_DEL
ROUTE

Fanout
--24

Delay (ns)
Site
Resource
0.542
90.PAD to
90.PADDI clk
1.472
90.PADDI to
IOL_B8A.CLK clk_int
-------2.014
(26.9% logic, 73.1% route), 1 logic levels.

Warning:

2.131ns is the minimum offset for this preference.

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Hold Analysis Example

Preference: INPUT_SETUP GROUP "ina" 2.500000 ns HOLD 1.500000 ns CLKPORT "clk" ;
16 items scored, 0 timing errors detected.
Passed: The following path meets requirements by 1.669ns
Logical Details: Cell type Pin type
Cell/ASIC name (clock net +/-)
Source:
Port
Pad
ina(7)
Destination:
FF
Data in
GA_7 (to pllclk +)
Min Data Path Delay:
0.436ns (44.7% logic, 55.3% route), 1 logic levels.
Max Clock Path Delay:
1.167ns (19.6% logic, 80.4% route), 2 logic levels.
Constraint Details:
0.436ns delay ina(7) to SLICE_3 plus
1.500ns hold offset ina(7) to clk (totaling 1.936ns) meets
1.167ns delay clk to SLICE_3 less
0.874ns feedback compensation less
plus
-0.026ns M_HLD requirement (totaling 0.267ns) by 1.669ns
Physical Path Details:
:
Report: There is no minimum offset greater than zero for this preference.

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Questions?

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Clock Definitions

Earliest rising edge

Tu = Clock uncertainty
Latest rising edge

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Polarity Skew

FF1clk

FF1

FF2

Td = Polarity skew

Td

FF2clk

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Polarity Skew Analysis Example

Preference: PERIOD PORT "clk" 3.000000 nS ;
32 items scored, 16 timing errors detected.
Error: The following path exceeds requirements by 0.379ns
Logical Details:
Source:
Destination:
Delay:

Cell type Pin type

Cell/ASIC name (clock net +/-)
FF
Q
FF1_9 (from clk_c +)
FF
Unknown
FF2_9_0io (to clk_c -)
1.896ns (31.1% logic, 68.9% route), 2 logic levels.

Constraint Details:
1.896ns physical path delay SLICE_4 to outa_9_MGIOL exceeds
1.500ns delay constraint less
0.125ns skew and
-0.142ns ONEG0_SET requirement (totaling 1.517ns) by 0.379ns
Physical Path Details:
Name
Fanout
Delay (ns)
Site
Resource
REG_DEL
--0.354
R3C2D.CLK to
R3C2D.Q1 SLICE_4 (from clk_c)
ROUTE
1
0.560
R3C2D.Q1 to
R4C2D.C0 n2_9
CTOF_DEL
--0.235
R4C2D.C0 to
R4C2D.F0 SLICE_14
ROUTE
1
0.747
R4C2D.F0 to IOL_L4A.ONEG0 n3_9 (to clk_c)
-------1.896
(31.1% logic, 68.9% route), 2 logic levels.
Clock Skew Details:
Source Clock:
Delay
1.597ns
Destination Clock:
Delay
1.472ns
Warning:

Connection
90.PADDI to R3C2D.CLK
Connection
90.PADDI to IOL_L4A.CLK

3.758ns is the minimum period for this preference.

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Phase Skew

FF1clk

FF1

FF2
Td = 45 degree phase skew

FF2clk

PLL
Td= 45 degree phase skew

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Phase Skew Analysis Example

Preference: FREQUENCY NET "FF1clk" 250.000000 MHz ;
16 items scored, 0 timing errors detected.
Passed: The following path meets requirements by 1.758ns
Logical Details:
Source:
Destination:
Delay:

Cell type Pin type

Cell/ASIC name (clock net +/-)
Port
Pad
ina_9
FF
Data in
FF1_9 (to FF1clk +)
2.129ns (25.5% logic, 74.5% route), 1 logic levels.

Constraint Details:
2.129ns physical path delay ina_9 to SLICE_4 meets
4.000ns delay constraint less
0.113ns M_SET requirement (totaling 3.887ns) by 1.758ns
:
Preference: FREQUENCY NET "FF2clk" 250.000000 MHz ;
16 items scored, 0 timing errors detected.
Passed: The following path meets requirements by 2.249ns
and meets 4.000ns delay constraint requirement for source clock "FF1clk"
by 2.249ns
Logical Details:
Source:
Destination:
Delay:

Cell type Pin type

Cell/ASIC name (clock net +/-)
FF
Q
FF1_7 (from FF1clk +)
FF
Unknown
FF2_7_0io (to FF2clk +)
2.323ns (25.4% logic, 74.6% route), 2 logic levels.

Constraint Details:
2.323ns physical path delay SLICE_3 to outa_7_MGIOL meets
4.000ns delay constraint less
-0.375ns skew and
0.000ns feedback compensation and
-0.197ns ONEG0_SET requirement (totaling 4.572ns) by 2.249ns
:

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Phase Skew Analysis Example

Clock Skew Details:
Source Clock Path:
Name
Fanout
Delay (ns)
Site
Resource
PADI_DEL
--0.542
19.PAD to
19.PADDI pllclk
ROUTE
1
0.000
19.PADDI to PLL3_R6C1.CLKI pllclk_c
CLK2OUT_DE --0.000 PLL3_R6C1.CLKI to LL3_R6C1.CLKOP I1/PLLBInst_0
ROUTE
9
1.874 LL3_R6C1.CLKOP to
R14C14B.CLK FF1clk
-------2.416
(22.4% logic, 77.6% route), 2 logic levels.
PLL3_R6C1.CLKOP attributes: FDEL = 0
Destination Clock Path:
Name
Fanout
Delay (ns)
Site
Resource
PADI_DEL
--0.542
19.PAD to
19.PADDI pllclk
ROUTE
1
0.000
19.PADDI to PLL3_R6C1.CLKI pllclk_c
CLK2P_DEL
--0.500 PLL3_R6C1.CLKI to LL3_R6C1.CLKOS I1/PLLBInst_0
ROUTE
16
1.749 LL3_R6C1.CLKOS to
IOL_B14A.CLK FF2clk
-------2.791
(37.3% logic, 62.7% route), 2 logic levels.
PLL3_R6C1.CLKOS attributes: PHASEADJ = 45, FDEL = 0
Source Clock f/b:
Name
Fanout
Delay (ns)
Site
Resource
CLKOP_DEL
--0.000 LL3_R6C1.CLKFB to LL3_R6C1.CLKOP I1/PLLBInst_0
ROUTE
9
1.749 LL3_R6C1.CLKOP to LL3_R6C1.CLKFB FF1clk
-------1.749
(0.0% logic, 100.0% route), 1 logic levels.
PLL3_R6C1.CLKOP attributes: FDEL = 0
Destination Clock f/b:
Name
Fanout
Delay (ns)
Site
Resource
CLKOP_DEL
--0.000 LL3_R6C1.CLKFB to LL3_R6C1.CLKOP I1/PLLBInst_0
ROUTE
9
1.749 LL3_R6C1.CLKOP to LL3_R6C1.CLKFB FF1clk
-------1.749
(0.0% logic, 100.0% route), 1 logic levels.
PLL3_R6C1.CLKOP attributes: FDEL = 0

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Frequency Skew
FF1clk

FF1

FF2
Td

Td = Frequency skew

FF2clk

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Frequency Skew Analysis Example

Preference: PERIOD PORT "FF1clk" 4.500000 nS ;
16 items scored, 0 timing errors detected.
Passed: The following path meets requirements by 2.745ns
Logical Details: Cell type Pin type
Cell/ASIC name (clock net +/-)
Source:
Port
Pad
ina(6)
Destination:
FF
Data in
FF1_6 (to FF1clk_int +)
Delay:
1.642ns (33.0% logic, 67.0% route), 1 logic levels.
Constraint Details:
1.642ns physical path delay ina(6) to SLICE_3 meets
4.500ns delay constraint less
0.113ns M_SET requirement (totaling 4.387ns) by 2.745ns
:
Report:

1.755ns is the minimum period for this preference.

Preference: PERIOD PORT "FF2clk" 2.000000 nS ;

16 items scored, 0 timing errors detected.
-------------------------------------------------------------------------------WARNING - trce: Clock skew between net 'FF1clk_int' and net 'FF2clk_int not computed:
nets may not be related
Passed: The following path meets requirements by 0.158ns and meets
4.500ns delay constraint requirement for source clock "FF1clk_int" by 2.658ns
Logical Details:
Source:
Destination:
Delay:

Cell type Pin type

Cell/ASIC name (clock net +/-)
FF
Q
FF1_12 (from FF1clk_int +)
FF
Unknown
FF2_12 (to FF2clk_int +)
2.039ns (28.9% logic, 71.1% route), 2 logic levels.

Constraint Details:
2.039ns physical path delay SLICE_6 to outa(12)_MGIOL meets
2.000ns delay constraint less
-0.197ns ONEG0_SET requirement (totaling 2.197ns) by 0.158ns
:
Report:

1.842ns is the minimum period for this preference.

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Frequency Skew Analysis Example

run 50 ns
# ** Warning: SLICE_0 SETUP High VIOLATION ON M1 WITH RESPECT TO CLK;
#
Expected := 0.113 ns; Observed := 0.107 ns; At : 71.883 ns
#
Time: 71883 ps Iteration: 1 Process: /testbench/uut/slice_0i/vitalbehavior File: ex1.vho
# Break in Process vitalbehavior at ex1.vho line 232

ModelSim
Design Planner

Source

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Cycle Skew

FF1clk

FF1

Td = Cycle skew

FF2

Td

FF2clk

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Cycle Skew Analysis Example

Preference: PERIOD PORT "clk" 3.000000 nS ;
32 items scored, 1 timing error detected.
Error: The following path exceeds requirements by 0.133ns
:
Constraint Details:
3.330ns physical path delay sel to outa_15_MGIOL exceeds
3.000ns delay constraint less
-0.197ns ONEG0_SET requirement (totaling 3.197ns) by 0.133ns
:
Preference: MULTICYCLE FROM GROUP "FF1" TO GROUP "FF2" 2.000000 X ;
16 items scored, 0 timing errors detected.
Passed: The following path meets requirements by 3.491ns
Logical Details:
Source:
Destination:
Delay:

Cell type Pin type

Cell/ASIC name (clock net +/-)
FF
Q
FF1_10 (from clk_c +)
FF
Unknown
FF2_10_0io (to clk_c +)
2.581ns (22.8% logic, 77.2% route), 2 logic levels.

Constraint Details:
2.581ns physical path delay SLICE_5 to outa_10_MGIOL meets
6.000ns delay constraint less
0.125ns skew and
-0.197ns ONEG0_SET requirement (totaling 6.072ns) by 3.491ns
:

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False Paths

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Analysis of Phase-Locked Loops

DLYa

Ta

DLYb

Tb

Tref

PLL
Tfb

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Timing Analysis By Stage

Preliminary Timing Analysis

Synthesis Timing Analysis
RTL vs. Gate-Level
Timing in RTL Code
Black-Box Timing Arcs

Place & Route Timing Analysis

Post-Map
Post-Placement
Post-Route

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Timing Parameters

Corners and STA

Timing Derating Factors
Grading FPGAs by Speed
Best-Case Delay Values

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19

Synthesis STA with Precision

Timing Specification
Native or Synopsys (SDC) Format

Analysis Commands
Timing Report

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Synthesis STA with Synplify

Timing Specification
Native Synplify Design Constraints

Analysis Commands
Timing Report

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Place & Route STA with ispLEVER

STA Setup, Project Navigator

TRACE Report
Routing Congestion with Design Planner
Viewing Critical Paths with Design Planner
I/O Timing Report

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Summary

Leverage STA engines throughout flow

Handle fundamentals: clocks and I/O timing
Advanced constraints for multicycle and blocks
Simulate or formal methods for clock domain crossing

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Resources

Actel, Static Timing Analysis Using Designers Timer, Application

Note. January 2004
Lattice Semiconductor, ispLEVER FPGA Design Guide. 2006
Lattice Semiconductor, LatticeEC FPGA Design with ispLEVER
Tutorial. 2006
Nekoogar, Timing Verification of Application-Specific Integrated
Circuits (ASICs), Prentice Hall PTR, 1999
Synopsys, Synopsys PrimeTime User Guide: Fundamentals. June
2006
Xilinx, Development System Reference Guide, 2005

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Thank You!
Interested in learning more ..

Lattice Semiconductor Corporation

www.latticesemi.com
1-800-Lattice [528-8423] North America
1-408-826-6002 Outside North America
[email protected]

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Questions?

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