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This document contains an exam for a CPSC 330 Fall 2013 class. It has 12 questions covering topics like prefixes for powers of 10, benchmark programs, CPU time equations, logic terms, Karnaugh maps, counter design, and speedup calculations. The questions test knowledge of computer architecture and performance concepts. Suggested answers are provided for all questions in the document.

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86 views8 pages

f13_3300_e1.pdf

This document contains an exam for a CPSC 330 Fall 2013 class. It has 12 questions covering topics like prefixes for powers of 10, benchmark programs, CPU time equations, logic terms, Karnaugh maps, counter design, and speedup calculations. The questions test knowledge of computer architecture and performance concepts. Suggested answers are provided for all questions in the document.

Uploaded by

Mohamed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CPSC 330 Fall 2013 -- Exam 1 <with answers>

No calculators or other aids.


1. Give the power of 10 associated with these prefixes. (1.5 pts. each)
exa
________
giga ________
kilo ________
mega ________
micro ________
milli ________
nano ________
peta ________

<answers>
+18, +9, +3, +6
-6, -3, -9, +15

2. Define "benchmark program" and give at least one example. (3 pts.)

<suggested answer>
A program used to measure performance on a computer system, e.g., Dhrystone

3.

Matching -- technology/performance terms. Write the correct term from the


list into each blank. (1.5 pts. each)
embedded computer
desktop computer
server
supercomputer

a. _________________
b. _________________
c. _________________
d. _________________
e. _________________
f. _________________

datapath
transistor
wafer
yield

throughput
CPU time
CPI
workload

arithmetic mean
harmonic mean
geometric mean
speedup

Linpack
Whetstone
Dhrystone
SPEC

a computer with highest performance and cost


a computer that provides computation, file storage,
and/or printing to multiple users across a network
the circular slice of silicon upon which integrated
circuits are built
the ratio of the execution times of two computer systems
used to summarize a set of normalized execution rates
a set of benchmark suites that are used to compare the
performance of various desktops and small servers

<answers>
supercomputer, server, wafer, speedup, geometric mean, SPEC

4. Give the CPU time equation and define the terms you use. (6 pts.)

<answer>
CPU time = IC * CPI * CCT

IC * CPI
or CPU time = -------CR
IC is instruction count
CPI is cycles per instruction
CCT is clock cycle time (which is equal to 1/CR)
CR is clock rate

5. Find the execution time for a program that executes 10 billion instructions on
a processor with an avg. CPI of 2.5 and a clock frequency of 2 GHz. (6 pts.)

<answer>
( 10 * 10^9 instructions ) * ( 2.5 cycles/instruction )
------------------------------------------------------- = 12.5 seconds
2 * 10^9 cycles/second

6. For the following workload and cycle values, find the average CPI. (3 pts.)
type
| freq cycles
-------+-------------alu
| 0.2
1
ld/st | 0.2
2
branch | 0.6
4

CPI = _____________________________

<answer>
CPI = .2*1 + .2*2 + .6*4 = 3

7. If a new compiler for the computer in question 6 could reduce the number of
instructions to 1/2 of the original total and alter the instruction frequencies
in the following manner, what would be the total speedup? (8 pts.)
type
| freq cycles
-------+-------------alu
| 0.5
1
ld/st | 0.25
2
branch | 0.25
4

<answer>
Note that there is a change in IC and CPI but not CCT.
New IC = 0.5 * original IC
New CPI = 0.5*1 + .25*2 + .25*4 = 2
IC * CPI * CCT
IC * 3 * CCT
Speedup = ------------------------ = ----------------- = 3
IC_new * CPI_new * CCT
.5*IC * 2 * CCT
(note that IC and CCT cancel out, so you did not need to know their values)

8. Consider enhancing a scalar machine by providing a vector mode, which is 8 times


faster than the normal mode of operation. If the percentage of vectorization is
60%, what is the overall speedup? (9 pts.)

<answer>
1
1
Overall speedup = ----------------- = ----------- -> simplifies to 40/19
f
.4 + .6/8
( 1 f ) + --s

9. Matching -- logic terms. Write the correct term into each blank. (1.5 pts. each)
minterm
sum of products
don't care
glitch
a. _________________
b. _________________
c. _________________
d. _________________
e. _________________
f. _________________
g. _________________
h. _________________

race condition
circuit depth
fan-in
fan-out

half adder
full adder
decoder
multiplexer

ALU
PLA
latch
flip-flop

register
shift register
RS latch
JK flip-flop

unused value that can be arbitrarily assigned 0 or 1


undesired signal lasting only a short time
a form of logical representation that employs a
logical OR of product terms
where the output of a circuit depends on small
differences in signal timing
the number of gates in a circuit that form the longest
path from any input to any output
a circuit in which n select values route one of 2**n
input values to the single output
a memory element in which the stored state can only
change once per clock cycle
a circuit that connects several flip-flops into a linear
structure where the output of each flip-flop can be
the input to either of its neighbors

<answers>
dont care, glitch, sum of products, race condition,
circuit depth, multiplexer, flip-flop, shift register

10. Simplify the following Karnaugh maps of function F. (7 pts.)


\ BC
A \ 00
01
11
10
+----+----+----+----+
0 | 1 | 0 | 1 | 1 |
+----+----+----+----+
1 | 0 | 0 | 1 | 0 |
+----+----+----+----+
\ CD
AB \ 00
01
11
10
+----+----+----+----+
00 | 1 | 0 | 0 | 0 |
+----+----+----+----+
01 | 1 | 1 | d | 1 |
+----+----+----+----+
11 | 1 | d | d | 0 |
+----+----+----+----+
10 | 1 | 0 | d | 0 |
+----+----+----+----+

F = fn(A,B,C) = _________________________

F = fn(A,B,C,D) = _______________________
d = don't care

<answers>
\ BC
A \ 00
01
11
10
+----+----+----+----+
0 | 1 | 0 | 1 | 1 |
+----+----+----+----+
1 | 0 | 0 | 1 | 0 |
+----+----+----+----+
\ CD
AB \ 00
01
11
10
+----+----+----+----+
00 | 1 | 0 | 0 | 0 |
+----+----+----+----+
01 | 1 | 1 | d | 1 |
+----+----+----+----+
11 | 1 | d | d | 0 |
+----+----+----+----+
10 | 1 | 0 | d | 0 |
+----+----+----+----+

F =

_ _
A*C

B*C

F =

_
A*B

_ _
C*D

11. Design a two-bit counter with the following repeated sequence: 0,1,3,2
(a) Give the state diagram. (3 pts.)
(b) Give the state transition table with current states QA(t) and QB(t), and
next states QA(t+1) and QB(t+1). (3 pts.)
(c) Give the simplified logic expressions for QA(t+1) and QB(t+1). (3 pts.)

<answers>

00
10

01
11

QA(t) QB(t) | QA(t+1) QB(t+1)


-------------+----------------0
0
|
0
1
0
1
|
1
1
1
0
|
0
0
1
1
|
1
0

QA(t+1) = QB(t)
_____
QB(t+1) = QA(t)

12. Design a three-bit counter with the following repeated sequence: 0,1,3,7,6,4
(a) Give the
(b) Give the
and next
(c) Give the
(6 pts.)

state diagram. (4 pts.)


state transition table with current states QA(t), QB(t), and QC(t),
states QA(t+1), QB(t+1), and QC(t+1). (4 pts.)
simplified logic expressions for QA(t+1), QB(t+1), and QC(t+1).

<answers>

000
(unused states)
100

001
010

110

011
111

QA(t) QB(t) QC(t) | QA(t+1) QB(t+1) QC(t+1)


-------------------+------------------------0
0
0
|
0
0
1
0
0
1
|
0
1
1
0
1
0
|
d
d
d
0
1
1
|
1
1
1
1
0
0
|
0
0
0
1
0
1
|
d
d
d
1
1
0
|
1
0
0
1
1
1
|
1
1
0

\ QB*QC
QA \ 00
01
11
10
+----+----+----+----+
0 | 0 | 0 | 1 | d |
+----+----+----+----+
1 | 0 | d | 1 | 1 |
+----+----+----+----+

QA(t+1) = QB(t)

\ QB*QC
QA \ 00
01
11
10
+----+----+----+----+
0 | 0 | 1 | 1 | d |
+----+----+----+----+
1 | 0 | d | 1 | 0 |
+----+----+----+----+

QB(t+1) = QC(t)

101

\ QB*QC
QA \ 00
01
11
10
+----+----+----+----+
0 | 1 | 1 | 1 | d |
+----+----+----+----+
1 | 0 | d | 0 | 0 |
+----+----+----+----+

_____
QC(t+1) = QA(t)

Extra Credit. (5 pts.)


Consider two independent enhancements with speedups s1 and s2, respectively. Let
normal execution time be partitioned into a fraction f1 for which only the first
enhancement is applicable, a fraction f2 for which only the second enhancement is
applicable, and the remaining amount (1-f1-f2) for which neither are applicable.
Note: there is no fraction of normal execution time in which both are applicable.
Derive the overall speedup equation in terms of s1, s2, f1, and f2.
<answer>
+---------------+--------------+----------+
| 1 f1 f2 |
f1
|
f2
|
+---------------+--------------+----------+
+---------------+-------+---------+
| 1 f1 f2 | f1/s1 | f2/s2 |
+---------------+-------+---------+
1
Overall speedup = ------------------------------f1
f2
( 1 f1 f2 ) + ---- + ---s1
s2

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