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Lab 1 Report

The document describes modeling a 4-bit ALU and sequencer using VHDL code. For part 1, it models an 8-bit sequencer circuit using VHDL and verifies the design works as expected by simulating the output over time. For part 2, it models a 4-bit ALU that performs logic and arithmetic operations on two 4-bit inputs based on a 3-bit control signal. The VHDL code implements the different operations and outputs the result along with carry/overflow flags.

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146 views

Lab 1 Report

The document describes modeling a 4-bit ALU and sequencer using VHDL code. For part 1, it models an 8-bit sequencer circuit using VHDL and verifies the design works as expected by simulating the output over time. For part 2, it models a 4-bit ALU that performs logic and arithmetic operations on two 4-bit inputs based on a 3-bit control signal. The VHDL code implements the different operations and outputs the result along with carry/overflow flags.

Uploaded by

Nguyễn Thắng
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
You are on page 1/ 7

1.

PART 1
a. Hardware modelling using VHDL code

Figure 1: The secquencer

VHDL code for the secquencer of Figure 1 is shown below:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Part1 is
port ( x : out STD_LOGIC_VECTOR (0 to 7);
reset : in STD_LOGIC;
clock : in STD_LOGIC);
end Part1;
architecture behavioral of Part1 is
signal temp_x : STD_LOGIC_VECTOR (0 to 7):="00000000";
begin
process (clock,reset)
begin
if reset='1' then
temp_x(0) <='0'; temp_x(1) <= '0';temp_x(2) <=
'0';temp_x(3) <= '0';temp_x(4) <= '0';temp_x(5) <= '0';temp_x(6) <=
'1';temp_x(7) <= '0';
elsif (clock ='1' and clock'event) then
temp_x(0) <= temp_x(7);
temp_x(1) <= temp_x(0);
temp_x(2) <= temp_x(7) xor temp_x(1);
temp_x(3) <= temp_x(2);
temp_x(4) <= temp_x(3);
temp_x(5) <= temp_x(4);
temp_x(6) <= temp_x(5);
temp_x(7) <= temp_x(6) xor temp_x(7);
end if;
end process;
x <= temp_x;
end behavioral;

b. Synthesize result

==============================================================
*
Advanced HDL Synthesis Report
*
==============================================================
Macro Statistics
# Registers
: 8
Flip-Flops
: 8
# Xors
: 2
1-bit xor2
: 2
==============================================================
*
Final Report
*
==============================================================
Final Results
RTL Top Level Output File Name
: Part1.ngr
Top Level Output File Name
: Part1
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: No
Design Statistics
# IOs
: 10
Cell Usage :
# BELS
: 2
#
LUT2
: 2
# FlipFlops/Latches
: 8
#
FDC
: 7
#
FDP
: 1
# Clock Buffers
: 1
#
BUFGP
: 1
# IO Buffers
: 9
#
IBUF
: 1
#
OBUF
: 8
==============================================================

Comments: The synthesized result contains 8 flip-flops and 2 LUT (2 xor gates) which are
the same as the given circuit.

c. Simulating result
Explaination: Flip-flops are triggered by the edge of the clock. Possitive edge flip-flops sample
the input only at the possive edges of the clock. There are 2 possitve states in this case
(temp_x(n) can only take 0 or 1), the initial value for temp_x is 00000000 as required.
Transition between these states have to occur at the possitive edge of the clock.
Testbench code is shown below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Part1testbench is
end Part1testbench;
architecture behavioral of Part1testbench is
component Part1
port ( x : out STD_LOGIC_VECTOR (0 to 7);
reset : in STD_LOGIC;
clock : in STD_LOGIC);
end component;
signal reset: STD_LOGIC := '0';
signal clock : STD_LOGIC := '0';
signal x : STD_LOGIC_VECTOR (0 to 7);
constant clock_period : time := 10 ns; --clock period
begin
uut: Part1 PORT MAP (x => x,
reset => reset,
clock => clock);
clock_process: process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
stim_proc: process
begin
wait for 100 ns; --initial result should be 00000000
reset <='1';
wait for 10 ns; -- first flip-flop, the result should be 00000010
reset <='0';
wait for 10 ns; -- the result should be 00000001
reset <= '1';
wait for 10 ns;-- the result should be 00000010 and so on.
reset <= '0';
wait;
end process;
end;

As we can see for the Figure 2, the value of x vector has been change at every clock edge. The
output is clearly the same as expected.

Figure 2: Simmulation result

2. PART 2
a. Hardware modelling of 4-bit ALU

Figure 3: Block diagram of 4-bit ALU

VHDL code for 4-bit ALU with given function is shown below
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

entity lab1alu is
Port ( M : in STD_LOGIC;
S : in STD_LOGIC_VECTOR(1
A : in STD_LOGIC_VECTOR(3
B : in STD_LOGIC_VECTOR(3
Co : in STD_LOGIC;
F : out STD_LOGIC_VECTOR(3
Cout : out STD_LOGIC;
Flag : out STD_LOGIC);
end lab1alu;

DOWNTO 0);
DOWNTO 0);
DOWNTO 0);
DOWNTO 0);

architecture Behavioral of lab1alu is


signal Arithmetic
: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
signal Arithmetic_shift : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
signal Logical_shift : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
signal Sum
: STD_LOGIC_VECTOR ( 4 DOWNTO 0);
signal Sub
: STD_LOGIC_VECTOR ( 4 DOWNTO 0);
begin
Arithmetic <= S & Co;
Logical_shift <= '0' & A(3 DOWNTO 1);
Arithmetic_shift <= B(3) & B(3 DOWNTO 1);
Sum <= ( '0' & A) + ('0' & B) + Co;
Sub <= ( '0' & A) - ('0' & B);

process ( S, M, Co, A, B, Arithmetic)


begin
Flag <= '0' ;
Cout <= '0' ;
-- Logical Operation --------------------------------------if ( M = '0' ) then
case S is
when "00" => F <= A and B;
when "01" => F <= A or B;
when "10" => F <= A xor B;
when "11" => F <= A xnor B;
when others => F <= "0000";
end case;
-- Arithmetic Operation -----------------------------------elsif ( M = '1' ) then
case Arithmetic is
when "000" => F <= Logical_shift;
when "001" => F <= Arithmetic_shift;
when "010" => F <= Sum ( 3 DOWNTO 0 );
when "011" => F <= Sum ( 3 DOWNTO 0 );
if ( Sum(4) = '1' )
then Cout <= Sum(4); -- Present the extra bit----else Cout <= '0';
end if;
when "100" => F <= Sub ( 3 DOWNTO 0 );
if ( Sub(4) = '1' )
then Flag <= '1'; -- Indicate overflow -----------else Flag <= '0';
end if;
when "101" => F <= A + not B + 1;
-- 2 compliment subtraction
when others => F <= "0000";
end case;
end if;
end process;
end Behavioral;

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