VISHAY SILICONIX

Power MOSFETs

Application Note 833

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler
By Patrick Chiang and Mark Hu

Abstract
This application note will analyze the switching behavior of
synchronous rectifier MOSFETs in a phase-shifted
full-bridge converter topology with a current doubler.
Figure 1 shows the basic circuit of this application. An
overview will describe the timing diagram of a
phase-shifted full-bridge converter for achieving zero
voltage switching (ZVS). Two topologies are introduced for
gate driving of synchronous rectifier (SR) MOSFETs. The
timing diagrams will introduce the SR MOSFET operations
during every stage for both topologies. The body diode will
be highlighted, and the operational phenomena that occur
when the SR MOSFET turns off will be described. The
power dissipation of SR MOSFETs will be presented as
equations to assist in designs, while test results of
waveforms will help in understanding the application. A

summary will include the advantages of SR MOSFETs, an

efficiency comparison, and other design considerations.
L1
+

+
QA

SA

SR1

SC
Lr

Vi

Cb
QB

SB
-

Q1

QC

C0

T1
-

VT
Q2

QD

SR2

SD
-

L2

Figure 1 - Phase-Shifted Full-Bridge Converter

Introduction to the Phase-Shifted Full-Bridge Converter

The phase-shifted full-bridge converter introduces an

almost 50 % fixed-duty cycle to QA, QB, QC, and QD. The
pulse width modulation (PWM) duty is controlled by the
overlapped duty of QA and QD, and QB and QC. There is a
small amount of overlap between QA and QB, and QC and
QD, which is called PWM delay (PWM delay AB, and
PWM delay CD). PWM delay will prevent the same-side
MOSFETs (QA and QB, or QC and QD) from turning on
simultaneously, which would result in a short circuit that
burns out the MOSFETs. In addition, the delay time helps
Document Number: 69747
Revision: 11-Oct-07

the MOSFETs to achieve zero voltage switching (ZVS).

When the PWM pulse is off, the snubber inductance Lr, by
way of storage energy, will resonate with the output
capacitances of the MOSFETs and oscillate the MOSFET
voltage to zero before the MOSFETs turn on at the next
period. At this stage, ZVS (which means no switching loss)
occurs and a significant improvement in efficiency is
gained.
Due to high density (per W/inch3) and thermal
considerations, most designers do not add an external
snubber inductor in conjunction with the transformer
(shown in Figure 1). The snubber inductance Lr results from
the leakage inductance of transformer T1. Only if the
primary current Ip is enough to let Lr be stored at a
minimum energy, and an achieved ZVS transition, is the
external inductor not necessary. Using the leakage
inductance of the transformer, most power supplies can
achieve ZVS with more than 50 % maximum load. It is
necessary to add Cb to avoid an unbalance of the
transformer flux and saturation of the transformer.
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1

APPLICATION NOTE

The phase-shifted full-bridge converter has long been used

to achieve high efficiency and high density in power supply
designs with outputs from 500 W to 5000 W. The traditional
full-bridge converter transfers power from primary bulk
capacitors to secondary LC filters when its MOSFETs (QA
and QD, or QB and QC) are turned on at the same time. This
operation results in increased power dissipation (known as
switching loss) when a primary MOSFET is turned on and
off. The higher the switching frequency, the greater the
switching losses.

Application Note 833

Vishay Siliconix

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler
Resonant Operation of ZVS
The second criterion for achieving ZVS is that the delay
time is long enough to allow resonant voltages to finish
the energy transfer in COSS and Lr. Assuming the
1
-.
frequency of the resonant is Fr, one period time Tr is -----

The first criterion for achieving ZVS is

1
2 1
2
--- Lr Ip > --- Cr Vi
2
2

where Cr = 8--- C OSS + Cxfm ,

3

Fr

if Cxfrm is small and negligible with comparison to COSS,

8
Cr = --- C OSS .
3

1
2 4
2
--- Lr Ip > --- C OSS Vi
2
3

Designers may measure the IDS and VDS of a MOSFET to

find out at which output load ZVS of the MOSFET starts
to happen (for example, 40 %). If Lr is the leakage
inductance of the transformer, the LCR meter can measure
Lr by shorting the secondary wire. Adequate Ip stores the
energy and, by way of Lr, forces the VDS of the MOSFET
to zero before the MOSFET turns on.
In Figures 2 and 3, the primary current is Ip and a > b > c.
The critical point is Ip = b. That is
1
4
2
2
--- Lr b = --- C OSS Vi, max b =
2
3

8 C OSS Vi, max

--- ------------------------------------------Lr
3

If Ip b, the MOSFET can achieve ZVS. If Ip < b, ZVS is

not possible.
Vi = max

ZVS Point

Ip = c

Figures 2 and 3 show the voltage waveforms of the

resonant transitions. Figure 2 occurs while the COSS of the
MOSFET discharges from Vi = max to zero. Figure 3
occurs while the COSS of the MOSFET charges from
Vi = zero to max. The boundary condition occurs when
Ip = b. The delay time must be equal to or greater than tb,
or the MOSFET cannot achieve ZVS. Designers may
choose to let the delay time be equal to ta, and have no
ZVS in light loads. The criteria of the duty cycle is
Dutymaximum + Dutydelay = 50 % switching period.
The larger delay time will cause the maximum duty cycle
to be smaller, impacting the hold-up time performance.
The power transition from Lr to COSS needs to be
completed to achieve ZVS. The minimum time is
one-fourth of the resonant period.
1
tb = --- Tr
4
1
1
Tr = ------ , Fr = -----------------------------------------Fr
2 Lr Cr

tb = --- Lr Cr
2

Ip = b
Ip = a
Vi = 0
ta
tb

APPLICATION NOTE

Figure 2 - COSS Discharging Waveform

tb
ta
Vi = max

Ip = a
Ip = b
Ip = c

ZVS Point

Vi = 0

Figure 3 - COSS Charging Waveform

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Document Number: 69747

Revision: 11-Oct-07

Application Note 833

Vishay Siliconix

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler
L1
+

SA

+
QA
SA

QC

Q1
SR1

SC

Co
T1

SB

QB

Delay A/B

VT
(=Max.)

Vi

SB

Q2

QD

Duration
t0
t1

SR2

SD

SC

L2
L1
+

SD

+
QA
SA

QC

Q1
SR1

SC

Co
T1
VT
(=0)

Vi

Delay C/D

QB

VT

SB

Q2

QD

Duration
t1
t2

SR2

SD

L2

t7 t0

t1 t2

t3 t4

t5 t6

t7 t0

t1 t2

L1
+

L1

+
QA
SA

QC

Q1

SR1

SC

+
QA
SA

Co

QC
SC

T1

QB
SB

Q2

QD
SD

VT
(=0)

Vi

QB

Duration
t2
t3

SR2

Co
T1

VT
(=0)

Vi

SB

Q2

QD
SD
-

L2
L1

+
QA
SA

QC

Q1

SR1

SC

+
QA
SA

Co

QC

Q2

QD
SD

QB

Duration
t4
t5

SR2

VT
(=0)

Vi

SB

Q2

QD
SD
-

L2
L1
+

L2
L1

+
QA
SA

QC

Q1

SR1

SC

+
QA
SA

Co

QC

SB

Q2

QD

Co

QB
SB
-

VT
(=0)

Vi

Duration
t6
t7

SR2

SD

SR1

T1
VT
(=0)

QB

Q1

SC

T1
Vi

Duration
t5
t6

SR2

Q2

QD

Duration
t7
t0

SR2

SD
-

L2

L2

Figure 4 - Schematic Operation of Phase-Shifted Full-Bridge PWM Control

Document Number: 69747
Revision: 11-Oct-07

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3

APPLICATION NOTE

SB

Co
T1

VT
(=-Max.)
QB

Q1
SR1

SC

T1
Vi

Duration
t3
t4

SR2

L2
L1
+

Q1
SR1

Application Note 833

Vishay Siliconix

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler
Schematic Operation and Description
Timeframe t0 t1:
At the beginning of this timeframe, QD has already turned
on and the VDS of QA is zero. QA starts to turn on when
the VDS equals zero. The primary current is flowing
through QA, T1, and QD as shown in Figure 4. The power
transfers from the Vi source tank to the VT of the
secondary PWM pulse source by way of transformer T1.
Timeframe t1 t2:
Inductance Lr exists inside of transformer T1. The
characteristics of inductance will keep the current Ip in the
same direction. If there is no passive component in the
current loop of Ip, the value of Ip will remain the same
with no energy loss. At t1, QD turns off. The stored energy
of Lr forces Ip to keep flowing with its value at t1. This
action will start to charge the COSS of QD and discharge
the COSS of QC as shown in Figure 4. If the Ip is adequate
as shown in Figure 4, the voltage of drain of QD, or source
of QC, will resonate from Vi, max to zero. The ZVS
transition will finish within one-fourth of the resonant
cycle. After the voltage of drain of QD, or source of QC,
reaches zero, the current Ip stops flowing through the
COSS. It turns on the body diode of QC and Ip keeps
flowing.
Timeframe t2 t3:
At t2, QC starts to turn on. Ip transfers the current path
from the body diode of QC to the MOSFET QC. As shown
in Figure 4, the Ip current will keep flowing through QA,
T1, and QC with almost the same value, which means the
resistance loss is very low.

APPLICATION NOTE

Timeframe t3 t4:
At t3, QA turns off. The stored energy of Lr forces Ip to
keep flowing with its value at t3. This action will start to
charge the COSS of QA and discharge the COSS of QB as
shown in Figure 4. If the Ip is adequate as shown in Figure
4, the voltage of source of QA, or drain of QB, will
resonate from Vi, max to zero. The ZVS transition will
finish within one-fourth of the resonant cycle. After the
voltage of source of QA, or drain of QB, reaches Vi, max,
the current Ip stops flowing through the COSS. It turns on
the body diode of QB and keeps flowing.
Timeframe t4 t5:
QC has already turned on and the VDS of QB is zero. QB
starts to turn on when its VDS is zero. The primary current
is flowing through QA, T1, and QD as shown in Figure 4.
The power transfers from the Vi source tank to the VT of
the secondary PWM pulse source by way of transformer
T1.
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4

Timeframe t5 t6:
Inductance Lr exists inside of transformer T1. The
characteristics of inductance will keep the current Ip in the
same direction. If there is no passive component in the
current loop of Ip, the value of Ip will remain the same. At
t1, QC turns off. The stored energy of Lr forces Ip to keep
flowing with its value at t5. This action will start to charge
the COSS of QC and discharge the COSS of QD as shown in
Figure 4. If the Ip is adequate as shown in Figure 4, the
voltage of drain of QD, or the source of QC, will resonate
from Vi, max to zero. The ZVS transition will finish
within one-fourth of the resonant cycle. After the voltage
of drain of QD, or the source of QC, reaches zero, the
current Ip stops flowing through the COSS. It turns on the
body diode of QD and Ip keeps flowing.
Timeframe t6 t7:
At t6, QD starts to turn on. Ip transfers the current path
from the body diode of QD to the MOSFET QD. As
shown in Figure 4, the Ip current will keep flowing
through QB, T1, and QD with almost the same value,
which means the resistance loss is very low.
Timeframe t7 t0:
At t7, QB turns off. The stored energy of Lr forces Ip to
keep flowing with its value at t3. This action will start to
charge the COSS of QB and discharge the COSS of QA as
shown in Figure 4. If the Ip is adequate as shown in Figure
4, the voltage of drain of QB, or the source of QA, will
resonate from zero to Vi, max. The ZVS transition will
finish within one-fourth of the resonant cycle. After the
voltage of drain of QB, or the source of QA, reaches Vi
max, the current Ip stops flowing through the COSS. It
turns on the body diode of QA and keeps flowing.

Primary Circuit Application and Consideration:

a. With adequate Ip, the primary MOSFETs of a
phase-shifted full-bridge converter switch will show no
dissipation at the turn-on stage, i.e. ZVS. However, the
power dissipation at the turn-off stage cannot be avoided.
r = 2 Fr, ta , Ip = a

which refers to Figure 3.

Vi, a is the maximum voltage when Ip = a.

4
1
2
2
--- Lr a = --- C OSS Vi, a Vi, a =
3
2

3 Lr a
--- -----------------8 C OSS

Document Number: 69747

Revision: 11-Oct-07

Application Note 833

Vishay Siliconix

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler
To calculate ta is to find the time Vi, a(t) = Vi, max
1 Vi, max
sin --------------------
Vi, a
Vi, a sin ( r ta ) = Vi, max ta = --------------------------------------r
ta

ta

ta

Vi, a a
1
1
Pat = ----- ( Vi, a(t) Ip )dt = ---- ( Vi, a ( sin t ) Ip )dt = --------------------- ( sin r t )dt
ta
ta
ta
Vi, a a
Pat = --------------------- ( 1 cos ( r ta ) ) Pat
ta r

= power dissipation in the transition period.

The power dissipation of a MOSFET at turn-off is Pa, off (TSW is switching period).
Vi, a a
Vi, a a
ta
Pa, off = ----------- --------------------- ( 1 cos ( r ta ) ) Pa, off1 = ----------------------- ( 1 cos ( r ta ) )
T SW r
T SW ta r

If Ip=b, then
1

Vi, b = Vi, max; tb = ------------- tb = --------------4 fr

2 r
2
Pat = --- Vi, max b

where r = 2 f r

max b
and Pa = Vi,
----------------------------T SW r

b. When the MOSFETs and the transformer start the

resonant transition, energy is sometimes lost. The rDS(on),
the forward drop voltage of the body diode, the
parasitical resistance in the PCB, and the wire resistance
of the transformer gradually dissipate the energy stored
as inductance. Some stored energy is dissipated in the
time interval of the C/D resonant transition delay and the
PWM-off transition. The stored energy of the A/B
resonant transition delay will be smaller than that of the
C/D resonant transition delay. Thus, it is easier to achieve
ZVS in the C/D resonant transition delay than the A/B
resonant transition delay. That is why the case thermal
data of MOSFETs QA and QB are always higher than QC
and QD.

c. Thermal considerations in light loads are a problem.

Phase-shifted control enlarges the overlap waveforms of
the MOSFET voltage and current in light loads. That
means power losses will increase tremendously in this
situation, because there is no ZVS and Ip keeps the
voltage of the MOSFET at a high value before switching.
Even worse, most current power supplies specify smaller
airflow under light output load conditions as a way of
reducing acoustic noise. The case temperature of the
MOSFET will be very high. Designers should do thermal
testing around 10 % to 40 % of the load and check the
data carefully. Be sure to meet the de-rating guidelines of
the customer's specifications. Designers may set a
variable step value for delay A/B and delay C/D. Sensing
the primary current, the controller changes to a longer
delay time in light loads. The longer transition time can
reduce the power losses in the MOSFET.

APPLICATION NOTE

Document Number: 69747

Revision: 11-Oct-07

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5

Application Note 833

Vishay Siliconix

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler
Control Drivers of Synchronous Rectifier With Current Doubler
L1
+

+
QA
SA

SC

VT

QC
Co

D1

T1

VD1

turn off

turn on

turn off

VD2

turn on

turn off

turn on

Lr
Vi

VT
QB

QD

SB

Ls

Cb

D2
ID1

SD

ID2
t7 t0

L2

t1 t2

t3 t4

t5 t6

t7 t0

t1 t2

Figure 5 - Schematic Operation of Diode Rectifier

The secondary side acts as a buck converter. The diodes

act as switchers by following the power transferring from
the primary side. When VT is positive, D1 will
automatically turn off. When VT is negative, D2 will
automatically turn off.
Synchronous rectifiers can replace diode rectifiers. That
is, control drivers of synchronous rectifiers behave as
diode rectifiers. Because the product of the average
current Id and rDS(on) is much lower than the VF of the

diode, higher efficiency can be achieved by using the SR

topology. The SR MOSFET, however, must be controlled
to turn on and perform in the zone of the diode turn-on as
shown in Figure 5. If SR1 turns on before t1 and turns off
after t0, the sudden short circuit of Q1 and Q2 will result
in their burning out and damaging other components.
Two types of control drivers have been introduced in
today's application.

Type 1 SR Driver

APPLICATION NOTE

Designers may put the phase-shifted full-bridge controller

in the secondary side of the main transformer. In this
scenario, the control driver of the synchronous rectifier is
built up without an insulation transformer. See Figure 6.
SR1 is controlled "off" in t1 and t2, and t7 and t0,
providing a delay that avoids the short circuit of Q1 and
Q2 and results in optimal efficiency.

SA

current driver

SR2
SD
SB

current driver

SR1
SC

Figure 6 - Schematic Diagram of Type 1 Synchronous Rectifier

TRUTH TABLE OF TYPE 1 SYNCHONOUS RECTIFIER

STATE
t0 t1
t1 t2
t2 t3
t3 t4
t4 t5
t5 t6
t6 t7
t7 t0

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6

SA
H
H
H
L
L
L
L
L

PRIMARY GATE SIGNAL

SB
SC
L
L
L
L
L
H
L
H
H
H
H
L
H
L
L
L

SD
H
L
L
L
L
L
H
H

SR INPUT SIGNAL
SR1
SR2
L
H
L
H
H
H
H
L
H
L
H
L
H
H
L
H

Document Number: 69747

Revision: 11-Oct-07

Application Note 833

Vishay Siliconix

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler
L1
+

SA

+
QA
SA

QC

Q1
SR1

SC

Co
T1
-

VT
(=Max.)

Vi

SB
QB
SB

t0

Q2

QD

SR2

SD

t1

Delay A/B

L2
L1
+

+
QA
SA

QC

SC

Q1
SR1

SC
T1

VT
(=0)

Vi

QB

SD

SB

t1

Q2

QD

SR2

SD

t2

L2
L1

Delay C/D

+
QA
SA

QC

Q1
SR1

SC
T1

VT

VT
(=0)

Vi

QB
SB

t2

Q2

QD

SR2

SD

t3

L2
L1

SR1
+

+
QA
SA

QC
SC

SR2

Q1
SR1

T1
VT
(=0)

Vi

QB

VQ1

SB

t3

Q2

QD

SR2

SD

t4

L2
L1

VQ2
+

+
QA
SA

Body diode of
Q1 turn on

QC
SC

Body diode of
Q1 turn on

Q1
SR1

T1

IQ1
Body diode of
Q2 turn on

VT
(=-Max.)

Vi

QB
SB

t4

Q2

QD

SR2

SD

t5

L2
L1

IQ2
+

+
QA
SA

QC

T1
VT
(=0)

Vi

QB

IL2

SB

t1 t2

t3 t4

t5 t6

t7 t0

SR2

t6

t1 t2

L2
L1

L1
+

+
QA
SA

QC

Q1

SC

+
QA
SA

QC

QB

T1
VT
(=0)

SB

Q1

SC

T1
Vi

t5

Q2

QD
SD

t7 t0

t6

Q2

QD
SD

t7

VT
(=0)

Vi

QB
SB
-

t7

Q2

QD
SD

t0

L2

L2

Figure 7 - Schematic Operation of Phase-Shifted Full-Bridge PWM Control With Type 1 SR Driver
Document Number: 69747
Revision: 11-Oct-07

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7

APPLICATION NOTE

IL1

Q1
SR1

SC

Application Note 833

Vishay Siliconix

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler
Schematic Operation and Description With Type 1 SR Driver
Timeframe t0 t1:
QA and QD are turned on and power is transferred from
the primary side to the secondary side. SR2 is already
turned on. No current flows through Q1. Q2 will take all
the transferring current flow through itself. However,
before t0, the body diode of Q1 is turned on. At t0, forcing
the body diode of Q1 to turn off will cause a diode
reverse-recovery condition. The high spike voltage of Q1
VDS and the turn-off switching loss occur.
Assuming output inductors (L1 and L2) both work in
continuous mode, the currents of L1 and L2 will keep
flowing in the same direction. Two paths of current flow
are separated through L1 and L2. The current of L1 is
increasing by the forced voltage VT, and that of L2 is
decreasing with the freewheeling stored energy in L2.
Timeframe t1 t2:
At t1, the forced voltage is off and transfers from the
maximum value to zero voltage. In this short time, Q1 VDS
will reach zero voltage and the Q1 body diode will turn on.
Since the primary Ip keeps almost the same value, the
current of the secondary side transformer is almost the
same value as at t1. Therefore, the current of body diode
Q1 will start at zero current and increase slowly. Besides
the two current paths in the timeframe t0 t1, the current
through the Q1 diode and L1 is the third path.
Timeframe t2 t3:
At t2, SR1 starts to turn the Q1 MOSFET on. Because the
body diode of Q1 is already turned on, the VDS of Q1 is
zero. ZVS occurs in the turn-on switching of Q1. The
three current paths are the same as those of timeframe
t1 t2. The third one, however, is not flowing through
the Q1 diode, but the Q1 MOSFET.

APPLICATION NOTE

Timeframe t3 t4:
At t3, the voltage of QA source or QB source is resonated
from the maximum value to zero voltage. In this short
time, the VDS of QB will reach zero voltage and the body
diode will turn on. Since the primary IP keeps almost the
same value, the current of the secondary side transformer
is almost the same value as at t1. Therefore, the current
of the body diode Q2 will take all the current of the
Q2 MOSFET at t3. The three current paths are the same as
those of timeframe t2 t3. However, the path through
MOSFET Q2 is changed through the body diode of Q2.

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8

Timeframe t4 t5:
QB and QC are turned on. SR2 is already turned on. There
is no current flow through Q2. Q1 will take all the
transferring current flow through itself. However, before
t4, the body diode of Q2 is turned on. The high spike
voltage of Q1 VDS and the turn-off switching loss occur.
Two paths of current flow are separated through L1 and
L2. The current of L2 is increasing by forced voltage VT,
and that of L1 is decreasing with the freewheeling stored
energy in L2.
Timeframe t5 t6:
At t5, the forced voltage VT is off and transfers from the
maximum value to zero voltage. In this short time, Q2 VDS
will reach zero voltage and the Q2 body diode will turn on.
Since the primary IP keeps almost the same value, the
current of the secondary side transformer is almost the
same value as at t1. Therefore, the current of body diode
Q2 will start at zero current and increase slowly. Besides
the two current paths in timeframe t4 t5, the current
through the Q2 diode and L2 is the third path.
Timeframe t6 t7:
At t6, SR2 starts to turn the Q2 MOSFET on. Because the
body diode of Q2 is already turned on, the VDS of Q2 is
zero. ZVS occurs in the turn-on switching of Q2. The
three current paths are the same as those of timeframe
t5 t6. The third one, however, is not flowing through
the Q2 diode, but the Q2 MOSFET.
Timeframe t7 t0:
At t7, the voltage of QA source or QB source is resonated
from the maximum value to zero voltage. In this short
time, the VDS of QB will reach zero voltage and the body
diode will turn on. Since the primary IP keeps almost the
same value, the current of the secondary side transformer
is almost the same value as at t1. Therefore, the current of
body diode Q1 will take all the current of the Q1 MOSFET
at t7. The three current paths are the same as those of
timeframe t6 t7. The path through the MOSFET Q1,
however, is changed through the body diode of Q1.

Document Number: 69747

Revision: 11-Oct-07

Application Note 833

Vishay Siliconix

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler
Type 2 SR Driver

current driver

The control driver of synchronous rectifier can use the

PWM control signals SA and SB for the inputs. This is an
easy way for a design to build up in circuitry (Figure 8).
Obviously, the power loss of Q1 derives from the product
of VF in the body diode and the average in t2 to t4. It is
greater than that of the type 1 SR driver.

SA

SR2

current driver

SB

SR1

Figure 8 - Schematic Diagram of Type 2 Synchronous Rectifier

TRUTH TABLE OF TYPE 2 SYNCHONOUS RECTIFIER

STATE
t0 t1
t1 t2
t2 t3
t3 t4
t4 t5
t5 t6
t6 t7
t7 t0

SA
H
H
H
L
L
L
L
L

PRIMARY GATE SIGNAL

SB
SC
L
L
L
L
L
H
L
H
H
H
H
L
H
L
L
L

SD
H
L
L
L
L
L
H
H

SR INPUT SIGNAL
SR1
SR2
L
H
L
H
L
H
L
L
H
L
H
L
H
L
L
L

APPLICATION NOTE

Document Number: 69747

Revision: 11-Oct-07

www.vishay.com
9

Application Note 833

Vishay Siliconix

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler
L1
+

SA

+
QA
SA

QC

Q1
SR1

SC

Co
T1

Vi

SB

VT
(=Max.)
QB
SB

t0

Q2

QD

SR2

SD

t1

L2
L1

Delay A/B
+

+
QA
SA

QC

SC

Q1
SR1

SC
T1

VT
(=0)

Vi

QB

SD

SB

t1

Q2

QD

SR2

SD

t2

L2
L1

Delay C/D

+
QA
SA

QC

Q1
SR1

SC
T1

VT

VT
(=0)

Vi

QB
SB

t2

Q2

QD

SR2

SD

t3

L2
L1

SR1
+

+
QA
SA

QC

SR2

Q1
SR1

SC
T1

VT
(=0)

Vi

QB

VQ1

SB

t3

Q2

QD

SR2

SD

t4

L2
L1

VQ2
+

Body diode of
Q1 turn on

+
QA
SA

Body diode of
Q1 turn on

QC

Q1
SR1

SC
T1

Body diode of
Q2 turn on

VT
(=-Max.)

Vi

IQ1

QB
SB

t4

Q2

QD

SR2

SD

t5

IQ2

L2
L1
+

+
QA
SA

QC

APPLICATION NOTE

IL1

Q1
SR1

SC
T1

VT
(=0)

Vi

IL2

QB
SB

t7 t0

t1 t2

t3 t4

t5 t6

t7 t0

QD

SR2

SD

t1 t2

t5

Q2

t6

L2
L1

L1
+

+
QA
SA

QC

Q1

SC

+
QA
SA

QC
SC

T1

QB
SB
-

T1
VT
(=0)

Vi

Q1

t6

Q2

QD
SD

t7

VT
((=0)

Vi

QB
SB
-

t7

Q2

QD
SD

t0

L2

L2

Figure 9 - Schematic Operation of Phase-Shifted Full-Bridge PWM Control With Type 2 SR Driver
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10

Document Number: 69747

Revision: 11-Oct-07

Application Note 833

Vishay Siliconix

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler
Schematic Operation and Description
Timeframe t0 t1 and t1 t2
At t0, SR2 starts to turn the Q2 MOSFET on. Because the
body diode of Q2 is already turned on, the VDS of Q2 is
zero. ZVS occurs in the turn-on switching of Q2. The high
spike voltage of Q1 VDS and the turn-off switching loss
also occur. Other operations are the same as type 1.

Timeframe t4 t5 and t5 t6

Timeframe t2 t3

Timeframe t6 t7

At t4, SR1 starts to turn the Q1 MOSFET on. Because the

body diode of Q1 is already turned on, the VDS of Q1 is
zero. ZVS occurs in the turn-on switching of Q1. The high
spike voltage of Q2 VDS and the turn-off switching loss
also occur. Other operations are the same as type 1.

At t2, SR1 is still off. The current continues to flow

through the body diode of Q1. Other operations are the
same as type 1.

At t6, SR2 is still off. The current continues to flow

through the body diode of Q2. Other operations are the
same as type 1.

Timeframe t3 t4

Timeframe t7 t0

All operations are the same as type 1. However, SR1 and

SR2 are low. The current will not flow through the
MOSFET, but the body diode.

All operations are the same as type 1. However, SR1 and

SR2 are low. The current will not flow through the
MOSFET, but the body diode.

Design Consideration of Synchronous Rectifier MOSFET

Voltage Spike of VDS in Turn-Off of Body Diode
L1
+

+
QA

QC

SA

Q1

Dsn1

SR1

SC

T1

Rsn1

Co

Lr
Vi

Csn1

Ls

Cb

Csn2
VT
QB

QD

SB

SR2

SD

Q2

Rsn2
Dsn2

L2

Figure 10 - Leakage Inductance of Transformer and Snubber of SR

Since Q2 is on at t0, Q1 will be off at the same time. The

is transferred from the

primary side to the secondary side and is combined with the

parasitical capacitance (PCB and MOSFET). Inductance L
and capacitance C resonate a high-voltage spike. This spike

Document Number: 69747

Revision: 11-Oct-07

may cause an over-rating of VDSS in the SR MOSFET. The

spike only happens at the turn-off moment. The snubbers
may be added as shown in Figure 10. Below, we report on
experiments aimed at discovering the main parameter that
causes the voltage spike. The results are obtained by testing
a power supply.

www.vishay.com
11

APPLICATION NOTE

leakage inductance Ls

Ns 2

= ----------2 Lr
Np

Application Note 833

Vishay Siliconix

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler
Delay Circuit of Control Driver
L1
+

+
QA

QC

SA'

Q1
SR1

SC'

Co

Vo

T1
Vi

VT

QB
SB'

Q2

SR2

QD
SD'

L2

SA

Rdl

SD

Cdl

current driver

SB

Rdl

SC

Cdl

current driver

Figure 11 - Driver Circuit With RC Delay of Secondary SR

switching delays for SA, SB, SC, and SD. Figure 11 shows
a design that measures the delay time between SA and SA',
and sets the RC delay for the SR driver, so that the SR
MOSFET will not turn on before the primary MOSFET,
avoiding the short circuit of Q1 and Q2.

Putting the feedback control and PWM controller on the

secondary side allows better regulation of the output and
simplifies design of the control compensator. Most power
supplies use a pulse transformer (or driver transformer) to
drive the primary MOSFET. But this approach does not
represent an "ideal" transformer, and its use introduces
Calculation of SR Power Dissipation
ILmax
ILav
ILmin

I,L1

Slope=-Vo/L

Slope=(VT-Vo)/L

ILmax
ILav
ILmin

I,L2
Slope=-Vo/L
Slope=(VT-2Vo)/L

APPLICATION NOTE

Slope=Vo/L
I,Q2
Vds=Vf
Type2
Vds=Id x Rds,on
Type1

Vds=Id x Rds,on
Vds,Q2
t0

t1

t4

t5

t0

t1

Figure 12 - Illustration of Power Dissipation of Synchronous Rectifier

To simplify the calculation, the duration of the A/B and C/D

delays can be considered negligible. Figure 12 shows the

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12

current waveforms of the output inductors Id and VDS of the

SR Q2 MOSFET.

Document Number: 69747

Revision: 11-Oct-07

Application Note 833

Vishay Siliconix

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler
Power dissipation calculations of the four periods according to the type 1 SR driver are stated as follows:
1. Timeframe t0 t1

Io
average Id = IL av + IL av = 2 IL av = Io IL av = -----

V DS = r DS(on) average Id = r DS(on) Io

D TS
2
Power dissipation Pd1 = ----------------- Id V DS = D r DS(on) Io
TS

2. Timeframe t1 t4
Vo D Vo
Vo D Vo
V DS = r DS(on) average Id = r DS(on) Io + T SX -----------average Id = Io + T SX ----------- 4 L ---------------- 4 L ----------------2L
2L
( 0.5 D ) T S
Vo D Vo 2
Power dissipation Pd2 = ------------------------------------ Id V DS = ( 0.5 D ) r DS(on) Io + T SX ------------ ------------------
4 L
TS
2L

3. Timeframe t4 t5
Power dissipation = Turn-off power loss according to waveforms
t rr
Pd3 = ---------------- V DS , off Irm
2 TS

4. Timeframe t5 t0
Vo D Vo
average Id = T SX ------------ ------------------
4 L
2L
Vo D Vo
V DS = r DS(on) average Id = r DS(on) T SX ------------ ------------------
4 L 2 L
( 0.5 D ) T S
Vo D Vo
Power dissipation Pd2 = ------------------------------------ Id V DS = ( 0.5 D ) r DS(on) T SX ------------ ------------------
4 L 2 L
TS

5. Total Power Dissipation = Pd1 + Pd2 + Pd3 + Pd4

Example:
Assume TS = 10 s, D = 0.3, Io = 30 A, Vo = 12 V, L = 10 H, rDS(on) = 4.7 m, trr = 40 ns, Irm = 6 A, VDS, off = 40 V
2

Pd1 = 0.3 0.0047 30 = 1.269 W

2
2
12
0.3 12
---------------------------------- ---------------------------------- = 0.2 0.0047 31.2 = 0.915 W

6
6
4 10 10
2 10 10
9
40 10
- 40 6 = 0.48 W
Pd3 = --------------------------------6
2 10 10
2
6
2
12
0.3 12
Pd4 = 0.2 0.0047 10 10 ---------------------------------- ---------------------------------- = 0.2 0.0047 1.2 = 0.002 W

6
6
4 10 10
2 10 10

Pd2 = 0.2 0.0047 30 + 10 10

Total power dissipation of type 1 MOSFET = 2.666 W

If the driver is type 2, Pd4 is different (VF = 1.3 V)
( 0.5 D ) T S
Vo D Vo
Pd4 = ------------------------------------ V F T SX ------------ ------------------ = 0.2 1.3 1.2 = 0.312 W
4 L
TS
2L

APPLICATION NOTE

Pd1, Pd2, Pd3 are same as those of type 2

Total power dissipation of type 2 MOSFET = 2.976 W
If there is no SR, just Schottky diode rectifiers operate in the secondary side (VF = 0.8 V)
D TS
Pd1 = ----------------- V F Io = 0.3 0.7 30 = 7.2 W
TS
Vo D Vo
Pd2 = ( 0.5 D ) V F Io + T SX ------------ ------------------ = 0.2 0.8 31.2 = 4.992 W
4 L 2 L
9

40 10
- 40 6 = 0.48 W
Pd3 = --------------------------------6
2 10 10
( 0.5 D ) T S
Vo D Vo
Pd4 = ------------------------------------ V F T SX ------------ ------------------ = 0.2 0.8 1.2 = 0.192 W
4 L
TS
2L

Total power dissipation of Schottky diode = 12.864 W

Document Number: 69747
Revision: 11-Oct-07

www.vishay.com
13

Application Note 833

Vishay Siliconix

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler
Test Results and Analysis of Synchronous Rectifier MOSFET
Do the Voltage Spikes of SR Relate to trr and Qrr?
Assume the spike is related to trr and Qrr of the body diode,
because the spike is found while the MOSFET is turned
off. If trr and Qrr are bigger, that may induce the larger VDS
spike in the recovery period.

The following test waveforms show:

(1)

Channel 3: VDS; 50 V/div

(2)

Channel 4: Id; 5 A/div

Figure 13 - 30-A Load of SUP90N08-4m8p

1. Test waveforms in Figure 13 show that the spike occurs when SR has been turned off and the reverse voltage of VDSS starts
to rise.
2. After SR is turned off, the current of the SR body diode goes negative and processes the reverse recovery operation.
3. Placing capacitors in between the drain and source of SR is one method of finding out if the voltage spike is related to trr.
Does the Voltage Spike of SR Relate to Cds and Cdg?
Assume the spike is related to Cds, Cdg, and Cgs of the body
diode. Changing Cds or Cdg may change Ciss, Crss, and COSS
of the SR MOSFET. The change probably interferes with
the efficiency, Ids, and VDS waveforms.

The following data shows the test results. Some test

waveforms are shown in the last section for your reference.
The comparison of efficiency and the VDSS spike are listed
in the table and statistic chart.

1. Efficient Result
No significant difference of efficiency for SR by adding
Cds and Cdg with SUP90N08.

APPLICATION NOTE

Efficiency with SUP90N08 (%)

ADD
ADD
ASS
ADD
OUTPUT ADD 0 470 pF 1500 pF 100 pF 220 pF
Cdg
Cdg
Cds
Cds
LOAD
(%)
(%)
(%)
(%)
(%)
Power
Supply
Efficiency
with
SUP90N08

10 A

76.4

76.2

75.9

76.4

76.2

15 A

79.6

79.7

79.5

79.8

79.7

20 A

80.9

80.9

81.0

81.0

80.9

25 A

80.8

80.8

80.9

80.8

80.9

30 A

80.0

80.0

80.1

80.1

80.1

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14

81.0 %
80.5 %
80.0 %
79.5 %
79.0 %
78.5 %
78.0 %
77.5 %
77.0 %
76.5 %
76.0 %

add 0
add 470 pF
Cds
add 1500 pF
Cds
add 100 pF
Cdg
add 220 pF
Cdg
10 A

15 A

20 A

25 A

30 A

Document Number: 69747

Revision: 11-Oct-07

Application Note 833

Vishay Siliconix

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler
2. VDS Spike Result
Adding extra Cds in SUP90N08 does not significantly
improve the VDS spike. However, adding extra Cdg in
SUP90N08 leads to improvement (Cdg = 220 pF, around
13 V below the original data).
ADD
ADD
ASS
ADD
OUTPUT
ADD 0 470 pF 1500 pF 100 pF 220 pF
LOAD
Cdg
Cdg
Cds
Cds

VDS Spike
with
SUP90N08

10 A

66.0

65.1

61.7

61.1

55.1

15 A

74.1

72.0

67.4

69.1

58.9

20 A

76.0

78.1

71.1

71.9

63.0

25 A

79.0

81.0

74.9

76.1

65.9

30 A

78.1

81.0

76.0

78.0

65.0

VDS Spike with SUP90N08 (V)

85.00
add 0

80.00

add 470 pF
Cds
add 1500 pF
Cds
add 100 pF
Cdg
add 220 pF
Cdg

75.00
70.00
65.00
60.00
55.00
50.00
10 A

15 A

20 A

25 A

30 A

The following test waveforms show Channel 1: Vg, Q1; 10 V/div, Channel 2: Vg, Q2; 10 V/div, Channel 3: VDS, Q2;
50 V/div, and Channel 4: Id, Q2; 5 A/div:

30-A Load of SUP90N08-V1

APPLICATION NOTE

30-A Load of SUP90N08-V1, add Cds 470 pF

30-A Load of SUP90N08-V1, add Cds 1500 pF

Document Number: 69747

Revision: 11-Oct-07

www.vishay.com
15

Application Note 833

Vishay Siliconix

Switching Analysis of Synchronous Rectifier MOSFETs With

Phase-Shifted Full-Bridge Converter and Current Doubler

25-A Load of SUP90N08-V1, add Cdg 100 pF

30-A Load of SUP90N08-V1, add Cdg 220 pF

References
[1] Richard G. Hoft, Semiconductor Power Electronics, published by Van Nostrand Reinhold Company Inc. in 1986.
[2] Bill Andreycak, Phase Shift, Zero Voltage Transition Design Consideration and the UC3875 PWM Controller, Texas
Instruments Literature No. SLUA107.

APPLICATION NOTE

[3] Steve Mappus, Control Driven Synchronous Rectifier in Phase shifted Full Bridge Converters, Texas Instruments
Literature No. SLUA287.

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16

Document Number: 69747

Revision: 11-Oct-07