MOSFET CIRCUITS

Introduction

Q: What are two major types

of three-terminal
semiconductor devices?
metal-oxide-semiconductor
field-effect transistor
(MOSFET)
bipolar junction transistor
(BJT)
Q: Why are MOSFETs more
widely used?
size (smaller)
ease of manufacture
lesser power utilization

note: MOSFET is more widely used in

implementation of modern electronic
devices

MOSFET technology
It allows placement of
approximately 2 billion
transistors on a single IC

backbone of very
large scale
integration (VLSI)
It is considered preferable
to BJT technology for many
applications.

Device Structure
and Operation
Figure 5.1. shows general structure of the n-channel
enhancement-type MOSFET

Figure 5.1: Physical structure of the enhancement-type NMOS transistor: (a) perspective view, (b)

cross-section. Note that typically L = 0.03um to 1um, W = 0.1um to 100um, and the thickness of
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the oxide layer (tox) is in the range of 1 to 10nm.
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)

5.1.3. Creating a
Channel for
Current Flow
Q: What happens if (1) source and
drain are grounded and (2)
positive voltage is applied to gate?
Refer to figure to right.
step #1: vGS is applied to the
gate terminal, causing a
positive build up of positive
charge along metal electrode.
step #2: This build up causes
free holes to be repelled from
region of p-type substrate
under gate.

Figure 5.2: The enhancement-type NMOS

transistor with a positive voltage applied to the
gate. An n channel is induced at the top of the
substrate beneath the gate

Q: What happens if (1)

source and drain are
grounded and (2) positive
voltage is applied to gate?
Refer to figure to right.

step #3: This migration

results in the uncovering of
negative bound charges,
originally neutralized by the
free holes
step #4: The positive gate
voltage also attracts electrons
from the n+ source and drain
regions into the channel.

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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)

Figure 5.2: The enhancement-type NMOS

transistor with a positive voltage applied to the
gate. An n channel is induced at the top of the
substrate beneath the gate

5.1.3. Creating a
Channel for
Current Flow
threshold voltage (Vt) is the
minimum value of vGS required to
form a conducting channel
between drain and source
typically between 0.3 and
0.6Vdc
field-effect when positive vGS is
applied, an electric field develops
between the gate electrode and
induced n-channel the
conductivity of this channel is
affected by the strength of field
SiO2 layer acts as dielectric
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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)

Vtn is used for n-type

MOSFET, Vtp is used
for p-channel

effective / overdrive voltage is

the difference between vGS applied
and Vt.
(eq5.1) vOV vGS Vt

oxide capacitance (Cox) is the

capacitance of the parallel plate
capacitor per unit gate area (F/m2)
ox is permittivity of SiO2 3.45E11 F / m
tox is thickness of SiO2 layer

(eq5.3) C ox ox in F / m2
tox

avOV

avDS

The voltage differential

between both sides of nchannel increases with

vDS.

University Publishingof the e-NMOS transistor as v

Figure
5.5:Oxford
Operation
DS is increased.
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)

note the average

value

note that we can define

total charge stored in
channel |Q| as area of this
trapezoid
Q vOV 12 vDS L

Figure 5.6(a): For a MOSFET with vGS = Vt + vOV application of vDS causes the voltage drop
along the channel to vary linearly, with an average value of vDS at the midpoint. Since vGD >
Vt, the channel still exists at the drain end. (b) The channel shape corresponding to the
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situation
inCircuits
(a).byWhile
the
depth
of the
channel at the source is still proportional to vOV,
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Adel S. Sedra
and Kenneth
C. Smith
(0195323033)
the drain end is not.

5.1.6. Operation
for vDS >> vOV
In section 5.1.5, we assume
that n-channel is tapered but
channel pinch-off does not
occur.
Trapezoid doesnt become
triangle for vGD > Vt
Q: What happens if vDS > vOV?
A: MOSFET enters
saturation region. Any
further increase in vDS has
no effect on iD.

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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)

pinch-off does not mean

blockage of current

Figure 5.8: Operation of MOSFET with vGS = Vt +

vOV as vDS is increased to vOV. At the drain end,
vGD decreases to Vt and the channel depth at
the drain-end reduces to zero (pinch-off). At
this point, the MOSFET enters saturation more
of operation. Further increasing vDS (beyond
vOV) has no effect on the channel shape and iD
remains constant.

saturation occurs
once vDS > vOV

1
triode:

C
v

n
ox
OV
2 vDS vDS

L
(eq5.14) iD
saturation: 1 C W v 2
n ox
OV
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Sedra and Kenneth C. Smith (0195323033)
2
L
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if vDS vOV
otherwise

in A

5.1.7. The pChannel MOSFET

Figure 5.9(a) shows crosssectional view of a p-channel
enhancement-type MOSFET.
structure is similar but
opposite to n-channel
complementary devices two
devices such as the p-channel
and n-channel MOSFETs.

Figure 5.9(a): Physical structure of the PMOS transistor. Note that it is similar to the
NMOS transistor shown in Figure 5.1(b), except that all semiconductor regions are
reversed in polarity. (b) A negative voltage vGS of magnitude greater than |Vtp| induces a
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p-channel,
and aby Adel
negative
a current iD to flow from source to drain.
Microelectronic Circuits
S. Sedra andvKenneth
C. Smith (0195323033)
DS causes

5.1.8.
Complementary
MOS or CMOS
CMOS employs MOS transistors of both polarities.
more difficult to fabricate
more powerful and flexible
now more prevalent than NMOS or PMOS

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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)

Figure 5.10: Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a
separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body
is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to
the n well; the latter functions as the body terminal for the p-channel device.

p-type semiconductor

provides the MOS body

(and allows generation
of n-channel)
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n-well is added to allow

generation of p-channel

SiO2 is used to isolate

NMOS from PMOS
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)

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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)

5.2.2. The iD-vGS

Characteristic

Q: What is one problem with (5.21)?

A: It is nonlinear w/ respect to
vOV however, this is not of
concern now.

In effect, it becomes a voltagecontrolled current source.

This is key for amplification.
Refer to (5.21).
2

vOV

1 W
2
(eq5.21) iD kn vGS Vtn
2 L

this relationship provides

basis for application of
MOSFET as amplifier

Figure 5.14: The iD-vGS characteristic of an NMOS transistor operating in the saturation region. The iDvOV characteristic can be obtained by simply re-labeling the horizontal axis, that is, shifting the origin to
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the point vGS = Vtn.
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)

5.2.2. The iD-vGS

Characteristic
The view of transistor as CVCS
is exemplified in figure 5.15.
This circuit is known as the
large-signal equivalent
circuit.
Current source is ideal.
Infinite output resistance
represents independent, in
saturation, of iD from vDS..
note that, in this circuit, iD is
completely independent of vDS
(because no shunt resistor
exists)

Figure 5.15: Large-signal equivalent-circuit

model of an n-channel MOSFET operating in the
saturation

5.2.4. Finite
Output
Resistance in
Saturation
Q: How do we account for this
effect in iD?
A: Refer to (5.23).

Figure 5.16: Increasing vDS beyond vDSsat causes

the channel pinch-off point to move slightly
away from the drain, thus reducing the effective
channel length by L

valid when vDS vOV

1
W 2
(eq5.17) iD nC ox vOV
in A
2
L
1
W 2
(eq5.23) iD nC ox vOV
1 vDS in A
2
L

valid when vDS vOV

A: Addition of finite output

resistance (ro).

Figure 5.18: Large-Signal Equivalent Model of the

n-channel MOSFET in saturation, incorporating the
output resistance ro. The output resistance
models the linear dependence of iD on vDS and is
given by (5.23)

5.2.4. Finite
Output
Resistance in
Saturation
Q: How is ro defined?
step #1: Note that ro is the
1/slope of iD-vDS
characteristic.
step #2: Define relationship
between iD and vDS using
(5.23).
step #3: Take derivative of
this function.
step #4: Use above to define
ro.
Note that ro may be defined in
terms of iD, where iD does not
take in to account channel length
modulation
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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)

i
(eq5.24) ro D
vDS vGS constant

(5.23)

iD
1
W 2
(eq5.23)

nC ox vOV 1 vDS
vDS vDS 2
L

(5.23)

iD
1
W 2
(eq5.23)

nC ox vOV 1 vDS
vDS vDS 2
L

iD 1
W 2
(eq5.23)
nC ox vOV

vDS 2
L

W 2
1
(eq5.25) ro nC ox vOV

L
2
vGS constant
(eq5.24) ro

1 VA

iD iD

5.2.4. Finite
Output
Resistance in
Saturation
Q: What is l?
A: A device parameter with the
units of V -1, the value of which
depends on manufacturers
design and manufacturing
process.
much larger for newer techs

Figure 5.17 demonstrates the effect

of channel length modulation on
vDS-iD curves
In short, we can draw a straight
line between VA and saturation.

Figure 5.17: Effect of vDS on iD in the

saturation region. The MOSFET
parameter VA depends on the process
technology and, for a given process, is
proportional to the channel length L.

5.4.2. Voltage
Transfer
Characteristic

Figure 5.27: (b) the voltage transfer

characteristic (VTC) of the amplifier
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from
previous
slideC. Smith (0195323033)
Microelectronic Circuits
by Adel
S. Sedra and Kenneth

voltage transfer characteristics

(VTC) plot of out voltage vs. input
three regions exist in VTC
vGS < Vt cut off FET
vOV = vGS Vt < 0
ID = 0
vout = vDD
Vt < vGS < vDS + Vt saturation
vOV = vGS Vt > 0
ID = kn(vGS Vt)2
vDS >> vOV
vout = VDD IDRD
vDS + Vt < vGS < VDD triode
vOV = vGS Vt > 0
ID = kn(vGS Vt vDS)vDS
vDS > vOV
vout = VDD IDRD

5.4.3: Biasing the

MOSFET to Obtain
Linear Amplification
bias point / dc operating pt. (Q) =
point of linearization for MOSFET
also known as quiescent point
Q: how will Q help us?
because VTC is linear near Q, we
may perform linear
amplification of signal << Q

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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)

linear
amplification
around Q in
saturation region

Figure 5.28: biasing the MOSFET amplifier at

point Q located on segment AB of VTC

Q: How is linear
gain achieved?
As long as vgs(t) is small, its
effect on vDS(t) will be linear

facilitating linear amplification.

Figure 5.29: The MOSFET amplifier with a small

time-varying signal vgs(t) superimposed on the
dc bias voltage vGS. The MOSFET operates on a
short almost-linear segment of the VTC around
the bias point Q and provides an output voltage
vds = Avvgs

5.4.4. SmallSignal Gain

Equation (5.38) is
another version of (5.37)
which incorporates
(5.17).
It demonstrates that
gain is ratio of:
voltage drop across RD
half of over voltage

(eq5.37) Av knVOV RD
action:
incorporate
2
(5.17) iD 12 kn vOV

ID RD
(eq5.38) Av

VOV /2