QUESTIONS ON DIGITAL ELECTRONICS AND MICROPROCESSORS:-

1.) (734)8 = ( )16

(a) C 1 D
(b) D C 1

(c) 1 C D

(d) 1 D C

2.)No. of flip-flops required for synchronous mode-2 counter :

a) 3

b) 2

c) 1

d) 4

3.) EPROM contents can be erased by exposing it to :

(a) Ultraviolet rays
(b) Infrared rays
(c) Burst of microwaves
(d) Intense heat radiations
4.) The speed of conversion is maximum in :
(a) Successive-approximation A/D converter.
(b) Parallel-comparative A/D converter.
(c) Counter ramp A/D converter.
(d) Dual-slope A/D converter.
5.) If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in
cascade is :
(a) 1000 Hz

(b) 500 Hz (c) 25 Hz (d) 12.5 Hz.

6.) In digital ICs, Schottky transistors are preferred over normal transistors because of their
(a) Lower Propagation delay. (b) Higher Propagation delay.
(c) Lower Power dissipation. (d) Higher Power dissipation.
7.) Which TTL logic gate is used for wired ANDing
(a) Open collector output (b) Totem Pole
(c) Tri state output
(d) ECL gates
8.) A 6-bit R-2R ladder D/A converter has a reference voltage of 5V. It meets standard
linearity. Find output voltage for the word 011100 :
(a) 3.16 (b)2.18 (c) 2.81 (d)2.84

9.) In the figure, the LED ,

a.)
b.)
c.)
d.)

Emits light when both S1 and S2 are closed.

Emits light when both S1 and S2 are open.
Emits light when only of S1 or S2 is closed.
Does not emit light, irrespective of the switch positions.

10.) In the circuit shown, the device connected to Y5 can have address in the range,

a.)
b.)
c.)
d.)

2000 20FF
2D00 2DFF
2E00 2EFF
FD00 FDFF

11.) The output Y of a 2-bit comparator is logic 1 whenever the 2 bit input A is greater than the
2 bit input B. The number of combinations for which the output is logic 1, is
a.)
b.)
c.)
d.)

4
6
8
10

12.) In the circuit shown below, Q1 has negligible collector to emitter saturation voltage and the diode
drops negligible voltage across it under forward bias. If VCC is +5 volts, X and Y are digital signals with
0 volts as logic 0 and VCC as logic 1, then the Boolean expression for Z is

(a.)XY

(b) X Y

(c)XY

(d)X Y

13.) For an n variable Boolean function, the maximum number of prime implicants is
a.) 2(n 1)
b.) n/2
c.) 2n
d.) 2(n 1)
14.) What are the minimum number of 2 to 1 multiplexers required to generated a 2 input AND
gate and a 2 input EX-OR gate?
a.) 1 and 2
b.) 1 and 3
c.) 1 and 1
d.) 2 and 2
15.) The logic function implemented by the circuit below is (ground implies a logic 0)

a.)
b.)
c.)
d.)

F = AND (P,Q)
F = OR (P,Q)
F = XNOR (P,Q)
F = XOR (P,Q)

16.) If X and Y are inputs and the Difference (D = X Y) and the Borrow (B) are the outputs, which one of
the following diagrams implements a half-subtractor?

17.) An SR latch is a
a.)
b.)
c.)
d.)

Combinational circuit
Synchronous sequential circuit
One bit memory element
One clock delay element

18.) A Master Slave flip flop has the characteristic that

a.)
b.)
c.)
d.)

Change in the input immediately reflected in the output.

Change in the output occurs when the state of the master is affected
Change in the output occurs when the state of the slave is affected
Both the master and the slave states are affected at the same time.

19.) The present output Qn of an edge triggered JK flip-flop is logic 0. If j = 1, then Qn+1 is
a.)
b.)
c.)
d.)

Cannot be determined
Will be logic 0
Will be logic 1
Will race around

20.) The initial contents of the 4 bit serial in serial out, right shift, shift register shown in figure, are
0110. After three clock pulses are applied, the contents of the shift register will be

a.)
b.)
c.)
d.)

0000
0101
1010
1111

21.) Choose the correct one from among the alternatives A,B,C,D after matching an item from
Group 1 with the most appropriate item in Group 2.

a.)
b.)
c.)
d.)

P 3, Q 2, R 1
P 3, Q 1, R 2
P 2, Q 1, R 3
P 1, Q 2, R 2

22.) A PLA can be used

a.)
b.)
c.)
d.)

As a microprocessor
As a dynamic memory
To realize a sequential logic
To realize a combinational logic

23.) A dynamic RAM consists of

a.)
b.)
c.)
d.)

6 transistors
2 transistors and 2 capacitors
1 transistor and 1 capacitor
2 capacitors only

24.) The minimum number of MOS transistors required to make a dynamic RAM cell is
a.)
b.)
c.)
d.)

1
2
3
4

25.) A memory system of size 26K bytes is required to be designed using memory chips which have
12 address lines and 4 data lines each. The number of such chips required to design the memory
system is,

a.)
b.)
c.)
d.)

8
14
15
13

26.) Each cell of a Static Random Access Memory contains

a.)
b.)
c.)
d.)

6 MOS transistors
4 MOS transistors and 2 capacitors
2 MOS transistors and 4 capacitors
1 MOS transistor and 1 capacitor

27.) An 8085 microprocessor based system uses a 4K x8 bit RAM whose starting address is AA00H.
The address of the last byte in this RAM is

a.)
b.)
c.)
d.)

0FFFH
1000H
B9FFH
BA00H

28.) The advantage of using a dual slope ADC in a digital voltmeter is that
a.)
b.)
c.)
d.)

Its conversion time is small

Its accuracy is high
It gives output in BCD format
It does not require a comparator

29.) In the following circuit employing pass transistor logic, all NMOS transistors are identical with a
threshold voltage of 1 volt. Ignoring the body effect, the output voltages at P, Q, and R are(in volts)

a.)P=4,Q=3,R=2
b.)P=5,Q=5,R=5
c.)P=4,Q=4,R=4
d.)P=5,Q=4,R=3
30.) The output (Y) of the circuit shown in the figure is

(a)A + B + C

(b) A+ B C + AC

(c) ABC

(d) ABC

31)If WL is the Word Line and BL is the Bit Line, an SRAM cell is shown is ,

32.) The number of comparators in a 4 bit flash ADC is

a.)
b.)
c.)
d.)

4
5
15
16

33.) The most commonly used amplifier in sample and hold circuits is
a.)
b.)
c.)
d.)

A unity gain inverting amplifier

A unity gain non inverting amplifier
An inverting amplifier with a gain of 10
An inverting amplifier with a gain of 100

34.) In an 8085 microprocessor system with memory mapped I/O,

a.)
b.)
c.)
d.)

I/O devices have 16 bit addresses

I/O devices are accessed using IN and OUT instructions
There can be a maximum of 256 input devices and 256 output devices
Arithmetic and logic operations can be directly performed with the I/O data.

35.) When a CPU is interrupted, it

a.) Stops executing of instructions
b.) Acknowledges interrupt and branches of subroutine
c.) Acknowledges interrupt and continues

d.) Acknowledges interrupt and waits for the next instruction from the interrupt device
36.) The decoding circuit is shown in figure, has been used to generated the active low chip select
signal for a microprocessor peripheral (The address lines are designated as A0 to A7 for I/O
addresses).

a.)
b.)
c.)
d.)

60H 63H
A4 A7H
30 33H
70 73H

37.)If CS = A15A14A13 is used as the chip select logic of a 4K RAM in an 8085 system, then
its memory range will be
a.)
b.)
c.)
d.)

3000 3FFFFH
7000 7FFFH
5000 5FFFH and 6000 6FFFH
6000 6FFFH and 7000 7FFFH

38.) An instruction used to set the carry flag in a computer can be classified as
a.)
b.)
c.)
d.)

Data transfer
Arithmetic
Logical
Program control

39.) In the 8085 microprocessor, the RST 6 instruction transfers the program execution to the
following location

a.)
b.)
c.)
d.)

30H
24H
48H
60H

40.) The number of hardware interrupts (which require an external signal to interrupt) present in an
8085 microprocessor are,

a.)
b.)
c.)
d.)

1
4
5
13

41) A typical TTL gate has a fan-out of

a. )6
b. )8
c. )10

d.)20
42.) In standard TTL, the Totem pole stage refers to
a.)
b.)
c.)
d.)

Multi emitter input stage

Phase splitter
Output buffer
Open collector output stage

43.) Figure given below shows the internal schematic of a TTL AND-OR-Invert (AOI) gate. For the
inputs shown in the given figure, the output Y is

(a) 0

(b)1

( c)AB

(d)(AB)

44.) For a logic family, given that

VOH is the minimum output high level voltage.

VOL is the maximum output low level voltage.
VIH is the minimum acceptable input low level voltage.
VIL is the maximum acceptable input low level voltage.
Then the correct relationship is
a.) VIH>VOH>VIL>VOL
b.) VOH > VIH > VIL > VOL
c.) VIH > VOH > VOL > VIL
d.) VOH > VIH > VOL > VIL
45.)Which of the following logic family is also known as current-mode logic
a.) RTL
b.) DTL
c.) ECL
d.) TTL
46.)Which of the following logic family has typically(under similar conditions) highest noise
margin ,

a.)TTL
b.)GTL
c.)CMOS
d.)LS TTL
47.) What type of circuit is shown below and which statement best describes its operation?

a.)
b.)
c.)
d.)

It is a two-input CMOS AND gate with open drain.

It is a two-input CMOS buffer with tristate output.
It is a CMOS inverter with tristate output.
It is a hybrid TTL-CMOS inverter with FET totem-pole output.

48.)What does ECL stand for?

a.) It stands for electron-coupled logic; all of the devices used within the gates are N-type
transistors.
b.) It stands for emitter-coupled logic; all of the inputs are coupled into the device through the
emitters of the input transistors.
c.) It stands for emitter-coupled logic; all of the emitters of the input transistors are connected
together and each transistor functions as an emitter follower.
d.) It stands for energy-coupled logic; the input energy is amplified by the input transistors and
allows the device to deliver higher output currents.
49.) Why is the fan-out of CMOS gates frequency dependent?
a.) Each CMOS input gate has a specific propagation time and this limits the number of different gates
that can be connected to the output of a CMOS gate.
b.) When the frequency reaches the critical value, the gate will only be capable of delivering 70% of
the normal output voltage and consequently the output power will be one-half of normal; this defines
the upper operating frequency.
c.) The higher the number of gates attached to the output, the more frequently they will have to be
serviced, thus reducing the frequency at which each will be serviced with an input signal.

d.)The input gates of the FETs are predominantly capacitive, and as the signal frequency increases the
capacitive loading also increases, thereby limiting the number of loads that may be attached to the
output of the driving gate.
50.) Which of the following will not normally be found on a data sheet of a given logic family?
a.) Minimum HIGH level output voltage
b.) Maximum LOW level output voltage
c.) Minimum LOW level output voltage
d.) Maximum HIGH level input current