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Fpga Implementation of Fir Filters Using Pipelined Bit-Serial Canonical Signed Digit Multipliers

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SARATH MOHANDAS
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56 views9 pages

Fpga Implementation of Fir Filters Using Pipelined Bit-Serial Canonical Signed Digit Multipliers

Uploaded by

SARATH MOHANDAS
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© © All Rights Reserved
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FPGA IMPLEMENTATION OF FIR FILTERS USING

PIPELINED BIT-SERIAL
CANONICAL SIGNED DIGIT MULTIPLIERS

SEMINAR REPORT
Submitted in partial fulfilment of
the requirements for the award of M.Tech Degree in
Embedded Systems
of the University of Kerala
Submitted by
SARATH MOHANDAS
2nd Semester
M.Tech Embedded Systems.

Guided by
Mr. SUDEEP P.V.
Assistant Professor, Dept. of ECE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING


SREE BUDDHA COLLEGE OF ENGINEERING, PATTOOR
JUNE, 2012

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING


SREE BUDDHA COLLEGE OF ENGINEERING, PATTOOR

CERTIFICATE

This is to certify that this seminar report entitled FPGA IMPLEMENTATION


OF FIR FILTERS USING PIPELINED BIT-SERIALCANONICAL SIGNED
DIGIT MULTIPLIERS, is a bona fide record of the Seminar done by SARATH
MOHANDAS , under our guidance towards partial fulfilment of the requirements
for the award of the Degree of Master of Technology in Embedded systems of the
University of Kerala during the year 2012.

Mr. Sudeep P.V.


Asst. Prof
Dept. of ECE, SBCE.
(Guide)

Mr. Vishnu V.S


Asst. Prof
Dept. Of ECE, SBCE
(Project Coordinator)
Ms. R Ramya
Asst. Prof
Dept. of ECE, S.B.C.E
(P.G Coordinator)

ACKNOWLEDGEMENT
I take this opportunity to thank the Lord Almighty for his immense blessing
towards the successful completion of my seminar.

I would like to extend my deepest gratitude to thank Dr. SOMI


SEBASTIAN, Principal of Sree Buddha College of Engineering. I would like to
thank Ms. R. RAMYA, Head of the Electronics & Communication Engineering
department.

I also like to thank Mr. VISHNU V.S. (Seminar Coordinator) and Mr.
SUDEEP P.V. my guide, Asst. Professor in Electronics & Communication
Engineering, for lending me helping hand, and all other members of Electronics &
Communication Engineering department, who helped me at various instants, for
the successful completion of the seminar.

Last but not the least I would like to thank all my friends and family
members for their whole hearted support and encouragement.

SARATH MOHANDAS

ABSTRACT
Signal processing ranks among the most demanding applications of digital design and
concepts. It is a mature technology domain wherein the demands for enhanced performance and
reduced resource utilization have risen exponentially over the years. For years numerous efforts
have been made to reduce the implementation complexity of signal processors. One of the
method,

A pipelinable bit-serial multiplier using Canonic Signed Digit or CSD code, is

proposed, which is to represent constant coefficients is introduced to reduce the implementation


complexity of signal processors, which is measured by the Area-Time, or AT product. A bit serial
module for the a*(x-y)z-1 type computation is further developed. Optimization over discrete
power-of two coefficient space have been retargeted on this type of multipliers to generate
minimized no-zero bit coefficients. These also make it possible to confine the latency to be
equivalent to the data word length without causing a large delay in partial product sum
propagation. FPGA architecture is an ideal vehicle for the optimized bit-serial processing. Thus
for the Digital Signal Processing (DSP) and Communication the FPGAs are being increasingly
used for a variety of computationally intensive applications.

TABLE OF CONTENTS
TITLE

CHAPTER

PAGE No.

LIST OF FIGURES
LIST OF TABLES

i
ii

INTRODUCTION

LITERATURE SURVEY

FIR FILTERS BASICS

3.1

INTRODUCTION TO DSP

3.1.1

Analogue Implementation

3.1.2

Digital Implementation

3.2

3.3

DIGITAL FILTERS

3.2.1

Infinite Impulse response filters

3.2.2

Finite Impulse response filters

DIFFERENT OPERATIONS IN FIR FILTERS

10

NUMBER REPRESENTATIONS

12

4.1

REPRESENTATIONS OF NUMBERS

12

4.1.1

Signed Magnitude

14

4.1.2

Ones Complement

14

4.1.3

Twos Complement

14

4.1.4

Canonic Signed Digit Number

15

PIPELINED BIT SERIAL ARCHITECTURE

17

5.1

GENERAL BIT SERIAL ARCHITECTURE

17

5.2

BIT SERIAL PIPELINED ARC HITECTURE

19

5.3

OPERATION MODULES IN FIR FILTERS

21

5.4

IMPLEMENTATION OVER FPGA

23

PERFORMANCE ANALYSIS

24

6.1

PERFORMANCE MEASURES

28

6.1.1

Iteration Period

28

6.1.2

Sampling Period and Throughput

29

6.1.3

Latency

29

6.1.4 Power Dissipation

30

CONCLUSIONS
32

REFERENCES

33

LIST OF FIGURES
FIGURE

TITLE

No.

PAGE
No

3.1

Schematic of an LTI filter of order L

3.2

Typical Architecture of IIR Filter

3.3

Typical FIR filter architecture

3.4

(a) Original Datapath (b)2 level pipelined architecture

10

(c) 2-level parallel processing structure

11

3.5

Bit serial processing of the wordlength W=6

12

3.6

Bit-parallel architecture

12

3.7

Digit serial architecture

12

4.1

Survey of Number representations

13

5.1

General Structure of Bit Serial Architecture

17

5.2

Bit Serial Summation

18

5.3

Bit serial pipeline multiplier

20

5.4

Bit-serial modules for CSD coded coefficient multiplier

21

5.5

a(x y )z

5.6

a(x- y )z

5.7

Generic FPGA Architecture

23

5.8

FPGA Filter Tap Implementation

25

6.1

Throughput vs digit size.

27

6.2

Filter clock rate vs digit size

27

6.3

Relative speed

28

6.4

A-T vs Digit size

28

-l
-l

operator

22

operator

22

LIST OF TABLE
TABLE

TITLE

No.

PAGE
No.

Example for the conversion of the number 1.01110011


to its CSD representation

16

Implementation results

26

ii

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