Ch01 Basic Concepts and Computer Evolution
Ch01 Basic Concepts and Computer Evolution
Computer Architecture
Computer Organization
Attributes of a system
visible to the programmer
Have a direct impact on
the logical execution of a
program
Hardware details
transparent to the
programmer, control
signals, interfaces
between the computer and
peripherals, memory
technology used
Computer
Architecture
Architectural
attributes
include:
Organizational
attributes
include:
Computer
Organization
The operational units and
their interconnections that
realize the architectural
specifications
IBM System
370 Architecture
Could upgrade to a more expensive, faster model without having to abandon original software
New models are introduced with improved technology, but retain the same architecture so that the
customers software investment is protected
Architecture has survived to this day as the architecture of IBMs mainframe product line
Hierarchical system
Set of interrelated
subsystems
Structure
Function
Function
Data processing
Data may take a wide variety of forms and the range of
processing requirements is broad
Data storage
Short-term
Long-term
Data movement
Input-output (I/O) - when data are received from or delivered to a
device (peripheral) that is directly connected to the computer
Data communications when data are moved over longer
distances, to or from a remote device
Control
A control unit manages the computers resources and
orchestrates the performance of its functional parts in response to
instructions
COMPUTER
Main
memory
I/O
System
Bus
CPU
CPU
Registers
Structure
Internal
Bus
Control
Unit
CONTROL
UNIT
Sequencing
Logic
Control Unit
Registers and
Decoders
Control
Memory
ALU
+
CPU controls the operation of
System Interconnection
some mechanism that provides
for communication among CPU,
main memory, and I/O
+
CPU
Major structural
components:
Control Unit
Registers
CPU Interconnection
Core
Processor
Cache Memory
Used to speed up memory access by placing in the cache data from main memory
that is likely to be used in the near future
MOTHERBOARD
Main memory chips
I/O chips
Processor
chip
PROCESSOR CHIP
Core
Core
L3 cache
Core
Core
Core
Core
L3 cache
Core
Core
CORE
Instruction
logic
Arithmetic
and logic
unit (ALU)
Load/
store logic
L1 I-cache
L1 data cache
L2 instruction
cache
L2 data
cache
Figure 1.3
Motherboard with Two Intel Quad-Core Xeon Processors
Figure 1.4
zEnterprise
EC12 Processor
Unit (PU)
Chip Diagram
Figure 1.5
zEnterprise
EC12
Core Layout
History of Computers
First Generation: Vacuum Tubes
IAS computer
elements
Completed in 1952
MQ
Inputoutput
equipment
(I, O)
Arithmetic-logic
circuits
MBR
Instructions
and data
Instructions
and data
M(0)
M(1)
M(2)
M(3)
M(4)
PC
IBR
MAR
IR
Main
memory
(M)
Control
signals
M(4092)
M(4093)
M(4095)
Control
circuits
0 1
39
sign bit
opcode (8 bits)
20
28
opcode (8 bits)
39
Registers
Memory buffer register
(MBR)
Memory address
register (MAR)
Instruction buffer
register (IBR)
Start
Is next
instruction
in IBR?
Yes
No memory
access
required
Fetch
cycle
IR
MAR
IBR (0:7)
IBR (8:19)
No
MAR
MBR
IR
MAR
MBR (20:27)
MBR (28:39)
PC
No
PC
M(MAR)
Left
instruction
required?
Yes
PC + 1
Decode instruction in IR
AC
Go to M(X, 0:19)
M(X)
If AC > 0 then
go to M(X, 0:19)
Yes
Execution
cycle
MBR
AC
M(MAR)
PC
MAR
MBR
AC
AC + M(X)
Is AC > 0?
No
MBR
AC
M(MAR)
AC + MBR
Instruction Type
Opcode
00001010
Symbolic
Representation
LOAD MQ
00001001
LOAD MQ,M(X)
00100001
STOR M(X)
00000001
00000010
00000011
LOAD M(X)
LOAD M(X)
LOAD |M(X)|
00000100
00001101
00001110
00001111
LOAD |M(X)|
JUMP M(X,0:19)
JUMP M(X,20:39)
JUMP+ M(X,0:19)
00000101
00000111
00000110
00001000
0
0
0
1
0
0
0
0
ADD M(X)
ADD |M(X)|
SUB M(X)
SUB |M(X)|
00001011
MUL M(X)
00001100
DIV M(X)
00010100
LSH
00010101
RSH
00010010
STOR M(X,8:19)
00010011
STOR M(X,28:39)
Data transfer
Unconditional
branch
Conditional branch
JU
MP
+
M(X
,20:
39)
Arithmetic
Address modify
Description
Transfer contents of register MQ to the
accumulator AC
Transfer contents of memory location X to
MQ
Transfer contents of accumulator to memory
location X
Transfer M(X) to the accumulator
Transfer M(X) to the accumulator
Transfer absolute value of M(X) to the
accumulator
Transfer |M(X)| to the accumulator
Take next instruction from left half of M(X)
Take next instruction from right half of M(X)
If number in the accumulator is nonnegative,
take next instruction from left half of M(X)
If number in the
accumulator is nonnegative,
take next instruction from
right half of M(X)
Table 1.1
The IAS
Instruction Set
History of Computers
Second Generation: Transistors
Smaller
Cheaper
Table 1.2
Computer Generations
Generation
Approximate
Dates
19461957
Vacuum tube
2
3
19571964
19651971
4
5
6
19721977
19781991
1991-
Transistor
Small and medium scale
integration
Large scale integration
Very large scale integration
Ultra large scale integration
Technology
Typical Speed
(operations per second)
40,000
200,000
1,000,000
10,000,000
100,000,000
>1,000,000,000
+
Second Generation Computers
Introduced:
More
History of Computers
Third Generation: Integrated Circuits
Discrete component
Input
Boolean
logic
function
Output
Input
Binary
storage
cell
Read
Write
Activate
signal
(a) Gate
Output
Integrated
Circuits
Wafer
Chip
Gate
Packaged
chip
In
in ve
te n
gr tio
at n
ed of
ci
rc
M
ui
p r oo
t
r
om e
s
ul l a
ga w
te
d
F
tr irst
an w
si o
st rk
or in
g
1947 50
55
60
65
70
75
80
85
90
95
2000
05
100 bn
10 bn
1 bn
100 m
10 m
100,000
10.000
1,000
100
10
1
11
Moores Law
1965; Gordon Moore co-founder of Intel
The cost of
computer logic
and memory
circuitry has
fallen at a
dramatic rate
The electrical
path length is
shortened,
increasing
operating
speed
Computer
becomes smaller
and is more
convenient to use
in a variety of
environments
Reduction in
power and
cooling
requirements
Fewer interchip
connections
Microprocessors
Birth of microprocessor
More and more elements were placed on each chip so that fewer
and fewer chips were needed to construct a single computer
processor
80286
386TM DX
386TM SX
1982
6 MHz - 12.5
MHz
16 bits
1985
16 MHz - 33
MHz
32 bits
1988
16 MHz - 33
MHz
16 bits
486TM DX
CPU
1989
25 MHz - 50
MHz
32 bits
134,000
275,000
275,000
1.2 million
1.5
0.8 - 1
16 MB
4 GB
16 MB
4 GB
1 GB
64 TB
64 TB
64 TB
8 kB
486TM SX
1991
16 MHz - 33
MHz
32 bits
Pentium
1993
60 MHz - 166
MHz,
32 bits
Pentium Pro
1995
150 MHz - 200
MHz
64 bits
Pentium II
1997
200 MHz - 300
MHz
64 bits
1.185 million
3.1 million
5.5 million
7.5 million
0.8
0.6
0.35
4 GB
4 GB
64 GB
64 GB
64 TB
64 TB
64 TB
8 kB
8 kB
64 TB
512 kB L1 and 1
MB L2
512 kB L2
Pentium 4
1999
450 - 660 MHz
2000
1.3 - 1.8 GHz
2006
1.06 - 1.2 GHz
Core i7 EE
4960X
2013
4 GHz
64 bits
64 bits
64 bits
64 bits
Number of
transistors
Feature size (nm)
Addressable
memory
Virtual memory
9.5 million
42 million
167 million
1.86 billion
250
180
65
22
64 GB
64 GB
64 GB
64 GB
64 TB
64 TB
64 TB
Cache
512 kB L2
256 kB L2
2 MB L2
64 TB
1.5 MB L2/15
MB L3
6
Introduced
Clock speeds
Bus
wid
th
Number of cores
Core 2 Duo
Two processor families are the Intel x86 and the ARM architectures
Current x86 offerings represent the results of decades of design effort on complex
instruction set computers (CISCs)
ARM architecture is used in a wide variety of embedded systems and is one of the
most powerful and best-designed RISC-based systems on the market