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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 10, OCTOBER 2016

A Fully Isolated Delta-Sigma ADC for

Shunt Based Current Sensing
Zhichao Tan, Member, IEEE, Mick Mueck, Member, IEEE, Xiao Hong Du, Larry Getzin, Michael Guidry,
Shane Keating, Xing Xing, Flow Zhao, and Baoxing Chen
Abstract This paper presents the worlds first reported chiplevel 5 kVrms isolated delta-sigma ADC architecture which
realizes isolation in both the power and signal domains. The
compact IC package contains an integrated isolated power
converter which includes an on-chip transformer, oscillator and
rectifier, three deltasigma analog-to-digital converters, a voltage
reference, a temperature transducer, on-chip data transformers,
and a controller/communication chip. Because it includes all
of the isolation units within the same package, no PCB level
isolation components are needed. This solution displaces the need
for isolation using opto-couplers or costly, bulky and frequency
dependent current transformers, and enables lower cost shunt
resistor based current sensing applications such as domestic and
industrial energy monitoring. It also enables new portable current
sensing applications where high voltage isolation is required. The
system-in-package (SIP) draws 12.5 mA from a 3.3 V supply and
achieves 74.4 dBFS SNDR and 80.8 dBFS SFDR in a bandwidth
of 3.3 kHz. It achieves an insulation voltage rating of 400 Vrms
continuous and 5 kVrms over a 1 minute duration.
Index Terms Analog-to-digital converters, current sensing,
delta-sigma ADC, isolated power converter, on-chip transformer,
system-in-package (SIP).

I. I NTRODUCTION

PPLICATIONS such as power line monitoring, power

system operation and protection are required to meet
various stringent insulation and safety standards. For example,
domestic power line meters typically measure currents of up to
100 A in AC line voltages of 110 Vrms to 240 Vrms. However,
they typically also need to be rated and tested against a variety
of fault conditions such as 400 Vrms continuous operation
due to miswiring, 5 kVrms for 1 minute, and survive fast
50 s transient surges of 6 kV with 1.2 s rise times. Passing
these tests is mandatory to receive certifications from the many
international regulatory agencies that allow these products to
be sold legally.
The current flow in power lines is usually measured at the
output of an isolated sensor such as a current transformer (CT)
or a Rogowski coil or directly across a nonisolated sensor
such as a shunt resistor [1][3]. If a shunt resistor is used,
the measurement IC is directly connected to the high-voltage
side, and its power supply and data I/O pins must therefore be

Manuscript received February 10, 2016; revised April 19, 2016; accepted
June 5, 2016. Date of publication July 18, 2016; date of current version
September 30, 2016. This paper was approved by Guest Editor Makoto Ikeda.
The authors are with Analog Devices, Inc., Wilmington, MA 01887 USA
(e-mail: [email protected]).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2016.2581800

electrically isolated from the low-voltage side. This is typically

achieved using external opto-couplers, transformers, and highvoltage capacitor division circuitry. In all of these systems, the
external isolating devices (CTs, Rogowski coils, opto-couplers,
transformers, and capacitors) bear the burden of meeting these
insulation and safety standards, and the measurement circuitry
used for the voltage and current analog-to-digital conversion
and the subsequent energy metering is simply a conventional
low-voltage IC. These external isolation elements not only
complicate the system design but also increase both the PCB
area and the system cost.
This paper presents the worlds first reported singlepackage, fully isolated measurement IC in which the ADC
inputs directly connect to a sensor on the high-voltage line
and the ADCs receive power and transfer data across internal
isolation barriers to the low-voltage side of the package. The
IC package itself meets all of the requisite insulation and
safety standards, thus enabling a significantly reduced cost,
component count, and board space solution. Being a shunt
resistor-based solution, it also provides improved features such
as DC and high-frequency current measurement capability and
improved tampering resistance.
The paper is organized as follows. Section II describes various structures of isolated ADC systems including the implemented fully isolated ADC structure. Section III addresses
circuit design and implementation aspects, and Section IV
presents measurement results. The paper is concluded in
Section V.
II. P RIOR -A RT AND THE I MPLEMENTED F ULLY
I SOLATED S OLUTION
In order to determine power and energy, both the high
voltage and current need to be measured by the data
converter IC. The voltage is typically measured using
a simple high-value resistor divider yielding signals of
around 500 mV (350 mVrms). Further discussion of the
voltage channel measurement is therefore omitted due to its
trivial nature. The current is measured by monitoring the
voltage across a sensor in series with the primary current.
While it may seem intuitive to place that sensor near the
Neutral or Ground terminals, it is typically placed at the
high voltage Active terminal. This is to enable the use
of higher voltages by connecting loads across the Active
terminals of different phases in a multi-phase system, e.g.,
220 Vrms appears between the two Active terminals in a twophase 110 Vrms environment. In such cases, a current sensor
placed in the Neutral line would not be able to monitor any

0018-9200 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

TAN et al.: A FULLY ISOLATED DELTA-SIGMA ADC FOR SHUNT BASED CURRENT SENSING

Fig. 1.

Fig. 2.

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CT-based isolation solution.

Fig. 3.

Isolated deltasigma ADC SIP.

Fig. 4.

General sensing application for the implemented isolated ADC.

Shunt-based isolation solution.

current in the 220 Vrms load circuit. It is also more difficult

to tamper with a sensor on an active terminal.
In a conventional CT-based solution as shown in Fig. 1, the
CT converts the high-voltage side AC current in the primary
to a much lower current in the secondary on the low-voltage
side. The secondary current is converted to a voltage via
a burden resistor and then presented to an ADC where the
converted data subsequently undergoes further signal processing. The CT serves the roles of both signal scaling and
isolation. CT-based solutions have several drawbacks. They
only pass AC signals and cannot be used in DC measurement
applications. Their usable frequency response is limited, and
an inherent frequency-dependent phase shift needs to be
corrected. They are expensive, bulky, and easily tampered
with typically by unscrupulous consumers trying to undermine their electricity bill, e.g., the DC magnetic field of an
appropriately placed strong magnet can saturate the CTs core,
leading to a reduced current in the secondary being measured
without actually affecting the used current in the primary side.
In the conventional shunt resistor-based solution as shown
in Fig. 2, a small value resistor, typically about 200 ,
is put in series with the power line and the measurement
circuit directly connects across that hot-side resistor. Shuntbased solutions are attractive because the shunt resistors are
physically small, highly linear, can pass both AC and DC
signals, and (importantly) are very cheap to manufacture.
They are also immune to magnetic fields and therefore much
more difficult to tamper with. However, in order to isolate
the measurement IC directly connected to the shunt resistor,
a variety of undesirable external components are required.
Opto-couplers are typically used to isolate the data I/O pins,

and the measurement ICs power supply is typically realized

using a traditional transformer circuit, or capacitive division
techniques from the high voltage power line. These additional
external components offset the cost benefits of using the
cheaper shunt resistor.
To overcome the above problems, the worlds first
reported chip level, fully isolated ADC solution as shown
in Fig. 3 is presented. This system-in-package (SIP) solution integrates an isolated power converter (comprising three
die a high-voltage oscillator, an on-chip power transformer,
and a rectifier), a control and communication logic die, a
die containing on-chip data transformers, and an analog die
containing three  analog-to-digital converters (ADCs) (one
for current measurement and two for voltage measurements), a
voltage reference, LDO, temperature sensor, and other support
and communication circuitry. Because it includes all of the
isolation capability within the package, no external isolation
components are needed. It also enables many new portable
industrial and medical sensing applications where the voltage
isolation and safety is vital. Fig. 4 shows a generalized sensing
application in which the isolated ADC may be used. The ADC
can accept a peak differential input voltage of 500 mV with
a common mode voltage of up to 400 Vrms.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 10, OCTOBER 2016

III. D ESIGN AND I MPLEMENTATION

A. On-Chip Isolated DC-DC Converter
For many isolated data acquisition systems, there is a need
to transfer power from the low voltage system side to the
isolated high voltage side. To transfer DC power across the
isolation barrier, three stages are needed. Firstly, the DC power
is converted to AC power typically using an oscillator or
switching elements, then the AC power is transferred across
the isolation barrier using isolation components such as transformers, and finally the AC power is converted back to DC
on the isolated side. These isolation transformers are typically
discrete and bulky in nature, and reducing their size and cost
involves trade-offs in energy density and efficiency. Efforts
have been made to realize these transformers on printed circuit
boards or even on integrated circuits [4][7]. The following
describes the techniques used in this work to achieve isolated
power transfer using only integrated components.
There are many challenges in using integrated micro-sized
transformers for isolated power conversion. One of the key
challenges is the small ratio of inductance to resistance,
with limited area to generate inductance and limited metal
thickness to reduce series resistance. To maximize the quality
factor Q, the on-chip transformers need to operate at a very
high frequency, as Q is proportional to both frequency and the
inductance to resistance ratio as follows:

L
1 L
=
(1)
Q=
R C
R
However, to switch transformers at very high frequencies,
a standard power converter architecture, such as flyback,
will suffer from substantial switching and gate drive losses.
A resonant transformer-based oscillator is an energy-efficient
way to transfer power and minimize these losses at high
frequencies [6], [7]. Power conversion at high frequencies also
presents a major challenge for regulation. It is not practical to
regulate the power at the same frequency as power conversion,
especially with the requirement for the feedback signal to go
back through the isolation barrier, so a separate low-frequency
feedback path needs to be introduced.
The architecture for the fully integrated, isolated DC-DC
converter used in this work is shown in Fig. 5. It contains
an oscillator, an on-chip coreless micro transformer, and a
full-wave Schottky diode bridge rectifier. The transformer coil
and cross-coupled MOS devices form an LC oscillator which
generates a high frequency AC signal to transfer energy from
the primary low-voltage (LV) side to the secondary high
voltage (HV) side. The LC oscillation frequency is chosen
to match the peak Q frequency for the power transformer.
The relationship between Q and the oscillation frequency is
shown in Fig. 6. The optimal power transfer frequency, where
a decent Q can be obtained and the Schottky diodes can be
operated without too much reverse recovery loss, is found to
be around 200 MHz.
The equivalent circuit diagram of the LC oscillator is shown
in Fig. 7. The oscillator produces a differential waveform,
centered on VDD, with each side having an amplitude of
approximately VDD (also depicted in Fig. 10). To regulate the

Fig. 5.

Fully integrated isolated DC-DC converter.

Fig. 6.

Quality factor versus oscillation frequency.

Fig. 7.

Equivalent circuit diagram of the LC oscillator.

energy that is delivered, the LC oscillator is turned on and off

via the NMOS switching device M3 below the cross-coupled
NMOS devices M1 and M2 . That switch is controlled through
negative feedback based on the measured output voltage of the
DC-DC converter on the HV side where the ADCs are located.
A bang-bang control scheme is used to regulate the output
voltage of the power converter. As shown in Fig.5, the scaled

TAN et al.: A FULLY ISOLATED DELTA-SIGMA ADC FOR SHUNT BASED CURRENT SENSING

Fig. 8.

2235

Circuit model of a transformer-based LC tank

value of the output voltage VSE and a predetermined value

VREF are input to a comparator. The output of the comparator
is encoded, sent across the isolation barrier, and decoded by
the isolated data communication decoder. Based on whether
the isolated power converter output voltage is too high or too
low, a narrow or a wide pulse is selected to control the duration
of on time of the LC oscillator. This simplifies the feedback
control signal compared with [6] which uses a PWM scheme,
although it does lead to larger supply voltage variations on the
HV side.
On the HV side, four integrated Schottky diodes form a
full-wave bridge rectifier circuit, the output of which is lowpass filtered and subsequently powers the converter chip. For
efficiency reasons, the diodes are sized such that they stay
in the Schottky region during the rectification process [6].
As long as the diodes stay in the Schottky region, there
is no appreciable reverse recovery loss for the diodes up
to 200 MHz.
The output of the DC/DC converter needs to provide 3.3 V
and deliver at least 3 mA at 70% maximum duty cycle. Given
the output current requirements, Schottky diode sizes of 48
units of 5 m5 m are chosen to operate with a forward drop
of less than 0.5 V to ensure operation in the Schottky region
and to prevent significant reverse recovery loss at 200 MHz.
Transformer parameters were determined by the input power
needed for a given converter efficiency. For example, to ensure
a 20 mW output with a greater than 20% efficiency at full duty
cycle or 10 mW output at 50% duty cycle, the input power
needs to be 100 mW, or 30 mA at 3.3 V.
The transformer coupled resonator can be modeled as shown
in Fig. 8. There are two resonant modes, and for a symmetrical
primary and secondary where R1 = R2 = r , C1 = C2 = C
and L 1 = L 2 = L the resonating frequencies and input
impedance are given by [8]
1
1
C, and 22 =
C
(2)
12 =
L+M
LM
L+M
LM
, and Z I N (2 ) =
(3)
Z I N (1 ) =
2r C
2r C
It is desired that the oscillator be operated in the voltagelimited mode rather than the current-limited mode to get
large oscillation signals through the transformers for maximum power transfer. For the oscillator to operate in the
voltage-limited mode, we have
V = 0.5 L EFF i 2 f

(4)

where L EFF is the effective tank inductance, is the oscillator

frequency, and i is the peak tank current. For the tank to

Fig. 9.
On-chip micro transformer. (a) Cross section. (b) Top view.
(c) 3-D view.

operate in the low-frequency and high-input-impedance 1

mode (for high efficiency), we have L EFF = L + M. Using
V = 3.3 V, i = 30 mA 1.4, and f = 200 MHz, we get
L EFF = 125 nH. If the coupling is very good, then the primary
and secondary inductance can be set about 62.5 nH.
Once the diode and transformer parameters are known, the
oscillator switch sizes are chosen to minimize switching losses,
while also being careful not to present too much parasitic
capacitance so the oscillator can still operate at about 200 MHz
to achieve its peak quality factor. Iterations are required as the
efficiency may vary with the parameter variations for diodes,
transformers, and primary oscillator switches. For transformer
coupled oscillators, we also need to verify that the final
oscillator operates in the high-efficiency resonating mode with
high input impedance. The oscillator frequency of 200 MHz
is achieved with no extra parallel capacitance added to the
tank besides the intrinsic parasitics of the switches, diodes,
and the transformers. Any additional capacitance will lead to
a reduction of the oscillator frequency, the quality factors for
the transformers, and efficiency for the power conversion.
The power transformer cross section is shown in Fig. 9(a).
The top and bottom spirals are made of 6 m thick gold and
a 30 m thick polyimide layer provides isolation to better
than 5 kVrms. The primary and secondary transformer coils
are constructed using two spirals connected in an S-shape as
shown in Fig. 9(b). The primary coil is driven at the terminals
labeled P1 and P2 while its center-tap terminal C is held
at VDD. The secondary coil output terminals S1 and S2 drive
the rectifier circuit. At 200 MHz, even with a small diameter
of 600 m, the radiation from the windings is not negligible
with multiple turns. To minimize this radiation, counter-rotated
S-shaped coils were used so the flux from one spiral would
cancel the flux from the other spiral with a 180 degree phase
shift at least in the far field where radiation is measured.
To achieve 32 nH for each half of the S-shape, both spirals
have 8.5 turns, and the peak quality factor is optimized to be
around 5.7 for the top spiral and 4.5 for the bottom spiral both
at around 200 MHz, as shown in Fig. 6.
The transmission of power from the LV side to the isolated
HV side is also a disruptive influence on ADC performance.
If the 200 MHz power transfer signals are present and being

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Fig. 10.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 10, OCTOBER 2016

Isolated power converter timing.

Fig. 11.

rectified during ADC sampling instants (which occur on both

edges of the ADCs modulator clock), then the ADCs will
convert corrupted signals. Consequently, the transmission of
power across the isolation barrier must be coordinated with
the transmission of the modulator clock. This is achieved by
disabling OSC_enable in Fig. 7 sufficiently before issuing
the ADC clock edges to give the sampling process some
quiet time as shown in Fig. 10. The feedback signal from
the bang-bang control unit yields either a 70% or a 10%
duty cycle for the oscillator. These duty cycles limits are
chosen as maximum and minimum life support values in
the presence of high interference or tampering. Across all
process and operational corners, a continuous 70% duty cycle
was determined to never produce a destructively high supply
voltage on the ADC die, and a continuous 10% duty cycle
would always provide enough power to support minimum
sustainable operation and communication across the isolation
barrier. Within those duty cycle limits, the power supply
sensitivity of critical circuitry on the analog chip is further
reduced by powering those blocks from an internal LDO.
The power converter circuitry is designed to deliver 10 mW
at 24% efficiency. The main losses come from the transformers, accounting for 39% of the input power, followed by
the LC tank switches, accounting for 28%, and the Schottky
diodes and other parasitics constituting the remaining 9%. The
efficiency can be improved with lower resistance windings
either by making the windings thicker or by using a better
conductor such as copper. Reduction in diode series resistance
can lead to smaller diodes (with lower parasitics) for the same
load requirement, thus increasing the efficiency by optimizing
the transformer quality factors at higher frequencies.
B. DeltaSigma Modulators
In contemporary deltasigma converters with high input
signal bandwidths, continuous time architectures are preferred
since they provide inherent anti-aliasing and avoid the folding
down of sampled noise. In the target application of power
line monitoring and energy metering, input signal bandwidths
are typically below 5 kHz. However, the environment can
be polluted with a variety interference sources and therefore,
a switched-capacitor solution is more attractive. It is much
less sensitive to clock jitter and works more robustly with
large clock frequency variations, which can be an important
feature in these applications. Because the ADCs are measuring
energy consumption and money is involved, there are stringent
requirements on robustness especially with respect to
robustness in the presence of interference or the constantly
evolving tampering methods. As is often the case, simplicity
and high robustness go hand in hand and so a second order,

Loop diagram of the second-order deltasigma modulator.

single-bit, switched capacitor modulator was chosen. It has a

high tolerance of building block nonideality and sufficiently
high resolution thanks to oversampling and noise shaping [9].
The block diagram of the deltasigma modulators used is
shown in Fig. 11. A single-bit quantizer is adopted not only
because of the inherent linearity of a one bit feedback DAC,
but also because of the robustness achieved by transferring
only one bit per modulator at a time across the isolation barrier.
If a multi-bit quantizer was used, a random interference spike
at the wrong time would corrupt more information than if a
single bit was being used. Multibit communication per clock
cycle also complicates the design of the isolated digital timing
which would lead to lower system robustness, higher cost
and power consumption. A feedforward modulator structure
is chosen to yield a low integrator output swing and better
linearity compared with a feedback structure [10]. However,
compared with the well-known structure of [10], the feedforward path from input to the input of the quantizer is omitted
to avoid using below-ground sampling switches (described
in the following section) at the input of the quantizer. This
saves chip area and simplifies the design. Due to the lack of
a feedforward path from input to the quantizer, the second
integrator output will contain a signal component.
The loop filter order of the deltasigma modulator is chosen
based on the tradeoff between noise shaping and stability [9].
In the target application, stability of the system is a major
concern unexpected interference can temporarily over-range
the input signal to the deltasigma modulator and a higher
order modulator (a loop filter order greater than 2) usually
cannot inherently recover from such overshooting even after
the large input signal disappears. It also suffers from an overly
limited input signal range to ensure loop stability. A first-order
deltasigma modulator would require a high oversampling
ratio (OSR) to reduce the quantization noise to the required
level. Thus, for this design, a second-order modulator is chosen
for a high input range and inherent loop stability. The choice
of OSR is based on the balance between thermal noise and
quantization noise. An OSR of 256 is chosen to ensure the total
quantization noise and thermal noise meet the noise budget,
and, for optimal energy efficiency, the modulator should be
dominated by thermal noise. The sampling capacitor is sized
for the gain-of-one mode based on the specified thermal noise
(mainly kT/C noise) requirements.
C. Below Ground Sampling
The analog front-end (AFE) is powered with a single voltage
supply generated by the isolated power converter. The input
signals, whose full-scale values are 500 mV around ground,
are sampled by the ADC without a buffer to save power

TAN et al.: A FULLY ISOLATED DELTA-SIGMA ADC FOR SHUNT BASED CURRENT SENSING

Fig. 12.

2237

Below-ground sampling switch.

and cost. The input switch of the modulator must therefore

be designed to handle signals 500 mV below ground. The
simplified circuit of the input switch used in this design is
shown in Fig. 12 [11].
To allow the sampling of negative inputs, all transistors
directly connected to the analog input are PMOS devices
with accessible n-wells. The standard CMOS process used
supports a power supply voltage of nominally 3.3 V. MP1
is the main input switching device. Its gate is driven by a
boost circuit with bi-directional voltage clamps formed by
MP2-4. The inverter is powered by a 2.5 V supply (derived
from a separate LDO on the die). To turn the switch off,
CLK is driven to 0 V and VC is driven to 2.5 V. VG is
boosted up, but is clamped by MP2 at VIN + VTP , which is
sufficiently high to turn MP1 off. To turn the switch on, CLK
is driven to 2.5 V and VC is driven to 0 V. VG goes in the
negative direction, but MP3 and MP4 in diode connection form
a clamp at about VIN 2VTP , which is low enough to turn
on MP1. In addition to allowing below-ground sampling, this
circuit provides another benefit. The VGS on MP1 is ideally
signal independent if the nonideal effects on the transistors are
ignored. As a result, the signal dependency of the on-resistance
of MP1, and the charge injection and the clock feed-through
from MP1 are significantly reduced through bootstrapping,
which is a very desirable feature for a high performance
sampling circuit. The simulation results show that, with a fullscale input, the THD of the below-ground switching network
is 87 dBFS, and with a 6 dB input the THD of network
is 101 dBFS.
D. Communication Across the Isolation Barrier
Digital communication across an isolation barrier presents
several challenges. Without a galvanic connection, modulation
and demodulation schemes are typically used to send signals
across the barrier when using capacitive coupling [12], [13]
or transformer based inductive coupling [14][17]. There are
some limitations transferring isolated signals using capacitors.
Since a capacitor is a two-terminal device, both signal and
common-mode noise are transferred through the capacitor
simultaneously, leading to limited common-mode transient
immunity. A transformer, being a four-terminal device, couples
the signals differentially and provides an inherently higher
common mode noise rejection and is better suited as an
isolation coupling element for this purpose. However, driving
transformers can also be problematic due to the low impedance
levels involved.
Different digital pulse communication schemes across isolation barriers have been previously developed based on
inductive coupling. For example, a pulse polarity modulation

Fig. 13.

Communication of digital signals across the isolation barrier.

scheme encodes a 0 as a negative polarity pulse and a

1 as a positive polarity pulse [14] [15]. Another method
uses only single polarity pulses, e.g., encoding a 0 as
one pulse and a 1 as two consecutive pulses and includes
refreshing the data by periodically retransmitting and receiving
its logic state rather than only transmitting and receiving
logic state changes [16] [17]. Pulse-counting schemes carry
a latency penalty as pulses need to be counted during the
decoding process, and periodic refreshing schemes provide
desired robustness in the presence of high interference levels
at the expense of possible synchronization issues between
refreshes during the interference. In this design, we use two
data communication transformers one for each direction
between the two isolated sides. Each direction employs a modified pulse-counting scheme that minimizes data transmissionrelated emissions and enables clock recovery with a latency
identical to that of pulse polarity schemes.
As previously mentioned, the high rate 1-bit oversampled
modulator data for each of the three converters is transmitted across the barrier without any prior digital filtering and
decimation. This provides robustness against spurious events
which could interfere with the data transmission while the
information density at any given instant is at its lowest.
To improve robustness and to safeguard against tampering
techniques unknown to the authors, it was decided to not
use any digital registers on the analog side to hold persistent
configuration state. As such, all analog-side configuration data
is retransmitted with each modulator clock cycle.
To reduce costs, the regulation feedback bit for the isolated
power conversion loop is multiplexed into the data stream of
the three ADCs instead of through a dedicated transformer.
Fig. 13 shows the digital communication timing waveforms
between the two sides of the isolation barrier. The top ADC
CLK curve originates from the LV side (the master) and the
second curve shows the pulse clusters containing the encoded
modulator clock and configuration data to be transmitted
to the HV side (the slave). The following four curves are
waveforms on the HV side showing the received pulses at
the transformer output, the subsequently decoded configuration
data and modulator clock, and the 4-bit data (3 ADC outputs
and the isolated power feedback) are also encoded as pulse
clusters for transmission back to the LV side. Finally, the
last two curves on the LV side show the received pulses and
reconstructed data from the HV side.
Transmission of the configuration data and modulator clock
from the LV side to the HV side is achieved using encoded

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 10, OCTOBER 2016

pulse trains one pulse for a falling clock edge and two or
more pulses for a rising edge. If more than two pulses are
sent for a rising edge then the excess pulses are interpreted
as thermometer encoded configuration data for use in the
following clock cycle, e.g. to select the on-board temperature
sensor. When the analog side receives a cluster of pulses it
immediately initiates a local one-shot to envelop and count
the number of pulses received in the cluster. Rather than wait
for the pulse counting to complete to determine if a positive
or negative clock edge should be initiated, the analog side
immediately inverts its local clock to minimize the latency and
jitter with respect to the digital side. The subsequent pulse
counting decodes any configuration data and also validates
the preemptive clock edge decision. If an error occurred
in response to a spuriously induced glitch, e.g. the clock
polarity implemented is inconsistent with that decoded by the
pulse train, corrective action is taken on receipt of the next
pulse train.
The moment a new modulator clock edge is decoded on the
HV side, analog signal sampling occurs followed immediately
by the transmission of data from the previous clock cycle.
The HV side has four bits of data to transfer per clock cycle.
To keep power and radiated emissions to a minimum, two bits
are sent per clock edgethermometer encoded as 0, 1, 2, or
3 pulses, yielding an average of 1.5 pulses per clock edge,
or only three pulses per clock cycle for 4 bits of transmitted
data. Knowing that the HV side will respond with its data
immediately, the LV side starts counting received pulses from
the HV side until the next clock cycle commences, at which
time the received data are decoded and processed.

Fig. 14.

Fully isolated SIP in a modified 20-pin wide-body SOIC package.

Fig. 15.

Output spectrum for 500 mV, 50 Hz input.

Fig. 16.

Cumulative histogram of the ADC gain temperature coefficient.

IV. M EASUREMENT R ESULTS

Three deltasigma ADCs (two voltage channels and one
current channel) powered by the isolated power converter
were designed for domestic and industrial power monitoring
applications. The six die, which are assembled into a SIP
and shown in Fig. 14, are fabricated in various IC processes
to minimize the final cost. The ADC and digital die are
fabricated in a standard 3.3 V 0.25 m CMOS IC technology, the isolated power converter chips in 0.35 m DMOS
and the transformer die are fabricated in ADIs proprietary
iCoupler process. The ADC SIP is powered by a 3.3 V
supply while drawing 12.5 mA. It includes an analog die
containing three delta-sigma modulators, a voltage regulator,
a temperature transducer and other biasing circuits, a threedie isolated power converter subsystem, a transformer die
for digital communication, and a micro-controller die. The
operational efficiency achieved by the SIP is 22% while
maintaining guaranteed insulation specifications of 400 Vrms
continuous and 5 kVrms for one minute.
The spectrum of the decimated output bit stream for an input
voltage of 500 mV yielding an SNR of 74.4 dB and an SFDR
of 80.8 dB in a bandwidth of 3.3 kHz is shown in Fig. 15.
The AC PSRR is 90 dB with a 120 mVrms signal at 50 Hz on
the 3.3 V supply, and the DC PSRR is 80 dB. Other recently
published solutions for isolated current sensing [18], [19] use
magnetic sensors that can easily be tampered with and are
inherently more expensive than a simple shunt resistor.

In precision applications such as current sensing and power

monitoring, the temperature coefficient of the ADC gain drift
is also of interest. Fig. 16 shows the cumulative histogram

TAN et al.: A FULLY ISOLATED DELTA-SIGMA ADC FOR SHUNT BASED CURRENT SENSING

TABLE I
P ERFORMANCE S UMMARY

of the temperature coefficient of the ADC gain for temperatures between 40C and 85C. This measurement includes
both drift from the deltasigma modulator and the on-chip
reference. The main contributor to this gain drift is the onchip reference. The performance summary data for the isolated
ADC SIP is shown in Table I.
V. C ONCLUSION
The worlds first reported chip level fully isolated (power
and data) deltasigma ADC architecture has been presented.
The key attributes are the integrated isolated dc-dc converter
(which includes an on-chip transformer, oscillator and rectifier), control logic, and ADC (all of various IC technologies)
and the co-packaging of all die into an SIP. The three-channel
fully isolated ADC draws 12.5 mA from a 3.3 V supply and
the ADC achieves 74.4 dBFS SNR and 80.8 dBFS SFDR in
a bandwidth of 3.3 kHz.

2239

[7] N. Spina, V. Fiore, P. Lombardo, E. Ragonese, and G. Palmisano,

Current-reuse transformer-coupled oscillators with output power combining for galvanically isolated power transfer systems, IEEE Trans.
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[9] R. Schreier and G. C. Temes, Understanding DeltaSigma Data Converters, vol. 74. Piscataway, NJ, USA: IEEE, 2005.
[10] J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, Wideband lowdistortion delta-sigma ADC topology, Electron. Lett., vol. 37, no. 12,
pp. 737738, Jun. 2001.
[11] E. Nestler, Switched capacitor circuit adapted to store charge on a
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[12] A. Krone et al., A CMOS direct access arrangement using digital
capacitive isolation, in IEEE Int. Solid-State Circuits Conf. (ISSCC)
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[13] G. Knoedl, Jr., S. A. Rawls, L. J. Turgeon, and J. W. Bess, A monolithic
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Power Electron. Conf., Mar. 1989, pp. 165170.
[14] N. Miura et al., A high-speed inductive-coupling link with burst
transmission, IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 947955,
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[15] S. Kaeriyama et al., A 2.5 kV isolation 35 kV/s CMR 250 Mbps
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[16] B. Chen, Isolation in digital power supplies using micro-transformers,
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[18] M. F. Snoeij, V. Schaffer, S. Udayashankar, and M. V. Ivanov,
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[19] J. Jiang and K. Makinwa, A hybrid multipath CMOS magnetic sensor
with 210 Trms resolution and 3 MHz bandwidth for contactless current
sensing, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech.
Papers, 2016, pp. 204205.

ACKNOWLEDGMENTS
The authors would like to thank their colleagues from the
energy metering and isolator teams at Analog Devices Inc.,
both in Wilmington, MA, USA, and Beijing, China, for their
help during design, layout, and evaluation.
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[1] S. Ziegler, R. C. Woodward, H. H.-C. Iu, and L. J. Borle, Current sensing techniques: A review, IEEE Sensors J., vol. 9, no. 4, pp. 354376,
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Zhichao
Tan
(S09M13) received
the
B.Eng. degree from Xian Jiaotong University,
Xian, China, in 2004, the M.Eng. degree from
Peking University, Beijing, China, in 2008, and the
Ph.D. degree from Delft University of Technology,
Delft, The Netherlands, in 2013. His Ph.D. research
topic was Energy-Efficient Capacitive-Sensor
Interfaces. The results of his research have
been applied in commercial sensor products in
cooperation with NXP Semiconductor.
Since June 2013, he has been with Analog
Devices Inc., where he is currently a Staff IC Design Engineer, working on
low-power high-precision ADC and MEMS sensor interface for accelerometer
and gyroscope. In addition to two pending U.S. patents, he has authored
and coauthored two book chapters and 14 technical journal and conference
papers. His current research interests are in the area of energy-efficient
sensor interfaces, precision analog circuits, and ultralow-power ADCs.
Dr. Tan is currently an associate editor of the IEEE T RANSACTIONS
ON C IRCUITS AND S YSTEMS I: R EGULAR PAPERS and a member of
the Technical Program Committee of IEEE Sensors Conference and IEEE
International Instrumentation and Measurement Technology Conference. He is
also a member of the Technical Committee on MEMS and Nanotechnology
of the IEEE Industrial Electronics Society. He twice received the IEEE
Solid-State Circuits Society Student Travel Grant Award (STGA), from
the 2011 IEEE Asian Solid-State Circuits Conference and the 2012 IEEE
Symposium on VLSI Circuits.

2240

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 10, OCTOBER 2016

Mick Mueck (S80M85) received the B.S. degree

in electronics engineering from Royal Melbourne
Institute of Technology, Melbourne, Australia,
in 1982.
From 1982 to 1985, he was with AWA Microelectronics, designing custom analog ICs. From 1985
to 1987, he was with Royal Melbourne Institute
of Technology, teaching analog electronics and IC
design. From 1988 to 2007, he was with Analog
Devices, working on ADC design specializing in
precision SAR converters. From 2007 to 2008, he
was with Texas Instruments as the Chief Technologist in the SAR and Touch
Screen group. Since 2008, he has been with Analog Devices designing MEMS,
Energy Metering and SAR converter products. His research interests include
precision SAR converters and sensor AFE circuits.

Xiao Hong Du received the B.S. degree in

electrical engineering from Huazhong University
of Science and Technology, Wuhan, China, and
the Ph.D. degree in electrical engineering from
Pennsylvania State University, University Park,
PA, USA.
He is currently the Senior Staff Analog Design
Engineer with Analog Devices, Wilmington,
MA, USA. He holds 13 U.S. patents. His research
is in the field of integrated analog circuit design
where his interests have included A/D converters,
analog/mixed-signal circuits, bandgap references, amplifiers, and oscillators.

Lawrence Getzin received the B.S. degree in electrical engineering from DeVry Institute of Technology, Chicago, IL, USA.
Currently, he is an IC Design Manager and Senior
Staff IC Design Engineer with Analog Devices,
Wilmington, MA, USA. His interests include architecture and design of next-generation AFE and SOC
devices with focus on energy measurement systems.
He holds four issued U.S. patents.

Michael
Guidry
received the S.B. and
M.Eng. degrees in electrical engineering from the
Massachusetts Institute of Technology, Cambridge,
MA, USA, in 1999 and 2000, respectively.
Since 2011, he has been Analog and Mixed-Signal
Design Engineer with Analog Devices, Wilmington,
MA, USA, developing precision data conversion
solutions for the energy market. From 2009 to 2011,
he was with RF Integration, Billerica, MA, USA,
designing IF and baseband signal conditioning
blocks, and from 2000 to 2009 he was an Analog
Design Engineer for National Semiconductor, Salem, NH, USA, working on
high-speed ADC and DAC products.

Shane Keating received the B.E. degree from the

University Limerick, Limerick, Ireland, in 2003.
He was then with the Digital design team at ADI
Limerick between 2003 and 2005, working on physical design flows, RTL to GDS2. In 2005, he moved
to ADI USA as a Low-Power Digital Design and
Implementation Engineer. He is currently a Digital
Design Engineer with the MEMs (Micro-ElectroMechanical Systems) team working on ultralowpower design.

Xing Xing received the B.S. degree in physics from

Nanjing University, Nanjing, China, in 2006, and the
Ph.D. degree in electrical and computer engineering
from Northeastern University, Boston, MA, USA,
in 2011.
Her research was mainly focused on integrated
magnetics and vibration energy harvesting. She was
a Device Engineer with Analog Devices Inc. from
July 2011 to April 2016.

Flow Zhao received the B.Sc. degree in electrical

engineering, in 2001, and M.Sc degree in microelectronics from NanKai University, 2004.
He joined ADI Beijing Design Center (BDC)
in 2004. He is currently a Senior Staff Design
Engineer and Design Manager of BDC ISO product
line, working on integrated isolated products.

Baoxing Chen received the B.S. degree in physics

from Nanjing University, Nanjing, China, in 1989,
and the M.S. degree in electrical engineering and
Ph.D. degree in physics, both in 1997, from the
University of Michigan, Ann Arbor, MI, USA.
He joined Analog Devices in 1997. He pioneered
the use of micro-transformers for transmitting signal
and power through the isolation barrier, which has
found broad adoption in many isolation applications
with over 1.5 billion channels of isolation shipped.
At ADI, he has been leading iCoupler and iso
Power technology developments including circuit architectures and process
developments. He has authored or coauthored over 30 papers, and he holds
over 25 U.S. patents. His current research interests include power supply
on-chip and chip-scale energy harvesting.
Dr. Chen is an ADI Fellow.