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Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique For DSRC Applications

The document proposes a VLSI architecture that fully reuses hardware for FM0 and Manchester encoding using the similarity-oriented logic simplification technique. This improves the hardware utilization rate from 57.14% to 100% for both encodings. The design was evaluated in a 0.18-micron process and achieved maximum frequencies of 2 GHz for Manchester and 900 MHz for FM0, consuming 1.58 mW and 1.14 mW respectively. The area is 65.98 x 30.43 microns and supports DSRC standards of multiple regions.

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Don Raju
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58 views

Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique For DSRC Applications

The document proposes a VLSI architecture that fully reuses hardware for FM0 and Manchester encoding using the similarity-oriented logic simplification technique. This improves the hardware utilization rate from 57.14% to 100% for both encodings. The design was evaluated in a 0.18-micron process and achieved maximum frequencies of 2 GHz for Manchester and 900 MHz for FM0, consuming 1.58 mW and 1.14 mW respectively. The area is 65.98 x 30.43 microns and supports DSRC standards of multiple regions.

Uploaded by

Don Raju
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Fully Reused VLSI Architecture of FM0/Manchester Encoding

Using SOLS Technique for DSRC Applications


Abstract:
The dedicated short-range communication (DSRC) is an emerging technique to push the
intelligent transportation system into our daily life. The DSRC standards generally adopt FM0
and Manchester codes to reach dc-balance, enhancing the signal reliability. Nevertheless, the
coding-diversity between the FM0 and Manchester codes seriously limits the potential to design
a fully reused VLSI architecture for both. In this paper, the similarity-oriented logic
simplification (SOLS) technique is proposed to overcome this limitation. The SOLS technique
improves the hardware utilization rate from 57.14% to 100% for both FM0 and Manchester
encodings. The performance of this paper is evaluated on the post layout simulation in Taiwan
Semiconductor Manufacturing Company (TSMC) 0.18-m 1P6M CMOS technology. The
maximum operation frequency is 2 GHz and 900 MHz for Manchester and FM0 encodings,
respectively. The power consumption is 1.58 mW at 2 GHz for Manchester encoding and 1.14
mW at 900 MHz for FM0 encoding. The core circuit area is 65.98 30.43 m2. The encoding
capability of this paper can fully support the DSRC standards of America, Europe, and Japan.
This paper not only develops a fully reused VLSI architecture, but also exhibits an efficient
performance compared with the existing works.

Existing Method:
The dedicated short-range communication (DSRC) is a protocol for one- or two-way
medium range communication especially for intelligent transportation systems. it is short-range
communication. The DSRC standards generally adopt FM0 and Manchester codes to reach dc
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balance, enhancing the signal reliability. Nevertheless, the coding-diversity between the FM0 and
Manchester codes seriously limits the potential to design a fully reused VLSI architecture for
both.

Proposed Method:
In this paper, the similarity-oriented logic simplification (SOLS) technique is proposed to
overcome this limitation. The SOLS technique improves the hardware utilization rate from
57.14% to 100% for both FM0 and Manchester encodings.

The

literature

proposes

VLSI

architecture of Manchester encoder for optical communications. This design adopts the CMOS
inverter and the gated inverter as the switch to construct Manchester encoder. It is implemented
by 0.35-m CMOS technology and its operation frequency is 1 GHz. The literature further
replaces the architecture of switch in by the nMOS device. The literature develops a high-speed
VLSI architecture almost fully reused with Manchester and Miller encodings for radio frequency
identification (RFID) applications. This paper not only develops a fully reused VLSI
architecture, but also exhibits an efficient performance compared with the existing works.

Applications:
1. Dedicated short-range communication
2. Micro processor..etc..

Advantages:
1. Efficient performance
2. Area, power

System Configuration:Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore
www.pvrtechnology.com, E-Mail: [email protected], Ph: 81432 71457

In the hardware part a normal computer where Xilinx ISE 14.3 software can be easily
operated is required, i.e., with a minimum system configuration
HARDWARE REQUIREMENT
Processor

Pentium III

Speed

1.1 GHz

RAM

1 GB (min)

Hard Disk

- 40 GB

Floppy Drive

1.44 MB

Key Board

Standard Windows Keyboard

Mouse

- Two or Three Button Mouse

Monitor

SVGA

SOFTWARE REQUIREMENTS
Operating System

:Windows95/98/2000/XP/Windows7

Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore
www.pvrtechnology.com, E-Mail: [email protected], Ph: 81432 71457

Front End

: Modelsim 6.3 for Debugging and Xilinx 14.3 for

Synthesis and Hard Ware Implementation

This softwares where Verilog source code can be used for design
implementation.

Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore
www.pvrtechnology.com, E-Mail: [email protected], Ph: 81432 71457

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