PIC 16F877A:

High-Performance RISC CPU:

All single-cycle instructions except for program branches, which are two-cycle

Operating speed: DC 20 MHz clock input DC 200 ns instruction cycle

Up to 8K x 14 words of Flash Program Memory, Up to 368 x 8 bytes of Data

Memory (RAM), Up to 256 x 8 bytes of EEPROM Data Memory

Pinout compatible to other 28-pin or 40/44-pin PIC16CXXX and PIC16FXXX

microcontrollers

Peripheral Features:

Timer0: 8-bit timer/counter with 8-bit prescaler

Timer1: 16-bit timer/counter with prescaler, can be incremented during Sleep via
external crystal/clock

Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

Two Capture, Compare, PWM modules Capture is 16-bit, max. resolution is 12.5
ns Compare is 16-bit, max. resolution is 200 ns. PWM max. resolution is 10-bit

Synchronous Serial Port (SSP) with SPI (Master mode) and I2C
(Master/Slave)

Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with

9-bit address detection

Parallel Slave Port (PSP) 8 bits wide with external RD, WR and CS controls
(40/44-pin only)

Brown-out detection circuitry for Brown-out Reset (BOR)

Analog Features:
10-bit, up to 8-channel Analog-to-Digital Converter (A/D)
Brown-out Reset (BOR)
Analog Comparator module with:
- Two analog comparators

- Programmable on-chip voltage reference

(VREF) module
- Programmable input multiplexing from device inputs and internal voltage reference
- Comparator outputs are externally accessible
Special Microcontroller Features:
100,000 erase/write cycle Enhanced Flash program memory typical
1,000,000 erase/write cycle Data EEPROM memory typical
Data EEPROM Retention > 40 years
Self-reprogrammable under software control
In-Circuit Serial Programming (ICSP) via two pins
Single-supply 5V In-Circuit Serial Programming
Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
Programmable code protection
Power saving Sleep mode
Selectable oscillator options
In-Circuit Debug (ICD) via two pins
CMOS Technology:
Low-power, high-speed Flash/EEPROM technology
Fully static design
Wide operating voltage range (2.0V to 5.5V)
Commercial and Industrial temperature ranges
Low-power consumption

Pin diagram:

Device features

Block diagram

Pin description:
Pin 13
OSC1/CLKI Oscillator crystal or external clock input.
OSC1 Oscillator crystal input or external clock source input. ST buffer when configured
in RC mode, otherwise CMOS.
CLKI External clock source input. Always associated with pin function OSC1
Pin 14
OSC2/CLKO Oscillator crystal or clock output
OSC2 Oscillator crystal output- Connects to crystal or resonator in Crystal Oscillator
mode.
CLKO - In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1
and denotes the instruction cycle rate.
Pin 1
MCLR/VPP Master Clear (input) or programming voltage (output)
MCLR Master Clear (Reset) input. This pin is an active low Reset to the device
VPP Programming voltage input
Pin 2
RA0/AN0
RA0 Digital I/O
AN0 Analog input 0
PORTA is a bidirectional I/O port
Pin 3
RA1/AN1
RA1 Digital I/O
AN1 Analog input 1

Pin 4
RA2/AN2/VREF-/CVREF
RA2 Digital I/O
AN2 Analog input 2.
VREF A/D reference voltage (Low) input.
CVREF Comparator VREF output
Pin 5
RA3/AN3/VREF+
RA3 Digital I/O
AN3 Analog input 3
VREF+ A/D reference voltage (High) input
Pin 6
RA4/T0CKI/C1OUT
RA4 Digital I/O Open-drain when configured as output.
T0CKI Timer0 external clock input
C1OUT Comparator 1 output
Pin 7
RA5/AN4/SS/C2OUT
RA5 Digital I/O
AN4 Analog input 4.
SS SPI slave select input
C2OUT Comparator 2 output
PORTB is a bidirectional I/O port. PORTB can be software programmed for
internal weak pull-up on all inputs.

Pin 33
RB0/INT
RB0 Digital I/O
INT External interrupt
Pin 34
RB1 Digital I/O
Pin 35
RB2 Digital I/O
Pin 36
RB3/PGM
RB3 Digital I/O
PGM Low-voltage ICSP programming enable pin
Pin 37
RB4 Digital I/O
Pin 38
RB5 Digital I/O
Pin 39
RB6/PGC
RB6 Digital I/O
PGC In-circuit debugger and ICSP programming clock
Pin 40
RB7/PGD
RB7 Digital I/O
PGD In-circuit debugger and ICSP programming data

PORTC is a bidirectional I/O port.

Pin 15
RC0/T1OSO/T1CKI
RC0 Digital I/O
T1OSO Timer1 oscillator output.
T1CKI Timer1 external clock input.
Pin 16
RC1/T1OSI/CCP2
RC1 Digital I/O
T1OSI Timer1 oscillator input
CCP2 Capture2 input, Compare2 output, PWM2 output
Pin 17
RC2/CCP1
RC2 Digital I/O
CCP1 Capture1 input, Compare1 output, PWM1 output.
Pin 18
RC3/SCK/SCL
RC3 Digital I/O
SCK Synchronous serial clock input/output for SPI mode
SCL Synchronous serial clock input/output for I2C mode
Pin 23
RC4/SDI/SDA
RC4 Digital I/O
SDI SPI data in
SDA I2C data I/O

Pin 24
RC5/SDO
RC5 Digital I/O
SDO SPI data out
Pin 25
RC6/TX/CK
RC6 Digital I/O
TX USART asynchronous transmit
CK USART1 synchronous clock
Pin 26
RC7/RX/DT
RC7 Digital I/O
RX USART asynchronous receive
DT USART synchronous data
PORTD is a bidirectional I/O port or Parallel Slave Port when interfacing to a
microprocessor bus.
Pin 19
RD0/PSP0
RD0 Digital I/O
PSP0 Parallel Slave Port data
Pin 20
RD1/PSP1
RD1 Digital I/O
PSP1 Parallel Slave Port data

Pin 21
RD2/PSP2
RD2 Digital I/O
PSP2 Parallel Slave Port data
Pin 22
RD3/PSP3
RD3 Digital I/O
PSP3 Parallel Slave Port data
Pin 27
RD4/PSP4
RD4 Digital I/O
PSP4 Parallel Slave Port data
Pin 28
RD5/PSP5
RD5 Digital I/O
PSP5 Parallel Slave Port data
Pin 29
RD6/PSP6
RD6 Digital I/O
PSP6 Parallel Slave Port data
Pin 30
RD7/PSP7
RD7 Digital I/O
PSP7 Parallel Slave Port data

PORTE is a bidirectional I/O port.

Pin 8
RE0/RD/AN5
RE0 Digital I/O
RD Read control for Parallel Slave Port
AN5 Analog input 5
Pin 9
RE1/WR/AN6
RE1 Digital I/O
WR Write control for Parallel Slave Port
AN6 Analog input 6
Pin 10
RE2/CS/AN7
RE2 Digital I/O
CS Chip select control for Parallel Slave Port
AN7 Analog input 7
Pins 12, 31
VSS Ground reference for logic and I/O pins
Pins 11, 32
VDD Positive supply for logic and I/O pins

MEMORY ORGANIZATION
There are three memory blocks in each of the PIC16F87XA devices. The program
memory and data memory have separate buses so that concurrent access can occur and is
detailed in this section.

Program Memory Organization

The PIC16F877A device have a 13-bit program counter capable of addressing an 8K
word x 14 bit program memory space. The PIC16F877A device have 8K words x 14 bits
of Flash program memory. Accessing a location above the physically implemented
address will cause a wraparound. The Reset vector is at 0000h and the interrupt vector is
at 0004h.
Program Memory Map and Stack

Data Memory Organization

The data memory is partitioned into multiple banks which contain the General Purpose
Registers and the Special Function Registers. Bits RP1 (Status<6>) and RP0 (Status<5>)
are the bank select bits.

Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved
for the Special Function Registers. Above the Special Function Registers are General
Purpose Registers, implemented as static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special Function Registers from one bank may
be mirrored in another bank for code reduction and quicker access.
Register File Map

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and peripheral modules for
controlling the desired operation of the device. These registers are implemented as static
RAM. The Special Function Registers can be classified into two sets: core (CPU) and
peripheral. Those registers associated with the core functions are described in detail in
this section.
Status Register
The Status register contains the arithmetic status of the ALU, the Reset status and the
bank select bits for data memory. The Status register can be the destination for any
instruction, as with any other register. If the Status register is the destination for an
instruction that affects the Z, DC or C bits, then the write to these three bits is disabled.
These bits are set or cleared according to the device logic. Furthermore, the TO and PD

bits are not writable, therefore, the result of an instruction with the Status register as
destination may be different than intended.
For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves
the Status register as 000u u1uu (where u = unchanged). It is recommended, therefore,
that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the Status
register because these instructions do not affect the Z, C or DC bits from the Status
register.

OPTION_REG Register
The OPTION_REG Register is a readable and writable register, which contains various
control bits to configure the TMR0 prescaler/WDT post scaler (single assignable register
known also as the prescaler), the external INT interrupt, TMR0 and the weak pull-ups on
PORTB.

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

INTCON Register
The INTCON register is a readable and writable register, which contains various enable
and flag bits for the TMR0 register overflow, RB port change and external RB0/INT pin
interrupts.

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue
to set the bit. Reading PORTB will end the mismatch condition and allow the bit to be
cleared.(must be cleared in software).
0 = None of the RB7:RB4 pins have changed state.

PCON Register
The Power Control (PCON) register contains flag bits to allow differentiation between a
Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an
external MCLR Reset.

bit 7-2 Unimplemented: Read as 0

bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register
which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but
are indirectly writable through the PCLATH register. On any Reset, the upper bits of the
PC will be cleared.

STACK
The PIC16F87XA family has an 8-level deep x 13-bit wide hardware stack. The stack
space is not part of either program or data space and the stack pointer is not readable or
writable. The PC is PUSHed onto the stack when a CALL instruction is executed, or an
interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a
RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer. This means that after the stack has been PUSHed
eight times, the ninth push overwrites the value that was stored from the first push. The
tenth push overwrites the second push (and so on).
Program Memory Paging
All PIC16F87XA devices are capable of addressing a continuous 8K word block of
program memory. The CALL and GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page. When doing a CALL or GOTO
instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a
CALL or GOTO instruction, the user must ensure that the page select bits are
programmed so that the desired program memory page is addressed. If a return from a
CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack.
Therefore, manipulation of the PCLATH<4:3> bits is not required for the RETURN
instructions (which POPs the address from the stack).
Note: The contents of the PCLATH register are unchanged after a RETURN or RETFIE
instruction is executed. The user must rewrite the contents of the PCLATH register for
any subsequent subroutine calls or GOTO instructions.
The below example shows the calling of a subroutine in page 1 of the program memory.
This example assumes that PCLATH is saved and restored by the Interrupt Service
Routine (if interrupts are used).
Example: CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0
ORG 0x500
BCF PCLATH, 4
BSF PCLATH, 3; Select page 1
;( 800h-FFFh)
CALL SUB1_P1; Call subroutine in
: page 1 (800h-FFFh)
:

ORG 0x900; page 1 (800h-FFFh)

SUB1_P1
: called subroutine
; page 1 (800h-FFFh)
:
RETURN; return to
; Call subroutine
; in page 0
;( 000h-7FFh)
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
PORTA and the TRISA Register
PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is
TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e.,
put the corresponding output driver in a High-Impedance mode). Clearing a TRISA bit (=
0) will make the corresponding PORTA pin an output (i.e., put the contents of the output
latch on the selected pin).
Reading the PORTA register reads the status of the pins, whereas writing to it will write
to the port latch. All write operations are read-modify-write operations. Therefore, a write
to a port implies that the port pins are read, the value is modified and then written to the
port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become
the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open-drain
output. All other PORTA pins have TTL input levels and full CMOS output drivers. Other
PORTA pins are multiplexed with analog inputs and the analog VREF input for both the
A/D converters and the comparators. The operation of each pin is selected by
clearing/setting the appropriate control bits in the ADCON1 and/or CMCON registers.

Note: On a Power-on Reset, these pins are configured as analog inputs and read as 0.
The comparators are in the off (digital) state.
The TRISA register controls the direction of the port pins even when they are being used
as analog inputs. The user must ensure the bits in the TRISA register are maintained set
when using them as analog inputs.

PORTB and the TRISB Register

PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is
TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e.,
put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (=
0) will make the corresponding PORTB pin an output (i.e., put the contents of the output
latch on the selected pin). Three pins of PORTB are multiplexed with the In-Circuit
Debugger and Low-Voltage Programming function: RB3/PGM, RB6/PGC and
RB7/PGD.
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all
the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The weak
pull-up is automatically turned off when the port pin is configured as an output. The pullups are disabled on a Power-on Reset.
Four of the PORTB pins, RB7:RB4, have an interruption- change feature. Only pins
configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured
as an output is excluded from the interruption-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on the last read of PORTB. The
mismatch outputs of RB7:RB4 are ORed together to generate the RB port change
interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine,
can clear the interrupt in the following manner: a) Any read or write of PORTB. This will
end the mismatch condition. b) Clear flag bit RBIF. A mismatch condition will continue
to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit
RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key
depression operation and operations where PORTB is only used for the interrupt-onchange feature. Polling of PORTB is not recommended while using the interrupt-onchange feature.
This interrupt-on-mismatch feature, together with software configurable pull-ups on these
four pins, allow easy interface to a keypad and make it possible for wake-up on key

depression. RB0/INT is an external interrupt input pin and is configured using the
INTEDG bit (OPTION_REG<6>).

PORTC and the TRISC Register

PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is
TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e.,
put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (=
0) will make the corresponding PORTC pin an output (i.e., put the contents of the output
latch on the selected pin). PORTC is multiplexed with several peripheral functions.
PORTC pins have Schmitt Trigger input buffers. When the I2C module is enabled, the
PORTC<4:3> pins can be configured with normal I2C levels, or with SMBus levels, by
using the CKE bit (SSPSTAT<6>). When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit
to make a pin an output, while other peripherals override the TRIS bit to make a pin an
input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modify
write instructions (BSF, BCF and XORWF) with TRISC as the destination, should be
avoided. The user should refer to the corresponding peripheral section for the correct
TRIS bit settings.

PORTD and TRISD Registers

PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually
configurable as an input or output.
PORTD can be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by
setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.

PORTE and TRISE Register

PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7) which are
individually configurable as inputs or outputs. These pins have Schmitt Trigger input

buffers. The PORTE pins become the I/O control inputs for the microprocessor port
when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make certain that
the TRISE<2:0> bits are set and that the pins are configured as digital inputs. Also,
ensure that ADCON1 is configured for digital I/O. In this mode, the input buffers are
TTL. PORTE pins are multiplexed with analog inputs. When selected for analog input,
these pins will read as 0s. TRISE controls the direction of the RE pins, even when they
are being used as analog inputs. The user must make sure to keep the pins configured as
inputs when using them as analog inputs.

Parallel Slave Port Status/Control Bits:

bit 7 IBF: Input Buffer Full Status bit

1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6 OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared
in software)
0 = No overflow occurred
bit 4 PSPMODE: Parallel Slave Port Mode Select bit
1 = PORTD functions in Parallel Slave Port mode
0 = PORTD functions in general purpose I/O mode
bit 3 Unimplemented: Read as 0
PORTE Data Direction Bits:
bit 2 Bit 2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1 Bit 1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0 Bit 0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output