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EBT435 Polymer in Electronic Applications: Plteh@unimap - Edu.my

An electronic package protects electronic components from environmental hazards while also enabling testing and assembly. It provides physical protection, heat dissipation, electrical connections, and signal timing. Goals of electronic packaging include maximizing input/output, minimizing thermal and size issues, ensuring environmental protection and low cost. Packaging hierarchy involves different levels from the transistor to larger systems. Challenges in packaging include increasing functionality and speed while reducing size, along with rising input/output needs, signal timing issues, power demands, and heat dissipation problems.

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Tarani Tharan
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137 views

EBT435 Polymer in Electronic Applications: Plteh@unimap - Edu.my

An electronic package protects electronic components from environmental hazards while also enabling testing and assembly. It provides physical protection, heat dissipation, electrical connections, and signal timing. Goals of electronic packaging include maximizing input/output, minimizing thermal and size issues, ensuring environmental protection and low cost. Packaging hierarchy involves different levels from the transistor to larger systems. Challenges in packaging include increasing functionality and speed while reducing size, along with rising input/output needs, signal timing issues, power demands, and heat dissipation problems.

Uploaded by

Tarani Tharan
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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EBT435

Polymer in Electronic Applications

[email protected]

Introduction and Overview of


electronic packaging
An electronic package is defined as that portion of an
electronic structure that serves to protect an
electronic/electrical element from its environment and the
environment from the electronic/electrical element.
In addition to provide encapsulation for
environmental protection, a package must also allow
for complete testing of the packaged device and a
high-yield method of assembly to the next level of
integration.

Function of package:
1. A physical housing to provide protection from mechanical and
chemical hazards (a structure to physically support the chip
from environment).
2. An adequate means of removing heat generated by the chips
or system (dissipate heat).

3. Electrical connections to allow signal and power access to and


from the chip (Distribute signal and power).
4. Enable appropriate signal timing for desired performance
5. A wiring structure to provide interconnection between the
chips of an electronic system.

GOALS OF ELECTRONIC PACKAGING

Maximize I/O
Minimize thermal issues
Heat dissipation
Thermal stress
Environmental protection
and encapsulation
Lowest cost needed to get results
Drive to continuously reduce size and power

Die: also known as chip. Sawn out from the big


silicon wafer.

Packaging hierarchy
Level 0: Logic gate, transistor, gate-to-gate interconnections on a monolithic silicon
chip.
Level 1: Packaging of silicon chips into dual-in-line packages (DIPs), small outline
integrated circuit (SOICs), chip carriers, multichip packages, and so on, and
the chip-level interconnects that join the chip to the lead frames.

Level 2: Printed wiring board (PWB), also referred to as printed circuit board (PCB),
level of interconnections. Printed conductor paths connect the device leads
of components to PWBs and to the electrical edge connectors for off-theboard interconnection.
Level 3:

Connections between two subassemblies. For example, a rack or frame


may hold several shelves of subassemblies that must be connected
together to make up a complete system.

Level 4: Connections between physically separate systems such as host computer to


terminals, computer to printer, and so on.

Example of single and multiple chip packages

Multiple chip module:


a single electronic package
containing more than one IC.
The ICs are interconnected
through a substrate

Packaging hierarchy
Transistor to
transistor
(Level 0)
Chip to package
(Level 1)
Package to board
(Level 2)

Board to rack
(Level 3)
Rack to System
(Level 4)

Summary of IC packaging

First level interconnection


First level packaging ( or interconnection) refers to the
technology required to get electrical signals into and out of a
single transistor or IC; in other words, the connections
required between the bonding pads on the IC and the pins of
the package.

In general, first level interconnection assembly configurations


are accomplished by:
1. Wire bonding,
2. Flip-chip bonding,
3. Tape-Automated Bonding.

1. Wire Bonding
The oldest method, but is still the dominant
method used today, particularly for chips
with a moderate number of
inputs/outputs(I/O).
This technique involves connecting gold or
aluminum wires between the chip bonding
pads, located around the periphery of the
chip, and the contact points on the package.
This process has been automated for many years, but it is still time
consuming because each wire requires two bonding operations, and must
be attached individually.
Other limitations of wire bonding include the requirement for minimum
spacing between adjacent bonding sites to provide sufficient room for the
bonding tool, the number of bonding pads that can be located around the
periphery of the chip, signal delay, and crosstalk between adjacent wires.
Of all of the chip-to-package interconnection types, the electrical
performance of wire-bonds is the lowest.

Example of wire bonding

Wire diamater range from


1.2 mil, 1 mil, 0.9 mil &
0.8 mil

2. Flip-Chip Bonding

The chip is mounted upside down onto a


carrier, module, or PWB. Electrical
connection is made via solder bumps. The
solder bumps are located over the surface of
the chip in a somewhat random pattern or
an array so that periphery limitation, such as
that encountered in wire bonding, does not
limit the I/O capability.

The I/O density is primarily limited by the minimum distance between adjacent
bonding pads on the chip and the amount of chip area that can be dedicated to
interconnection.
Additionally, the interconnect distance between chip and package is minimized since
bumps can essentially be located anywhere on the chip.
Although this technique is attractive for use in multichip packaging technology
because chips can be located very close together, fatigue of solder joints due to
thermal expansion mismatch of the chip-bond-substrate, heat removal from the back
of the chip, and difficulty inspecting the solder joints after the chip has been
attached to the substrate offer special challenges to the packaging specialist.

Example of flip chip

Tape-Automated bonding

TAB is a connection technique for attaching semiconductor die to a variety of


packaging media, including single chip and multichip packages.
TAB uses a premanufactured lead frame as a substitute for wire bonding. The
lead frame presents a uniform array of inner leads to be attached to the bond
pads on the surface of the die.
In this technique, ICs first mounted on a flexible polymer tape, such as
polyimide, containing repeated, flat, wide copper interconnection patterns
formed lithographically from a metal laminate.
Each pad on the IC is aligned to a metal interconnection stripe on the tape and
attachment is effected by thermocompression bonding.
There are cost overhead for the tape design and tooling for each chip size and
therefore, TAB is suited to high volume application.

TAB concept

TAB assembly configurations


TAB parts can be assembled on three
basic configurations: Conventional TAB,
flip TAB and cavity TAB.
Conventional TAB consists of mounting
the die with backside attached to the
substrate or package.
Leads are formed to facilitate the
connection from the plane of die to the
plane of the substrate package.
Flip TAB consists of mounting the die
with the active surface facing the
substrate or package.
Leads in flip TAB are shorter relative to
conventional TAB.
Cavity TAB is similar the flip TAB in that
the leads are shorter.

Wire bond package vs Flip chip package

Second level interconnection


Level 2 interconnection refers to the electrical connection of
an IC to a circuit board, the most common one being a
conventional PWB.
Following level 1 interconnection, single IC chips normally
undergo encapsulation in either plastic or ceramic based
packages prior to connection to a PWB.

Challenges

There always has been and will continue to be motivation to pack more
electronic functionality and higher speed performance into a smaller volume of
space.
Packaging of ICs is one area that offers attractive benefits for reducing size and
improving performance by either eliminating the package or reducing the size to
the point where it takes up very little more space than the IC.
For many years the electronics industry had been concentrating on increasing
the performance of ICs (more circuitry/silicon area operating at higher speeds)
with little consideration of the fact that ICs in an electronic system must
communicate with each other through the packages that contain them.
As a result of the trend toward higher circuit densities and operating speeds on a
chip, following effects became important considerations for packaging engineers:
I/O requirements increased sharply.
Signal transition time between chips became a factor limiting system
speed.
Signal integrity between silicon chips degraded.
Power requirements per chip increased.
A problem with heat dissipation was created.
All of these factors forced electronic packaging technology into the spotlight,
resulting in a reconsideration of how ICs were being packaged.

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