MSP430 Debugger

TRACE32 Online Help

TRACE32 Directory
TRACE32 Index
TRACE32 Documents ......................................................................................................................

ICD In-Circuit Debugger ................................................................................................................

Processor Architecture Manuals ..............................................................................................

MSP430 .....................................................................................................................................

MSP430 Debugger ................................................................................................................

Brief Overview of Documents for New Users .................................................................

Warning ..............................................................................................................................

General Notes/Target Design Requirements/Recommendations

General ...............................................................................................................................

4
5

Target Design Requirements

Limitations

Contacting Support ...........................................................................................................

Quick Start .........................................................................................................................

Troubleshooting ................................................................................................................

10

Communication between Debugger and Processor can not be established

10

FAQ .....................................................................................................................................

11

MSP430 Specific Implementations ..................................................................................

13

Breakpoints

13

Software Breakpoints

13

On-chip Breakpoints

13

Breakpoints on Data Addresses and Data Values

14

Breakpoints on Registers

14

Breakpoints on Interrupts

14

Example for Standard Breakpoints

15

Cycle Counter

16

Runtime Measurement

16

Memory Classes

17

State Storage

17

Trigger Sequencer

17

General SYStem Commands ............................................................................................

SYStem.state

Display SYStem.state window

1989-2016 Lauterbach GmbH

MSP430 Debugger

18
18

SYStem.BdmClock

Define JTAG frequency

SYStem.CONFIG

18

Configure debugger according to target topology

19

Select the used CPU

20

Run-time CPU access (intrusive)

20

Set jtag clock frequency

21

SYStem.CPU
SYStem.CpuAccess
SYStem.JtagClock
SYStem.LOCK

Lock and tristate the debug port

21

Run-time memory access

22

Establish the communication with the target

23

Configure debugger behavior

24

Disable interrupts for assembler single steps

24

Disable interrupts for HLL single steps

24

SYStem.Option LPMX5

Enable LPMx5 support

24

SYStem.Option TURBO

Speed up memory access

25

Configure clock output pins

25

MSP430 Specific TrOnchip Commands ..........................................................................

26

SYStem.MemAccess
SYStem.Mode
SYStem.Option
SYStem.Option IMASKASM
SYStem.Option IMASKHLL

SYStem.Option TCKTOTEST

TrOnchip.CONVert

Extend the breakpoint range

26

Reset on-chip trigger settings

26

Display on-chip trigger window

26

Low Power Mode debugging ............................................................................................

27

TrOnchip.RESet
TrOnchip.view

Avoid loss of device

27

Supported Low Power Modes

27

Debug Connection ............................................................................................................

29

Support ...............................................................................................................................

30

Available Tools

30

Compilers

41

Realtime Operation Systems

41

3rd Party Tool Integrations

42

Products .............................................................................................................................

42

Product Information

43

Order Information

44

1989-2016 Lauterbach GmbH

MSP430 Debugger

MSP430 Debugger
Version 24-May-2016

Brief Overview of Documents for New Users

Architecture-independent information:

Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.

T32Start (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances

for different configurations of the debugger. T32Start is only available for Windows.

General Commands (general_ref_<x>.pdf): Alphabetic list of debug commands.

Architecture-specific information:

Processor Architecture Manuals: These manuals describe commands that are specific for the
processor architecture supported by your debug cable. To access the manual for your processor
architecture, proceed as follows:
-

Choose Help menu > Processor Architecture Manual.

RTOS Debugger (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware
debugging.

1989-2016 Lauterbach GmbH

MSP430 Debugger

Brief Overview of Documents for New Users

Warning

NOTE:

To prevent debugger and target from damage it is recommended to connect or

disconnect the debug cable only while the target power is OFF.
Recommendation for the software start:
1.

Disconnect the debug cable from the target while the target power is
off.

2.

Connect the host system, the TRACE32 hardware and the debug
cable.

3.

Power ON the TRACE32 hardware.

4.

Start the TRACE32 software to load the debugger firmware.

5.

Connect the debug cable to the target.

6.

Switch the target power ON.

7.

Configure your debugger e.g. via a start-up script.

Power down:
1.

Switch off the target power.

2.

Disconnect the debug cable from the target.

3.

Close the TRACE32 software.

4.

Power OFF the TRACE32 hardware.

General Notes/Target Design Requirements/Recommendations

Before starting please be sure to have up to date debugger software by getting an update from the
LAUTERBACH website. Note that the downloads on the website are stable releases but not necessarily the
latest versions. Therefore in case of problems please contact LAUTERBACH support at [email protected]

1989-2016 Lauterbach GmbH

MSP430 Debugger

Warning

General

The Lauterbach TRACE32 debugger for MSP430 is a on-chip debugging tool (OCD). It uses the
debug function implemented in the target CPU.

Available debug interfaces are the 4-wire JTAG interface or the Spy-Bi-Wire interface.

The debugging support does also include CC430 devices.

Target Design Requirements

Locate the debug connector as close as possible to the processor to minimize the capacitive
influence and cross coupling of noise onto the signals.

Reduce the cable length between CPU and Lauterbach connector to a minimum. Best results will
be provided, if a adequate connector will be foreseen directly on the target board.

The TEST pin of the MSP430 must be connected to the debugger if available. See Debug
Connection (debugger_msp430.pdf) on page 29 for connection information.

Limitations

The debugger offers no target power supply.

Locking the JTAG interface is currently not supported.

Multicore debugging is currently not supported. Please contact technical support if you intend to
debug multicore setups.

1989-2016 Lauterbach GmbH

MSP430 Debugger

General

Contacting Support
LAUTERBACH GmbH
Altlaufstrasse 40
85635 Hoehenkirchen-Siegertsbrunn
Germany
Phone

(+49) 8102-9876-555

Fax

(+49) 8102-9876-187

Internet

http://www.lauterbach.com/tsupport.html or http://www.lauterbach.com/report.html
Here youll find local and special support addresses.

E-mail

[email protected]
General support address where your request will be answered within a short time if it is
a basic support request or redirected to the appropriate address.

Be sure to include detailed system information about your TRACE32 configuration.

1.

To generate a system information report, choose TRACE32 > Help > Support > Systeminfo.

NOTE:

Please help to speed up processing of your support request. By filling out the
system information form completely and with correct data, you minimize the
number of additional questions and clarification request e-mails we need to
resolve your problem.

2.

Preferred: click Save to File, and send the system information as an attachment to your e-mail.

3.

Click Save to Clipboard, and then paste the system information into your e-mail.
1989-2016 Lauterbach GmbH

MSP430 Debugger

Contacting Support

Quick Start
Starting up the debugger is done by the following steps:
1.

Select the device prompt B: for the TRACE32 ICD-Debugger, if the device prompt is not active
after starting the TRACE32 software.
b::

The device prompt B:: is normally already selected in the command line. If this is not the case enter
B: to set the correct device prompt. A RESet command is useful if you do not start directly after
booting the TRACE32 development tool.
2.

Select the CPU derivative to load the specific settings.

SYStem.CPU <cputype>

The default value for SYStem.CPU is MSP430, which is a derivative that does not exist. You should
always select an appropriate device. Otherwise the debug connection to the target might fail. The
default values of all other SYStem options are set in such a way that it should be possible to work
without modification. Please consider that this is probably not the best configuration for your target.
3.

Enter debug mode.

SYStem.Mode Up

4.

Declare size and type of FLASH memory is recommended doing via script.
DO ~~/demo/msp430/flash/msp430f*.cmm

Select the adequate PRACTICE script for the connected target. It will setup the flash memory to allow
writing and setting of software-breakpoints. A number of demo *.cmm scripts for flash progamming is
included in your MSP430 installation demo directory.
You can load a program into flash (if this was not already done by the demo script) as follows:
5.

Load the program.

Data.LOAD.auto ~~/demo/hardware/msp_exp430fg5438/sieve.d43

This example loads a sieve demo for the MSP430F5438 evaluation board. Data.Load.AUTO detects
automatically the correct format. Refer to Supported Compilers to see if your compiler is supported
or not. The option auto is not mandatory an could be left aside. Loading an application to flash
memory is only possible if the flash is declared correctly and unlocked. Please refer to the flash demo
scripts if you need an example for this.
A detailed description of the Data.LOAD command and all available options is given in theGeneral
Reference Guide.
1989-2016 Lauterbach GmbH

MSP430 Debugger

Quick Start

A typical start sequence is shown below. This sequence can be written to an ASCII file (script file) and
executed with the command DO <filename>.
B::

; Select the ICD-Debugger device prompt

RESet

; Reset TRACE32 Software (not target!)

WinCLEAR

; Clear all windows

SYStem.CPU MSP430F5438

; Select the CPU derivative type

SYStem.Up

; Reset the target and enter debug mode

DO ~~/demo/msp430/flash/
msp430f5xx.cmm

; Start flash programming and load the

; application

Register.Set PC main

; Set the PC to function main

Register.view /SpotLight

; Open register window *)

Data.List

; Open source code window *)

Frame.view /Locals /Caller

; Open the stack frame with

; local variables *)

Var.Watch %Spotlight flags ast

; Open watch window for variables *)

PER.view

; Open a window for the special

; function registers and peripherals *)
; Appropriate cpu must be selected!

*) These commands open windows on the screen. The window position can be specified with the WinPOS
command.

1989-2016 Lauterbach GmbH

MSP430 Debugger

Quick Start

Having executed this script your debug session might look like this:
Data.List

PER.view

Register.view

Var.Watch

Frame.view

Command line

1989-2016 Lauterbach GmbH

MSP430 Debugger

Quick Start

Troubleshooting

Communication between Debugger and Processor can not be established

Typically the SYStem.Up command is the first command of a debug session where communication with the
target is required. If you receive error messages like debug port fail or debug port time out while executing
this command this may have the reasons below. target processor in reset is just a follow-up error message.
Open the AREA window to see all error messages.

The target has no power or the debug cable is not connected to the target. This results in the
error message target power fail.

The target is in an unrecoverable state. Re-power your target and try again.

The default debug clock speed is too fast, especially if the target is connected to the debugger by
a long cable. Reduce the communication speed with SYStem.JtagClock command and optimize
the speed when you got it working.

The CPU has no clock.

The CPU is kept in reset.

Although the debugger takes care of the watchdog you should check if there is a watchdog which
needs to be deactivated.

The target is in low power mode and the JTAG interface is not available.

The target is protected via JTAG fuse / password. In this case it is not possible to establish a
JTAG connection.

In case youve selected Spy-Bi-Wire (SBW) to connect to the target, check if there are capacities
connected to the reset line. In SBW mode the MSP430 shares the data line with the reset line.
Any capacities/loads might act as low-pass that reduces your possible clock speed.

The core is in LPMx.5 (Low power mode with JTAG turned off). The core could not be recovered
via JTAG. Try to connect to your core using the Spy-Bi-Wire (SBW) interface.

1989-2016 Lauterbach GmbH

MSP430 Debugger

10

Troubleshooting

FAQ

Debugging via
VPN

The debugger is accessed via Internet/VPN and the performance is very

slow. What can be done to improve debug performance?
The main cause for bad debug performance via Internet or VPN are low data
throughput and high latency. The ways to improve performance by the debugger
are limited:

in practice scripts, use "SCREEN.OFF" at the beginning of the script and

"SCREEN.ON" at the end. "SCREEN.OFF" will turn off screen updates.
Please note that if your program stops (e.g. on error) without executing
"SCREEN.OFF", some windows will not be updated.

"SYStem.POLLING SLOW" will set a lower frequency for target state

checks (e.g. power, reset, jtag state). It will take longer for the debugger to
recognize that the core stopped on a breakpoint.

"SETUP.URATE 1.s" will set the default update frequency of Data.List/

Data.dump/Variable windows to 1 second (the slowest possible setting).

prevent unneeded memory accesses using "MAP.UPDATEONCE

[address-range]" for RAM and "MAP.CONST [address--range]" for ROM/
FLASH. Address ranged with "MAP.UPDATEONCE" will read the specified
address range only once after the core stopped at a breakpoint or manual
break. "MAP.CONST" will read the specified address range only once per
SYStem.Mode command (e.g. SYStem.Up).

1989-2016 Lauterbach GmbH

MSP430 Debugger

11

FAQ

Setting a
Software
Breakpoint fails

What can be the reasons why setting a software breakpoint fails?

Setting a software breakpoint can fail when the target HW is not able to
implement the wanted breakpoint.
Possible reasons:

The wanted breakpoint needs special features that are only possible to
realize by the trigger unit inside the controller.
Example: Read, write and access (Read/Write) breakpoints ("type" in Break.Set
window). Breakpoints with checking in real-time for data-values ("Data").
Breakpoints with special features ("action") like TriggerTrace, TraceEnable,
TraceOn/TraceOFF.
TRACE32 can not change the memory.
Example: ROM and Flash when no preparation with FLASH.Create,
FLASH.TARGET and FLASH.AUTO was made. All type of memory if the
memory device is missing the necessary control signals like WriteEnable or
settings of registers and SpecialFunctionRegisters (SFR).
Contrary settings in TRACE32.
Like: MAP.BOnchip for this memory range. Break.SELect.<breakpoint-type>
Onchip (HARD is only available for ICE and FIRE).
RTOS and MMU:
If the memory can be changed by Data.Set but the breakpoint doesn't work it
might be a problem of using an MMU on target when setting the breakpoint to a
symbolic address that is different than the writable and intended memory
location.

1989-2016 Lauterbach GmbH

MSP430 Debugger

12

FAQ

MSP430 Specific Implementations

Breakpoints
Two types of breakpoints are available for MSP430 architecture: Software breakpoints (SW-BP) and on-chip
breakpoints (HW-BP).

Software Breakpoints
Software breakpoints are the default breakpoints. To set a software breakpoint, before resuming the CPU,
the debugger replaces the instruction at the breakpoint address with a breakpoint code instruction. SW-BPs
can be used in RAM areas and in FLASH areas if FLASH.AUTO is set properly.
There is no restriction in the number of software breakpoints. But it must be considered that by setting
software breakpoints in flash the flash memory will be changed. Consequently the use of software
breakpoints in flash will reduce the number of program/erase cycles that are left for the flash.
Please note that software breakpoints consume one on-chip breakpoint resource if one or more software
breakpoints are set. This must be taken into account when combining on-chip and software breakpoints.

On-chip Breakpoints
If on-chip breakpoints are set the debugger will configure the integrated debug hardware of the MSP430 for
this purpose. Current available MSP430 devices allow to set 2 to 8 on-chip breakpoints (device dependent).
Breakpoints that are set on code in read only memory must be on-chip breakpoints. With the command
MAP.BOnchip <range> it is possible to declare memory address ranges for use with on-chip breakpoints to
the debugger. The number of onchip breakpoints to be set depends on the complexity of the desired
breakpoint. Complex breakpoints consume more hardware resources than simple ones. Onchip breakpoints
take effect before execution.
The Lauterbach MSP430 debugger allows to use a powerful variety of breakpoints. Available breakpoint
types are also device dependent. It is possible to use the following breakpoints:

Program/Instruction Breakpoints: Break on instruction fetch, either on single address or

address range

Data Breakpoints: Break on data read and/or write on a single address or address range

Memory Breakpoints: Break when a certain program part does a read/write access to a certain
address range.

Register Breakpoint: Break when a certain register is written (if available)

All range breakpoints might be used with the exclude option

You can check your breakpoint setup with the command Break.List.
If no more on-chip breakpoints are available you will get an error message on trying to set a new on-chip
breakpoint. Delete other breakpoints to regain debug resources.
1989-2016 Lauterbach GmbH

MSP430 Debugger

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MSP430 Specific Implementations

Breakpoints on Data Addresses and Data Values

Breakpoints on data addresses are bound to several conditions:
1.

The entity doing the data access (read and/or write) must be the CPU. Any other accesses from
on-chip or off-chip peripherals (DMA etc.) will not be recognized by the data address breakpoints.
If you would like to trigger on other sources, like the DMA, contact technical support.

2.

The data being targeted must be qualified by an address in memory. It is not possible to target
registers (GPRs), peripherals etc.

3.

Per default the break will be done independently of the value (empty DATA field of Break.Set
window).

Breakpoints on Registers
Only a break on a register write action is supported by the MSP430 hardware. Register breakpoints are
not available for all MSP430. Limitations:
1.

Only write actions on registers can be triggered. Other breakpoint options for this type like read
or read/write would cause an error.

2.

When the pc is changed after an instruction execution this will not trigger a break action.

3.

Changes to SR (status register) might not always trigger a break action.

4.

A register breakpoint is automatically combined with a range breakpoint since most variables
mapped to registers are only valid in a certain address range.

Breakpoints on Interrupts
MSP430 devices do not offer a special mechanism to halt the device on an interrupt event. However, you
can set a data read/write breakpoint on the interrupt vector table. Once an interrupt is triggered the cpu will
fetch the address of the interrupt handler from the interrupt vector table. This operation will trigger the read/
write breakpoint and therefore halt the cpu on an interrupt event.
Please refer to your MSP430 specific device documentation for more information on MSP430 interrupts.

1989-2016 Lauterbach GmbH

MSP430 Debugger

14

MSP430 Specific Implementations

Example for Standard Breakpoints

Assume you have a target (MSP430FG4618) with:

Code flash memory from 0x3100--0x19fff

RAM from 0x1100--0x30ff

The following standard breakpoint combinations are possible without activated auto flash mode:
1.

2.

Unlimited breakpoints in RAM and up to eight breakpoints in ROM/FLASH

Break.Set 0x11f0 /Program

; Software breakpoint 1 (RAM)

Break.Set 0x1220 /Program

; Software breakpoint 2 (RAM)

Break.Set ram_addr /Program

; Software breakpoint 3 (RAM)

Break.Set 0x4100 /Program

; On-chip breakpoint (flash)

Unlimited breakpoints in RAM and up to eight breakpoints (BP) on a read or write access and up
to four breakpoints on a read and write access (On single address each). Up to two read/write
range breakpoints.
Break.Set 0x11f0 /Program

; Software breakpoint 1 (RAM)

Break.Set 0x1332 /Write

; On-chip breakpoint

Break.Set 0x1332--0x135E /Write

; On-chip range BP (RAM)

Break.Set 0x1334 /ReadWrite

; On-chip breakpoint (RAM)

Break.Set 0x1334++0x1C /ReadWrite

; On-chip range BP (RAM)

(RAM)

1989-2016 Lauterbach GmbH

MSP430 Debugger

15

MSP430 Specific Implementations

With activated auto flash mode even in code flash memory unlimited breakpoints (BP) are allowed. Like in
RAM complex breakpoints will still need an onchip breakpoint.
3.

4.

Unlimited breakpoints in ROM/FLASH

FLASH.AUTO 0x4000--0x43FF

Allow software breakpoints in

specific Flash area

Break.Set 0x4100 /Program

; Software BP 1 (flash)

Break.Set 0x5320 /Program

; Software BP 2 (flash)

Break.Set flash_addr /Program

; Software BP 3 (flash)

Break.Set 0x4200--0x423f /Program

; On-chip BP (flash)

Breakpoints on registers: It is assumed that variable i is mapped to a register. The variable shall
be part of the Lauterbach sieve demo. sieve\7 is the address where the variable is accessed
within the function.
Var.Break.Set sieve\7 /VarWrite
\main\sieve\i

; register breakpoint on
variable i in sieve demo

Cycle Counter
The Cycle Counter is used to evaluate the number of cycles certain actions take. This could be for example
measuring the number of instruction fetches that occurred.
There is currently no support implemented. Request a software update.

Runtime Measurement
The command RunTime allows run time measurements based on polling the CPU run status by software.
Therefore the result will be about few milliseconds higher than the real value.
The measured value depends on the set JtagClock for the debugger polls the cpu. A higher clock means
faster communication with the target an thus a more accurate measurement.

1989-2016 Lauterbach GmbH

MSP430 Debugger

16

MSP430 Specific Implementations

Memory Classes
Though the MSP430 has a linear memory space, the following specific memory classes are available:
Memory Class

Description

Program Memory

Data Memory

VM

Virtual Memory (memory on the debug system)

Emulation Memory, Pseudo Dual port Access to Memory.

To access a memory class write the class in front of the address. Prepending an E as attribute to the
memory class will make memory accesses possible, even when the target CPU is running. Such an access
must be allowed: See SYStem.MemAccess and SYStem.CpuAccess for more information. Example:
Data.dump E:0x200

; View data while CPU is running

Data.dump D:0x200

; View data memory

Data.dump VM:0x200

; Virtual memory, no target access

Note: Since the address space of the MSP430 is linear and non-overlapping memory class D and P are not
distinguished memory classes and can be left aside.
Note: The MSP430 does not allow to read/write memory during run time. This means that a memory access
using the access class E: is intrusive, i.e. the CPU is continuously stopped and restarted.

State Storage
The State Storage of the MSP430 allows to records the last eight address bus, data bus and status register
values, dependant on the trigger that triggers the state storage.
There is currently no support implemented. Request a software update.

Trigger Sequencer
The trigger sequencer can be used to trigger an action under the condition that a certain programmed
sequence happened.
There is currently no support implemented. Request a software update.

1989-2016 Lauterbach GmbH

MSP430 Debugger

17

MSP430 Specific Implementations

General SYStem Commands

SYStem.state

Format:

Display SYStem.state window

SYStem.state

Opens the SYStem.state window, where you can configure the MSP430 debugger:
SYStem.MemAccess

SYStem.Option
SYStem.Mode

SYStem.JtagClock
SYStem.CPU

SYStem.BdmClock

Define JTAG frequency

Obsolete command syntax. It has the same effect as SYStem.JtagClock. Use SYStem.JtagClock instead.

1989-2016 Lauterbach GmbH

MSP430 Debugger

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General SYStem Commands

SYStem.CONFIG

Configure debugger according to target topology

Format:

SYStem.CONFIG <parameter>

<parameter>:

state
DEBUGPORTTYPE
IRPRE <bits>
IRPOST<bits>
DRPRE <bits>
DRPOST <bits>
TriState [ON | OFF]
Slave [ON | OFF]
TAPState <state>
TCKLevel <level>

The four parameters IRPRE, IRPOST, DRPRE, DRPOST are required to inform the debugger of the TAP
controller position in the JTAG chain if there is more than one core in the JTAG chain. The information is
required before the debugger can be activated, e.g., by a SYStem.Mode.Attach.
TriState has to be used if several debugger are connected to a common JTAG port at the same time.
TAPState and TCKLevel define the TAP state and TCK level which is selected when the debugger switches
to TriState mode. TCK can have a pull-up or pull-down resistor, other trigger inputs needs to be kept in
inactive state.
DEBUGPORTTYPE
[JTAG | SPY-BIWIRE]

Select JTAG or Spy-Bi-Wire (SBW) interface. Only available for devices

with SBW.

state

Not available yet. Contact technical support.

IRPRE

Not available yet. Contact technical support.

IRPOST

Not available yet. Contact technical support.

DRPRE

Not available yet. Contact technical support.

DRPOST

Not available yet. Contact technical support.

TriState [ON | OFF]

Not available yet. Contact technical support.

Slave [ON | OFF]

Not available yet. Contact technical support.

TAPState

Not available yet. Contact technical support.

TCKLevel [0 | 1]

Not available yet. Contact technical support.

1989-2016 Lauterbach GmbH

MSP430 Debugger

19

General SYStem Commands

SYStem.CPU

Select the used CPU

Format:

SYStem.CPU <cpu>

<cpu>:

MSP430xxx | CC430xxx

Select the processor type. See Available Tools for supported processors. (Go to figure.)

SYStem.CpuAccess

Run-time CPU access (intrusive)

Format:

SYStem.CpuAccess <mode>

<mode>:

Enable | Denied | Nonstop

Enable

In order to perform a memory read or write while the CPU is executing

the program the debugger stops the program execution shortly.
Each short stop takes 1 100 ms depending on the speed of the CPU
and debug interface and on the size of the read/write accesses required.

Denied

No intrusive memory access is possible while the CPU executes the

program.

Nonstop

Nonstop ensures that the program execution can not be stopped and that
the debugger does not affect the real-time behavior of the CPU.
The debugger inhibits the following:

to stop the program execution

all features of the debugger that are intrusive (e.g. spot breakpoints, performance analysis via Stop-and-go, conditional breakpoints etc.)

NOTE:

Non-intrusive memory access during runtime is not possible for the MSP430. Use
the Enable option to declare if an intrusive memory access can take place while the
CPU is executing code.

The run-time memory access has to be activated for each window by using the memory class E: or by using
the format option %E .

1989-2016 Lauterbach GmbH

MSP430 Debugger

20

General SYStem Commands

Example:
Data.dump E:0x200

; Intrusive Data.dump at specific location

Data.List E:

; Intrusive Data.List at current program counter

Data.List E:0x3100

; Intrusive Data.List at specific location

Var.View %E first

; Intrusive display of variable first

Please refer to Memory classes for additional information. (Go to figure.)

SYStem.JtagClock

Format:

Set jtag clock frequency

SYStem.JtagClock <frequency>

Selects the JTAG port frequency (TCK) used by the debugger to communicate with the processor. This
influences e.g. the download speed. It could be useful to reduce the JTAG frequency if there are buffers,
additional loads or high capacities on the JTAG lines or if VTREF is very low. A very high frequency will not
work on all systems and will result in an erroneous data transfer.
The debugger cannot select all frequencies accurately. It chooses the next possible frequency and displays
the real value in the System Settings window.
A decimal number like 100000. also short forms like 100kHz or 15MHz can be used for <frequency>.
The short forms implies a decimal value, although no . is used.

SYStem.LOCK

Format:

Lock and tristate the debug port

SYStem.LOCK [ON | OFF]

Default: OFF.
If the system is locked, no access to the debug port will be performed by the debugger. While locked, the
debug connector of the debugger is tristated. The main intention of the lock command is to give debug
access to another tool.
The command has no effect for the simulator.

1989-2016 Lauterbach GmbH

MSP430 Debugger

21

General SYStem Commands

SYStem.MemAccess

Run-time memory access

Format:

SYStem.MemAccess <mode>
SYStem.ACCESS (deprecated)

<mode>:

CPU
Denied

Default: Denied. (Go to figure.)

If SYStem.MemAccess is not Denied, it is possible to read from memory, to write to memory and to set
software breakpoints while the CPU is executing the program. This is only possible for the instruction set
simulator.
CPU

A run-time memory access is made without CPU intervention while the

program is running (Only Simulator).

Denied

No memory access is possible while the CPU is executing the program.

If a specific window that displays memory or variables should be updated while the program is running select
the memory class E: or the format option %E.
Data.dump E:0x200

; Non-Intrusive Data.dump at specific location

Data.List E:

; Non-Intrusive Data.List at program counter

Data.List E:0x3100

; Non-Intrusive Data.List at specific location

Var.View %E first

; Non-Intrusive display of variable first

Please refer to Memory classes for additional information.

1989-2016 Lauterbach GmbH

MSP430 Debugger

22

General SYStem Commands

SYStem.Mode

Establish the communication with the target

Format:

SYStem.Mode <mode>

<mode>:

Down | NoDebug | Go | Attach | Up

Select target reset mode. (Go to figure.)

Down

Disables the debugger (default).

The state of the CPU remains unchanged. The JTAG/SBW port is
tristated.

NoDebug

Disables the debugger.

The state of the CPU remains unchanged. The JTAG/SBW port is
tristated.

Go

Resets the target and enables the debugger and start the program
execution.
Program execution can be stopped by the break command or external
trigger.

Up

Resets the target and sets the CPU to debug mode.

After execution of this command the CPU is stopped and prepared for
debugging. All registers are set to the default level.

Attach

User program remains running and the debug mode is activated.

After this command the user program can be stopped with the break
command or if any break condition occurs.

StandBy

Not available for MSP430.

1989-2016 Lauterbach GmbH

MSP430 Debugger

23

General SYStem Commands

SYStem.Option

Configure debugger behavior

System options allow to influence the behavior of the debugger.

SYStem.Option IMASKASM

Disable interrupts for assembler single steps

Format:

SYStem.Option IMASKASM <option>

<option>:

ON | OFF

Default: OFF
Disable interrupts while single stepping in assembler mode.

SYStem.Option IMASKHLL

Disable interrupts for HLL single steps

Format:

SYStem.Option IMASKHLL <option>

<option>:

ON | OFF

Default: OFF
Disables interrupts while single stepping in HLL mode. A HLL step might execute several lines of code.
Thus a target application might re-enable interrupts again during the step.

SYStem.Option LPMX5

Enable LPMx5 support

Format:

SYStem.Option LPMX5 <option>

<option>:

ON | OFF

Default: OFF
Per default the support of the LPM5 mode is disabled. If enabled, the debugger will check the LPMx.5 state
of a device. This takes additional time and will decrease the debug performance.

1989-2016 Lauterbach GmbH

MSP430 Debugger

24

General SYStem Commands

Only available for MSP430F5xxx, MSP430F6xxx, MSP30FR5xxx, CC4305xxx, CC430F5xxx devices that
support the LPMx.5 mode.

SYStem.Option TURBO

Speed up memory access

Format:

SYStem.Option TURBO <option>

<option>:

ON | OFF

Default: OFF
If activated, additional error checks are avoided. This increases the read and write access to memory. Write
or read errors might not be detected.
Only available for MSP430F5xxx, MSP430F6xxx, MSP30FR5xxx, CC4305xxx, CC430F5xxx devices.

SYStem.Option TCKTOTEST

Configure clock output pins

Format:

SYStem.Option TCKTOTEST<option>

<option>:

NORMAL | BOTHTCK | BOTHTEST | SWAP

Select output pin for debug clock. This option applies only for a Spy-Bi-Wire connection. It makes no
sense to use this with 4-wire JTAG.
NORMAL

Clock is only output on TCK pin

BOTHTCK

Clock is output on TCK and TEST pin

BOTHTEST

Test is output on TCK and TEST pin

SWAP

Clock is only output on TEST pin

1989-2016 Lauterbach GmbH

MSP430 Debugger

25

General SYStem Commands

MSP430 Specific TrOnchip Commands

The TrOnchip command provides low level access to the on-chip debug register.

TrOnchip.CONVert

Format:

Extend the breakpoint range

TrOnchip.CONVert [ON | OFF]

Default: ON.
The debug unit of some devices does not provide the resources to set an on-chip breakpoint to an address
range. Instead only bit masks can be used to mark a memory range with a breakpoint. A mask has a
reduced flexibility and cannot handle all ranges. It is therefore required to adapt the address range the user
has entered so that it fits to the debug unit capabilities.
If TrOnchip.Convert is set to ON (default) and a breakpoint is set to a range, this range is extended to the
next possible bit mask. The result is, that in most cases a bigger address range is marked by the specified
breakpoint. This can be easily controlled by the Data.View command.
If TrOnchip.Convert is set to OFF, the debugger will only accept breakpoints which exactly fit to the on-chip
breakpoint hardware.
This setting affects all on-chip breakpoints.

TrOnchip.RESet

Format:

Reset on-chip trigger settings

TrOnchip.RESet

Resets all TrOnchip settings.

TrOnchip.view

Format:

Display on-chip trigger window

TrOnchip.view

Open TrOnchip window.

1989-2016 Lauterbach GmbH

MSP430 Debugger

26

MSP430 Specific TrOnchip Commands

Low Power Mode debugging

MSP430 devices offer different low power modes. Low Power modes are designed to save energy. This is
done by disabling certain clocks, the CPU itself and the JTAG connection. Which parts are deactivated
depends on the Low Power Mode and the device. Details can be found in the device specific data sheet.

Avoid loss of device

Devices that implement the LPMx.5 mode (i.e. LPM3.5 and/or LPM4.5) may disable JTAG in LPMx.5 mode.
In this case the debugger has no access to the device until the next wake-up which cannot be done by the
debugger. If the JTAG is kept alive during LPMx.5 the debugger may snoop the LPMx.5 state of the device
and wake the device into debug mode. Hence the debugger might not be able to recover a device that goes
to LPMx.5 shortly after the device went out from reset. This happens when JTAG is powered down to fast.
Development recommendation:

Add a wait time of 5 to 10 seconds in the LPMx.5 application before entering LPMx.5. The
debugger has then a chance to bring the device to debug mode before LPMx.5 is entered.

Check then if device can be recovered from LPMx.5. Remove wait time once the development of
the LPMx.5 application has finished or if the device can be recovered by the debugger.

Supported Low Power Modes

LPM0 - LPM4

All MSP430 derivatives

LPMx.5

MSP430F5xxx, MSP430FR5xxx, MSP430F6xxx, CC430F5xxx, CC430F6xx.

Some of these devices may not support LPMx.5. Refer to device data sheet.

The current low power mode of the device is indicated on the at the right bottom of TRACE32:

1989-2016 Lauterbach GmbH

MSP430 Debugger

27

Low Power Mode debugging

The following state information can be displayed

running

Core is active an running. Core power is up. All clocks are active.

running
(lpm0)

Core is in lpm0. Core power is up. CPU and some clocks are disabled.

running
(lpm1)

Core is in lpm1. Core power is up. CPU and some clocks are disabled.

running
(lpm2)

Core is in lpm2. Core power is up. CPU and some clocks are disabled.

running
(lpm3)

Core is in lpm3. Core power is up. CPU and some clocks are disabled.

running
(lpm4)

Core is in lpm4. Core power is up. CPU and all clocks are disabled.

running
(lpmx.5)

Core is in lpm3.5 or lpm4.5. Core power is down, JTAG is not accessible.

running
(lpm3.5)

Core is in lpm3.5. Core power is down and JTAG is accessible

running
(lpm4.5)

Core is in lpm4.5. Core power is down and JTAG is accessible

Please refer to your device specific data sheet for detailed information on supported low power modes.

1989-2016 Lauterbach GmbH

MSP430 Debugger

28

Low Power Mode debugging

Debug Connection
Pinout of the 14-pin Debug Cable:
Signal
TDO|SBWTDIO RST
TDI TCLK
TMS
TCK|TEST SBWTCK
GND
RST
N/C

Pin
1
3
5
7
9
11
13

Pin
2
4
6
8
10
12
14

Signal
N/C
VTREF
N/C
TEST
N/C
N/C
NC

For details on logical functionality, physical connector, alternative connectors, electrical characteristics,
timing behavior and printing circuit design hints, refer to the application note JTAG Interface Specification.
In case of problems contact support at [email protected].

1989-2016 Lauterbach GmbH

MSP430 Debugger

29

Debug Connection

Support

CC430F5123
CC430F5125
CC430F5133
CC430F5135
CC430F5137
CC430F5143
CC430F5145
CC430F5147
CC430F6125
CC430F6126
CC430F6127
CC430F6135
CC430F6137
CC430F6143
CC430F6145
CC430F6147
MSP430AFE221
MSP430AFE222
MSP430AFE223
MSP430AFE231
MSP430AFE232
MSP430AFE233
MSP430AFE251
MSP430AFE252
MSP430AFE253
MSP430AFE4110
MSP430BT5190
MSP430C091
MSP430C092
MSP430C1101
MSP430C1111
MSP430C1121
MSP430C1331
MSP430C1351

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU

Available Tools

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

MSP430 Debugger

30

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
MSP430C311
MSP430C312
MSP430C313
MSP430C314
MSP430C315
MSP430C323
MSP430C325
MSP430C336
MSP430C337
MSP430C412
MSP430C413
MSP430CG4616
MSP430CG4617
MSP430CG4618
MSP430CG4619
MSP430F110
MSP430F1101
MSP430F1101A
MSP430F1111A
MSP430F112
MSP430F1121
MSP430F1121A
MSP430F1122
MSP430F1132
MSP430F122
MSP430F1222
MSP430F123
MSP430F1232
MSP430F133
MSP430F135
MSP430F147
MSP430F1471
MSP430F148
MSP430F1481
MSP430F149
MSP430F1491
MSP430F155
MSP430F156
MSP430F157
MSP430F1610
MSP430F1611

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

MSP430 Debugger

31

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
MSP430F1612
MSP430F167
MSP430F168
MSP430F169
MSP430F2001
MSP430F2002
MSP430F2003
MSP430F2011
MSP430F2012
MSP430F2013
MSP430F2013-EP
MSP430F2101
MSP430F2111
MSP430F2112
MSP430F2121
MSP430F2122
MSP430F2131
MSP430F2132
MSP430F2232
MSP430F2234
MSP430F2252
MSP430F2254
MSP430F2272
MSP430F2274
MSP430F2274-EP
MSP430F233
MSP430F2330
MSP430F235
MSP430F2350
MSP430F2370
MSP430F2410
MSP430F2416
MSP430F2417
MSP430F2418
MSP430F2419
MSP430F247
MSP430F2471
MSP430F248
MSP430F2481
MSP430F249
MSP430F249-EP

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

MSP430 Debugger

32

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
MSP430F2491
MSP430F2616
MSP430F2617
MSP430F2618
MSP430F2618-EP
MSP430F2619
MSP430F2619-SHT
MSP430F412
MSP430F413
MSP430F4132
MSP430F415
MSP430F4152
MSP430F417
MSP430F423
MSP430F423A
MSP430F425
MSP430F4250
MSP430F425A
MSP430F4260
MSP430F427
MSP430F4270
MSP430F427A
MSP430F435
MSP430F4351
MSP430F436
MSP430F4361
MSP430F437
MSP430F4371
MSP430F438
MSP430F439
MSP430F447
MSP430F448
MSP430F4481
MSP430F449
MSP430F4491
MSP430F4616
MSP430F46161
MSP430F4617
MSP430F46171
MSP430F4618
MSP430F46181

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

MSP430 Debugger

33

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
MSP430F4619
MSP430F46191
MSP430F47126
MSP430F47127
MSP430F47163
MSP430F47166
MSP430F47167
MSP430F47173
MSP430F47176
MSP430F47177
MSP430F47183
MSP430F47186
MSP430F47187
MSP430F47193
MSP430F47196
MSP430F47197
MSP430F477
MSP430F478
MSP430F4783
MSP430F4784
MSP430F479
MSP430F4793
MSP430F4794
MSP430F5131
MSP430F5132
MSP430F5151
MSP430F5152
MSP430F5171
MSP430F5172
MSP430F5212
MSP430F5214
MSP430F5217
MSP430F5219
MSP430F5222
MSP430F5224
MSP430F5227
MSP430F5229
MSP430F5232
MSP430F5234
MSP430F5237
MSP430F5239

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

MSP430 Debugger

34

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
MSP430F5242
MSP430F5244
MSP430F5247
MSP430F5249
MSP430F5252
MSP430F5253
MSP430F5254
MSP430F5255
MSP430F5256
MSP430F5257
MSP430F5258
MSP430F5259
MSP430F5304
MSP430F5308
MSP430F5309
MSP430F5310
MSP430F5324
MSP430F5325
MSP430F5326
MSP430F5327
MSP430F5328
MSP430F5329
MSP430F5333
MSP430F5335
MSP430F5336
MSP430F5338
MSP430F5340
MSP430F5341
MSP430F5342
MSP430F5358
MSP430F5359
MSP430F5418
MSP430F5418A
MSP430F5419
MSP430F5419A
MSP430F5435
MSP430F5435A
MSP430F5436
MSP430F5436A
MSP430F5437
MSP430F5437A

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

MSP430 Debugger

35

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
MSP430F5438
MSP430F5438A
MSP430F5500
MSP430F5501
MSP430F5502
MSP430F5503
MSP430F5504
MSP430F5505
MSP430F5506
MSP430F5507
MSP430F5508
MSP430F5509
MSP430F5510
MSP430F5513
MSP430F5514
MSP430F5515
MSP430F5517
MSP430F5519
MSP430F5521
MSP430F5522
MSP430F5524
MSP430F5525
MSP430F5526
MSP430F5527
MSP430F5528
MSP430F5529
MSP430F5630
MSP430F5631
MSP430F5632
MSP430F5633
MSP430F5634
MSP430F5635
MSP430F5636
MSP430F5637
MSP430F5638
MSP430F5658
MSP430F5659
MSP430F6433
MSP430F6434
MSP430F6435
MSP430F6436

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

MSP430 Debugger

36

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
MSP430F6438
MSP430F6458
MSP430F6459
MSP430F6630
MSP430F6631
MSP430F6632
MSP430F6633
MSP430F6634
MSP430F6635
MSP430F6636
MSP430F6637
MSP430F6638
MSP430F6658
MSP430F6659
MSP430F6720
MSP430F6721
MSP430F6723
MSP430F6724
MSP430F6725
MSP430F6726
MSP430F6730
MSP430F6731
MSP430F6733
MSP430F6734
MSP430F6735
MSP430F6736
MSP430F6745
MSP430F67451
MSP430F6746
MSP430F67461
MSP430F6747
MSP430F67471
MSP430F6748
MSP430F67481
MSP430F6749
MSP430F67491
MSP430F6765
MSP430F67651
MSP430F6766
MSP430F67661
MSP430F6767

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

MSP430 Debugger

37

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
MSP430F67671
MSP430F6768
MSP430F67681
MSP430F6769
MSP430F67691
MSP430F6775
MSP430F67751
MSP430F6776
MSP430F67761
MSP430F6777
MSP430F67771
MSP430F6778
MSP430F67781
MSP430F6779
MSP430F67791
MSP430FE423
MSP430FE4232
MSP430FE423A
MSP430FE4242
MSP430FE425
MSP430FE4252
MSP430FE425A
MSP430FE427
MSP430FE4272
MSP430FE427A
MSP430FG4250
MSP430FG4260
MSP430FG4270
MSP430FG437
MSP430FG438
MSP430FG439
MSP430FG4616
MSP430FG4617
MSP430FG4618
MSP430FG4619
MSP430FG477
MSP430FG478
MSP430FG479
MSP430FR5720
MSP430FR5721
MSP430FR5722

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

MSP430 Debugger

38

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
MSP430FR5723
MSP430FR5724
MSP430FR5725
MSP430FR5726
MSP430FR5727
MSP430FR5728
MSP430FR5729
MSP430FR5730
MSP430FR5731
MSP430FR5732
MSP430FR5733
MSP430FR5734
MSP430FR5735
MSP430FR5736
MSP430FR5737
MSP430FR5738
MSP430FR5739
MSP430FR5969
MSP430FW423
MSP430FW425
MSP430FW427
MSP430FW428
MSP430FW429
MSP430G2001
MSP430G2101
MSP430G2102
MSP430G2111
MSP430G2112
MSP430G2121
MSP430G2131
MSP430G2132
MSP430G2152
MSP430G2153
MSP430G2201
MSP430G2202
MSP430G2203
MSP430G2210
MSP430G2211
MSP430G2212
MSP430G2213
MSP430G2221

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

MSP430 Debugger

39

Support

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU
MSP430G2230
MSP430G2230-EP
MSP430G2231
MSP430G2231-EP
MSP430G2232
MSP430G2233
MSP430G2252
MSP430G2253
MSP430G2302
MSP430G2302-EP
MSP430G2303
MSP430G2312
MSP430G2313
MSP430G2332
MSP430G2332-EP
MSP430G2333
MSP430G2352
MSP430G2353
MSP430G2402
MSP430G2403
MSP430G2412
MSP430G2413
MSP430G2432
MSP430G2433
MSP430G2444
MSP430G2452
MSP430G2453
MSP430G2513
MSP430G2533
MSP430G2544
MSP430G2553
MSP430G2744
MSP430G2755
MSP430G2855
MSP430G2955
MSP430L092

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

1989-2016 Lauterbach GmbH

MSP430 Debugger

40

Support

Compilers
Language

Compiler

MSPGCC

C
C/C++

CCS
ICC430

Company

Texas Instruments
IAR Systems AB

Option

Comment

ELF

Gnu Compiler for

MSP430

COFF
D43/uBROF

Realtime Operation Systems

No operation systems supported.

1989-2016 Lauterbach GmbH

MSP430 Debugger

41

Support

3rd Party Tool Integrations

CPU

Tool

Company

ALL
ALL
ALL

ADENEO
X-TOOLS / X32
CODEWRIGHT

ALL

CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER

Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd

ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL

ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL

ATTOL TOOLS
VISUAL BASIC
INTERFACE
LABVIEW

CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER

Host
Windows
Windows
Windows

Code Confidence Ltd

Linux

EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation

Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows

NATIONAL
INSTRUMENTS
Corporation
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software

Windows

Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows

Vector Software

Windows

Windows

Windows

Products

1989-2016 Lauterbach GmbH

MSP430 Debugger

42

Products

Product Information
OrderNo Code

Text

LA-3713

JTAG Debugger for MSP430 (ICD)

JTAG-MSP430

supports MSP430 via JTAG or Spy-Bi-Wire

includes software for Windows, Linux and MacOSX
requires Power Debug Module
debug cable with 14 pin connector

1989-2016 Lauterbach GmbH

MSP430 Debugger

43

Products

Order Information
Order No.

Code

Text

LA-3713

JTAG-MSP430

JTAG Debugger for MSP430 (ICD)

1989-2016 Lauterbach GmbH

MSP430 Debugger

44

Products