Scribd
Upload
82 views

Memory Decode Test

The document discusses address decoding for connecting memory and peripherals to a microprocessor bus. It provides examples of how to determine the number of address lines needed and how to decode additional lines to selectively activate chips using a chip select pin. In the first example, it shows decoding one address line to connect a 32k RAM chip to a microprocessor with 20 address lines. In the second example, it adds a 32k program memory chip and shows determining the address ranges to avoid conflicts.

Uploaded by

kewancam
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
82 views

Memory Decode Test

The document discusses address decoding for connecting memory and peripherals to a microprocessor bus. It provides examples of how to determine the number of address lines needed and how to decode additional lines to selectively activate chips using a chip select pin. In the first example, it shows decoding one address line to connect a 32k RAM chip to a microprocessor with 20 address lines. In the second example, it adds a 32k program memory chip and shows determining the address ranges to avoid conflicts.

Uploaded by

kewancam
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 12

ECE3073

Address Decoding

A Few Questions
Some important basic
information

1) Each component on the bus has to have a unique address.

2) The number of address lines determines our availible


address space and hence the size of the memory we may
use etc.

3) You have to use some of the address lines as decoders


(Signals to turn on or off the components on the bus)

4) Most components use a pin called the chip select and it


is active low by convention. 0V or logic (0) turns the chip
on

5) For these example questions, try and use the upper most
address lines first
Example 1
Using an 8 bit microprocessor which has 20 address lines we
wish to implement a 32k RAM chip.

CS active low

CPU RAM
32K
20 address lines A0 A19
Determine number of address lines to RAM:

CS active low

20 address lines A0 A19


For 32k how many address lines do we need?
CPU RAM
Write it here.
32K
Determine number of free address lines to use as decoders:
How many address lines are free?
Draw how you would decode it

CS active low

CPU RAM
32K
Determine address range:

CS active low

CPU RAM
32K

fffff

BINARY. (Every bit represents one HEX


address line)
A19 A15 A11 A7 A3
A16 A12 A8 A4 A0

End address

Base
address

What is the start address of RAM in HEX ?


What is the end address of RAM HEX ?

CS active low

16 address lines A0 A16 RAM


CPU
For 16k we need 14 address line A0 A13 16K
Example 2
Using an 8 bit microprocessor which has 20 address lines we
wish to implement a 64k RAM chip and 32K program memory
chip

CS active low

CPU RAM
64K

CS active low

PM
32K
Determine number of address lines to RAM and PM:

How many address lines do we need to use for RAM ?


How many address lines do we need to use for PM ? CS active low
How many lines are left over?

How many do we have left over


CPU RAM
64K

CS active low

PM
32K

Determine number of free address lines to use as decoders:


What are they?
Design decode logic?

CS active low

CPU RAM
64K

CS active low

PM
32K

Determine address range:


CS active low

CPU RAM
64K

CS active low

PM
32K

BINARY. (Every bit represents one HEX


address line)
A19 A15 A11 A7 A3
A16 A12 A8 A4 A0
PM
End address

Base
address
RAM
End address

Base
address
Potential problem
Are there any problems in your circuit?

CS active low

CPU RAM
64K

CS active low

PM
32K

BINARY. (Every bit represents one HEX


address line)
A19 A15 A11 A7 A3
A16 A12 A8 A4 A0
PM
End address

Base
address
RAM
End address

Base
address
Potential solution

CS active low

CPU RAM
64K

CS active low

PM
32K

BINARY. (Every bit represents one HEX


address line)
A19 A15 A11 A7 A3
A16 A12 A8 A4 A0
PM
End address

Base
address
RAM
End address

Base
address

You might also like