Scribd
Upload
159 views2 pages

ECE3073 Computer Systems Practice Questions Bus Interfacing

This document contains three practice questions about bus interfacing in computer systems: 1) The minimum number of address lines required to address various memory and I/O devices. 2) How to connect a 16-bit address bus to a 74LS138 decoder chip to provide 8 chip selects for 8 memory chips within specific address ranges. 3) The sequence of signals that appear on the data, address and control busses when a microprocessor outputs data via a parallel I/O circuit, and how this results in a change of the digital output.

Uploaded by

kewancam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
159 views2 pages

ECE3073 Computer Systems Practice Questions Bus Interfacing

This document contains three practice questions about bus interfacing in computer systems: 1) The minimum number of address lines required to address various memory and I/O devices. 2) How to connect a 16-bit address bus to a 74LS138 decoder chip to provide 8 chip selects for 8 memory chips within specific address ranges. 3) The sequence of signals that appear on the data, address and control busses when a microprocessor outputs data via a parallel I/O circuit, and how this results in a change of the digital output.

Uploaded by

kewancam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

ECE3073 Computer Systems

Practice Questions

Bus Interfacing

i) What is the minimum number of address lines required to address the


following items is a byte-wide memory map?
a) 1024 kbytes of RAM
b) 3 by 16bit input devices
c) 512 kbytes of ROM
d) 1024 LEDs organised in groups of 8

ii) A 74LS138 decoder is to provide the chip select signals for eight memory chips.
Draw a diagram of the connections (using a minimum of additional logic functions)
between a 16-bit address bus and the decoder chip to provide 8 chip selects with the
following address ranges:

74LS138 output Address range

0 C100 - C1FF
1 C500 - C5FF
2 C900 - C9FF
3 CD00 - CDFF
4 D100 - D1FF
5 D500 - D5FF
6 D900 - D9FF
7 DD00 - DDFF

Truthtable for 74LS138 decoder Decoder chip logic symbol.


iii) When a microprocessor system outputs parallel digital data via a PIO (Parallel
Input/Output) circuit this causes a sequence of signals to appear on the system data,
address and control busses. Briefly describe these signals and explain how they
result in a change in the digital output of the PIO.
RAR 03/03/2013

You might also like