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Convolution Encoder Verilog Code

This document contains code for a convolutional encoder module and test bench. The convolutional encoder module takes an input bit (x), clock (clk), and reset and outputs the current state and encoded bits. It uses the current and previous input bits to calculate the encoded output bits through an XOR operation. The test bench instantiates the encoder module and provides it with a sample input data pattern over multiple clock cycles to test the encoding functionality.

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Mounesh Panchal
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© © All Rights Reserved
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Download as TXT, PDF, TXT or read online on Scribd
3K views

Convolution Encoder Verilog Code

This document contains code for a convolutional encoder module and test bench. The convolutional encoder module takes an input bit (x), clock (clk), and reset and outputs the current state and encoded bits. It uses the current and previous input bits to calculate the encoded output bits through an XOR operation. The test bench instantiates the encoder module and provides it with a sample input data pattern over multiple clock cycles to test the encoding functionality.

Uploaded by

Mounesh Panchal
Copyright
© © All Rights Reserved
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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////Convolution Encoder/////

module conv_encoder(x,clk,reset,state,en_output);
input x;
input clk;
input reset;
integer i=1;
//output i;
//reg i;
output [1:0] state;
output [1:0] en_output;
//output [i:0] en_out;
//reg din;
reg [1:18] en_out;
reg [1:0] state;
reg [1:0] en_output;
reg [1:8] data=8'b11010110;
//reg [i:0] en_out;
//
//initial
//begin
//if (reset==1'b1)
//begin
//din=0;
//state[1]=1'b0;
//state[0]=1'b0;
//en_output[1]=1'b0;
//en_output[0]=1'b0;
//$display("%b\t %b\t",state,en_output);
//end
//else
//begin
always @ ( posedge clk)
begin
//always @(posedge clk)
if (reset==1'b1)
begin
//din=0;
state[1]=1'b0;
state[0]=1'b0;
en_output[1]=1'b0;
en_output[0]=1'b0;
//$display("%b\t %b\t %b\n",din,state,en_output);
end
else
begin

//din<=x;
state[0]<=state[1];
state[1]<=x;

//$display("%b\t %b\n",din,x);

en_output[1]<=x ^ state[0];
en_output[0]<=x ^ state[1] ^ state[0];
en_out[i]<=en_output[1];
en_out[i+1]<=en_output[0];
i=i+2;
$display("message bits are %b\n",data);
$display("encoded output is %b\n",en_out);
//$display("%b\t %b\n",x,en_output);
end

//$display("%b\t %b\t %b\n",din,en_output,state);


end

endmodule

////Convolution Encoder_Test Bench/////


module conv_encoder_tb;
// Inputs
reg x;
reg clk;
reg reset;
reg [1:8] data;
integer I;
// Outputs
//wire din;
wire [1:0] state;
wire [1:0] en_output;
// Instantiate the Unit Under Test (UUT)
conv_encoder uut (
.x(x),
.clk(clk),
.reset(reset),
.state(state),
.en_output(en_output)
);
initial begin
// Initialize Inputs
x=0;
clk=0;
//reset=0;
I<=1;
data=8'b1101_0110;

forever #10 clk=~clk;

end
initial begin
//#5 x=0;
#10 reset=1;
#10 reset=0;
end

always @( posedge clk)


begin
if(I>11)
begin
$display("%b",en_output);
$finish;
end
else
begin

x<= data[I];
I<=I+1;
//$display("%d\t %d\t %d\n",x,I,data[I]);
end

end

//always #5 clk=~clk;
endmodule

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