Learning objectives By the end ofthis chapter you should be able t. show understanding of interrupt handling on CiChapter 19: Processor and Computer Architecture 19.01 The control unit While a program is being executed, the CPU is receiving a sequence of machine-code Instructions. its the responsibility of the cantral unit within the CPU to ensure that each ‘machine instruction is handled correctly, There are two ways that a control unit can be designed to alow itto perform its function. (One method is for the control unit to be constructed as alogic circuit. Tisis called the hard: Wired solution. The machine-code instructions are handled directly by hardware The alternatives for the control unit to use microprogramming. In this approach, the control Unit contains a ROM component in which is stored the microinstructions or microcode for ' rmicroprogramming, This is ten referred to as firmware, The choice of which method is used is largely dependent on the type of processor. 19.02 CISC and RISC processors The ‘architecture’ ofa processor can be defined in 2 number of ways, From the point of view ofa sophisticated programmer, the architecture involves the folowing: + theinstruction set + theinstruction format + theaddressing modes t + the registers accessible by instructions. The choice ofthe instruction sets the main factor in deciding on a suitable architecture. BE One view is that the instruction set should be chosen so thattcan be clearly applied to important problems, that only simple equipment is required and that important problems are handled speedily. An opposing view is that should be chosen to suit the needs ofhigh- level languages. Early devel ts iting led Hes aa arly developments in computing tothe tte ombecomingdomnent, | Fewet instructions More instructions Computersystems contained what _|Simplerinstructions More complexinstructions would now be refered to as CISC Small number finstucton formats_| Many instrution formats (Complexinstruction Set Computers) __[Single-cycle instructions whenever processors with the complexity ite Multi-cycle instructions pny ark ower Fixe-length instructions Varabe-ength instructions Sere prety cee, Inly load and store instructions to —_| Many types of instructions to address Degantobechalengadinthelae _ [ORYleadandstoreinsuctonsto | Many yp 1070s. twas argued that RISC (Reduced om : Instruction Set Computers| wouldbea | Fewer aderessing modes More eddresing modes better approach. Table 12.0 containsa_ | Muliple register sets Fewer egters umber of features that distinguish RISC [ard-wired contol unit icroprogrammed control unit fence Pipelining easier Pipelining more difficult Itcan be seen that reduced’ affects ‘more than just the number of instructions. The simplicity ofthe instructions allows data to be stored in registers and ‘manipulated in therm with na resource to memory access other than that necessary for initial loading and possible final storing. The simplicity also allows hard-wiringinside the control unit with limited complexity required, Table 18.01 Comparison of RISC with CISCIncontrast, the specialised instructions that can be part of a CISC architecture often require repeated memory access, The complexity of some of the instructions makes hard-wirin extremely difficult so microprogramming is the norm. However, the increased complexi of instructions for CISC is oten because they more closely match high-level language constructs. This means that compiler writing becomes much easier fora CISC processo Extension question 19.01, Canyou find out whether th (One ofthe major driving forces for creating RISC processors was the opportunity they would ig. Pipelining isa form of parallelism applied specifically to provide for eficient pipel instruction execution, Other forms of parallelism are discussed in Section 19.02, Quam © Pipelining: insructiontevel paraliism : aes 1B ity The underlying principle of pipelining is thatthe fetch-decode-execute cycle described in Chapter 5 (Section 5.04) can be separated into a number of stages. One possibility isa five-stage model consisting of + instruction fetch (IF) + instruction decode (1D) aa + operand fetch (OF) + instruction execute (IE) + result write back (WE, Figure 19.01 shows how pipelining would work with this five-stage breakdown of instruction handling, For pipelining to be implemented, the construction ofthe processor must have five independent unis, with each handling ane of the five stages identified. This explains the need for a RISC processor to have many register we sets; each processor unit must have access to its own _- 2 1D 12 | 22 | 32 | 42 | 52 | 62 set of registers. Figure 19.01 uses the representation 1.1, L2 and so on to define the instruction and the stage of the instruction. Initially only the fist stage of the firstinstruction has entered the pipeline. At clock cycle6 the frst instruction has left the pipeline, the lat stage of instruction 2s being handled and instruction 6 has just entered. Itcan be seen that once under way the pipeline is handling ive stages of ive individual instructions. In particular, at each clock cycle the complete processing of one instruction has, finished, without the pipeline the processing time would be fve times longer. (One issue that has to be dealt with regardinga pipelined processor's interrupt handling The discussion in Chapter 5 (Section 5.06) referred to a processor with instructions handled sequentially. n the pipelined system described above there wil be five Instruct ns in the pipeline when an interrupt occurs. One option for handling the interrupt isto erase the pipeline Contents forthe latest four instructions to have entered. Then the normal interrupt-handl routine can be applied to the remaining instruction. The other option is to construct the individual units in the processor with individual pragram counter registers, This allows current data to be stored for al ofthe instructions in the pipeline while the interrupts handled. ng, Figure 19.01 Pipelining for five-stage instruction handlingChapter 19: Processor and Computer Architecture ISC. The first adds the contents ext instruction is similar but uses truction will be reading the Stores 2 pipelined structure, the secon 19.03 Parallel processing Parallel processor systems One computer can have multiple processors running in parallel In principle, there are four categories of system: + SISD Single Instruction Single Data stream) + SIMD (Single instruction Multiple Data stream) + MISD (Multiple Instruction Single Data stream) + MIMD (Muitiple instruction Multiple Data stream). SISD (Single Instruction Single Data stream) isthe typical arrangement foundin early personel computers. There sa single processor s0 no pracessor parallelism, The single data stream just means one memory. SIMD (Single instruction Multiple Data stream) describes how an array or vector processor works. The multiple processors each have theirowa memory. One instructions input and each processor executes tis instruction using data avaliable in it dedicated memory. MISD (Multiple instruction Single Data stream) isn’t implemented in commercial products. MIMO (Mukiple Instruction Multiple Data stream has examples in modern personal computers which ae of the symmetric multipracessor type using identical processors. n this case, each processor executes a diferent individual instruction. The multiple data stream ccan be provided by a single memory suitably partitioned. Each processor might have a dedicated cache memory. Parallel computer systems Examples of one type of multicomputer system are called massively parallel computers. ‘These are the systems used by large organisations for computations iwolvinghighy complex mathematical processing, They are the latest nan evolution of what have traditionally been called ‘supercomputers’ The major difference in architectures that instead of having a bus structure to support multiple processors tere sa network infrastructure to support multiple computer units. The programs running onthe different computers can communicate by passing messages using the network ‘An alternative type of multicomputer system is cluster computing, where a very large number of PCs are networked.‘Acontrol unit can be haré-uired or microprogrammed. RISC Reduced instruction Set Computers) processors have a number of advantages compared t0CISC (Complex instruction Set Computers). Pipelining is one ofthe easons for choosing a RISC architecture, Parallelism can be based at the instruction level, processor level or computer level Exam-style Questions 1 Computer systems are now often constructed with RISC processors. {State what the acronym RISC stands for Wi State four characteristics tobe expected of aRISC system, ARISC processor's ely tobe hard-wired. 1 Explain what thisterm means and which specie part the processor wil be hard-wired, Ji State what the alternative to hard-wirings and what hardware component is needed ta be part ofthe processor to allow this alternative to be implemented. Parallelism can be achieved ina numberof ways 1 dent tree diferent types of parallelism IK identity which type pipelining belongs to, TW Usinga ciagram, explain how pipelining works. Interrupt handlingis not so straightforward ina pipelined system, Explain why this is so and give a brief ‘account of how problems can be avoided. 0 4 3 2 8 oy a