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B.Sc. Electronics Engineering Fall 2014: Engr. Kamran Javed

The document discusses various addressing modes used in PIC18 microcontrollers including immediate, direct, register indirect, indexed ROM, and indexed addressing. It also covers register indirect RAM addressing using FSR registers, auto-incrementing of FSR pointers, register indirect ROM addressing using TBLPTR to access data tables in program memory, and bank switching to access different sections of data RAM through the BSR register.

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Imran Shaukat
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57 views

B.Sc. Electronics Engineering Fall 2014: Engr. Kamran Javed

The document discusses various addressing modes used in PIC18 microcontrollers including immediate, direct, register indirect, indexed ROM, and indexed addressing. It also covers register indirect RAM addressing using FSR registers, auto-incrementing of FSR pointers, register indirect ROM addressing using TBLPTR to access data tables in program memory, and bank switching to access different sections of data RAM through the BSR register.

Uploaded by

Imran Shaukat
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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B.Sc.

Electronics Engineering
Fall 2014

Lecture 7

Engr. Kamran Javed


PIC18 : Addressing Modes
How CPU can access the data ?
1. Immediate
2. Direct
3. Register Indirect
4. Indexed ROM
1. Immediate
An 8-bit data (Literal) is provided in the instruction. MOVLW 0x25
2. Direct
An 8-bit address is provided (256 bytes of active bank)
An option for destination (F or W) is available in all
direct address instructions
PIC18 : Addressing Modes contd.
3. Register Indirect Data RAM Addressing
A register, FSRx (File Select Register), is used as a
pointer to data RAM location. (This register gives 12 bit
address)
FSRx is loaded with address, prior to the instruction
LFSR 0, 0x30 ; Load FSR0 with address 0x30
LFSR 1, 0x6F ; Load FSR1 with address 0x6F
MOVWF INDF0 ; copy W to RAM pointed by FSR0
MOVWF INDF1 ; copy W to RAM pointed by FSR1
INDFx is not a physical memory location, just an
address within SFRs.
An advantage of Register Indirect is that it makes
accessing the data DYNAMIC rather than STATIC.
INCF FSR0L, F ; Increment lower byte of pointer
PIC18 : Addressing Modes contd.
Auto-Increment of FSR

Above Table shows a syntax for CLRF instruction, it works


for all such instructions.
Auto-Increment or Auto-Decrement work for 12-bits of
FSR, has no effect on STATUS register.
MOVWF POSTINC1 ; Copy W to RAM & INC FSR1
PIC18 : Addressing Modes contd.
Register Indirect ROM Addressing (Table Processing)
No program instruction can be stored in data RAM, but some fix
data elements can be stored in Program ROM.
2 MB of program ROM is addressed by PC. To read data from this
area, there is a pointer, TBLPTR (21-bit), three registers (U, H & L)
in SFRs.
TBLRD (TaBLe ReaD) instruction reads a byte of data, through
TBLPTR, and save it in TABLAT (TABle LATch).
TBLWR (TaBLe WRite) instruction is also available for Flash type
ROMs
PIC18 : Addressing Modes contd.
Define Byte (DB)
DB data directive is used to allocate ROM memory for
byte sized chunks.
PIC18 : Addressing Modes contd.
Lookup Table
Lookup tables allow access to elements frequently
used. These tables can be placed in Program ROM as
well as in data RAM.
When lookup table is in Program ROM: A fix value is
added to PCL to index into lookup table and upon
return from table the RETLW instruction will provide
the desired element into WREG. Exp: CALL XSQR_TABLE
PIC18 : Addressing Modes contd.

Lookup Table in data RAM: can be accessed by FSR.


Example: MOVFF PLUSW2, PORTD
will bring elements of the lookup table from the address
location (FSR2 + WREG)
PIC18 : Addressing Modes contd

4. Indexed ROM
A special technique to access EEPROM ,

EEADR and EEDATA are two SFRs to read or write on


this ROM through EECON2.

Detail will be discussed later


PIC18 : Bank Switching
All instructions have a letter A :
MOVWF F, A ; by default A=0, Access Bank
; if A=1, active bank by BSR
Only low nibble of BSR indicates the active bank: 0 ~ F
This low nibble becomes the higher part of the 12-bit
address for 4K data RAM.
SFRs always starts at address FFFh and goes down.
INCF MyReg, F, 1 and INCF MyReg, F, 0
has entirely different locations for increment.
MOVLB 0x2 ; Load 2 in BSR (Bank 2)
Every active bank gives access to 256 bytes + 128 SFRs
MOVFF doesnt need bank switching
PIC18 : CHECKSUM Byte
To ensure the integrity of ROM contents an extra byte is
tagged to end of a series of data bytes called CHECKSUM
byte. Procedure is as follows:
1. Add the bytes together and drop carries
2. Take 2s complement of sum. This is Checksum byte
To perform counter check: Add all bytes including checksum,
the answer must be zero. Otherwise there is some error.
Example: Let 4 bytes of code: 25, 62, 3F, 52. Find checksum? and
cross check.
Sol: 25+62+3F+52 = 118 2s complement of 18 = E8 (checksum)
Check: 25+62+3F+52+E8 = 200 we get 00 so data is correct
By changing some data: let 22 instead of 62, than
25+22+3F+52+E8 = 1C0 a non-zero result, so some fault

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