Asynchronous Circuit Design. Chris J.

Myers
Copyright 2001 by John Wiley & Sons, Inc.
ISBNs: 0-471-41543-X (Hardback); 0-471-22414-6 (Electronic)

Appendix A
VHDL Packages

I have always imagined that Paradise will be a kind of library.

--Jorge Luis Borges

A.1 NONDETERMINISM.VHD

This package defines functions to model random selection and random delays.
library ieee ;
use ieee.math-real. all;
use ieee.std-logic-1164.all;
use ieee.std-logic-arith. all;
package nondeterminism is
shared variable sl:integer:=844396720;
shared variable s2:integer:=821616997;
-- Returns a number between 1 and num.
impure function select ion (constant num : in integer) return integer ;
-- Returns a std,logic-vector of size bits between 1 and num.
impure function selection(constant num:in integer;
constant size: in integer) return std-logic-vector;
-- Returns random delay between lower and upper.
impure function delay (constant 1: in integer;
constant u: in integer) return time ;

347
348 VHDL PACKAGES

end nondeterminism;
package body nondeterminism is
impure function selection(constant num:in integer) return integer is
variable result:integer;
variable tmp,real:real;
begin
uniform(sl,s2,tmp_real);
result := 1 + integer(trunc(tmp-real * real(num>>>;
returdresult) ;
end selection;
impure function select ion (constant num : in integer ;
constant size: in integer)
return std-logic-vector is
variable result:std-logic-vector(size-1 downto 0);
variable tmp-real:real;
begin
uniform(sl,s2,tmp-real);
result := conv-stdlogic-vector(integer(trunc(tmprea1 * real(num))>
+l,size);
return(result) ;
end selection;
impure function delay (constant 1: in integer ;
constant u: in integer) return time is
variable result:time;
variable tmp : real ;
begin
uniform(sl,s2,tmp);
result:=(((tmp * real(u - 1)) + real(l)> * 1. ns);
return result;
end delay;
end nondeterminism;

A.2 CHANNELJHD

This package defines a channel data type and send and receive functions.
library IEEE ;
use IEEE.std-logic-1164.all;
package channel is
constant MAX_BIT,WIDTH:natural:=32;
subtype datatype is std-logic-vector((MAXBIT-WIDTH-l) downto 0 >;
constant dataZ:datatype:=datatype) (others => Z);
constant dataO:datatype:=datatype(others => 0);
constant dataACK:dataType:=dataType'( others => )I));
type channel is record
dataright,dataleft:datatype;
pending-send,pending-recv,sync:stdlogic;
end record ;
type bools is array (natural range 0) of boolean;
-- Used to send data on a channel
procedure send (signal cl : inout channel) ;
procedure send(signa1 cl : inout channel; signal dl : inout std-logic) ;
procedure send(signa1 cl :inout channel ;signal dl :inout std-logic;
signal c2 : inout channel ; signal d2 : inout std-logic) ;
 CHANNEL. VHD 349

procedure send(signa1 cl : inout channel ; signal dl : inout std-logic ;

signal c2 : inout channel ; signal d2 : inout std-logic ;
signal c3 : inout channel ; signal d3 : inout std-logic) ;
procedure send(signa1 cl : inout channel; signal dl : inout stdlogic-vector) ;
procedure send(signa1 cl : inout channel ; signal dl : inout stdlogic-vector ;
signal c2:inout channel ;signal d2 :inout std-logic-vector);
procedure send(signa1 cl : inout channel ; signal dl : inout std-logic-vector ;
signal c2: inout channel; signal d2: inout std-logic-vector;
signal c3:inout channel ;signal d3 :inout std-logic-vector);
-- Used to receive data on a channel
procedure receive (signal cl : inout channel) ;
procedure receive (signal cl : inout channel ; signal dl : inout sthlogic) ;
procedure receive (signal cl : inout channel ; signal dl : inout stdlogic ;
signal c2 : inout channel ; signal d2 : inout std-logic) ;
procedure receive (signal cl : inout channel ; signal dl : inout stdlogic ;
signal c2 : inout channel ; signal d2 : inout std-logic ;
signal c3 : inout channel ; signal d3 : inout std-logic) ;
procedure receive (signal cl :inout channel ;signal dl :inout stdlogic-vector);
procedure receive (signal cl : inout channel ; signal dl : inout stdlogic,vector;
signal c2:inout channel ;signal d2 :inout std-logic-vector);
procedure receive (signal cl : inout channel ; signal dl : inout stdlogic-vector ;
signal c2:inout channel ;signal d2 :inout std-logic-vector;
signal c3:inout channel ;signal d3 :inout std-logic-vector);
-- Initialization function called in a port declaration
-- as a default value to initialize a channel.
function init-channel return channel;
function active return channel ;
function passive return channel ;
-- Test for pending communication on a channel
function probe (signal than: in channel) return boolean;
znd channel;
package body channel is
procedure validate (signal data: in std.-logic-vector) is
begin
assert f data'LENGTH <= MAX-BIT-WIDTH >
report "Bit width is too wide" severity failure;
end validate;
function init-channel return channel is
begin
return(dataright=>dataZ,dataleft=>dataZ,
pending-send=>'Z',pendingrecv=>'Z',sync=>'Z');
end init-channel;
function active return channel is
begin
return(dataright=>dataZ,dataleft=>dataZ,
pending-send=>'Z',pendingrecv=>'Z',sync=>'Z');
end active;
function passive return channel is
begin
return(dataright=>dataZ,dataleft=>dataZ,
pending-send=>'Z',pendingrecv=>'Z',sync=>'Z');
end passive;
procedure send-handshake (variable done: inout boolean;
variable reset : inout boolean;
signal than: inout channel) is
begin
350 VHDL PACKAGES

if (done=false) then
if (reset=false) then
if (chan.pending-send='Z') then
chan.pending-send<='l';
end if;
if (chan.sync='l') then
chan.pending-send<='Z';
reset:=true;
end if;
elsif (chan.sync='Z') then
done:=true;
end if;
end if;
end send-handshake;
function zero-extend(signa1 data: in std-logic) return datatype is
variable extdata:datatype;
begin
extdata := data0;
extdata(0) := data;
return extdata;
end zero-extend;
function zero-extendkignal data: in std.-logic-vector)
return datatype is
variable extdata:datatype;
begin
validate(data);
extdata := data0;
extdata( data'length - 1 downto 0 > := data;
return extdata;
end zero-extend;
procedure send (signal c 1: inout channel) is
variable done:bools(l to 1) := (others => false);
variable reset:bools(l to I> := (others => false);
begin
loop
send,handshake(done(l),reset(l),cl);
exit when (done(l)=true);
wait on cl.sync;
end loop;
end send;
procedure send(signa1 cl : inout channel ; signal dl : inout std-logic) is
variable done:bools(l to I> := (others => false);
variable reset:bools(l to 1) := (others => false);
begin
cl.dataright <= zero-extend(d1);
loop
send-handshake(done(l),reset(l),cl);
exit when (done(l)=true);
wait on cl.sync,cl.pending-send,cl.pendingrecv;
end loop;
end send;
procedure send(signal cl : inout channel ; signal dl : inout std-logic ;
signal c2 : inout channel ; signal d2 : inout std-logic) is
variable done:bools (I to 2) := (others => false) ;
variable reset:bools(l to 2) := (others => false);
begin
 CHANNEL. VHD 351

cI.dataright <= zero-extend(d1);

c2.dataright <= zero-extend(d2);
loop
send-handshake(done(I),reset(I),cI);
sendhandshake(done(2),reset(2),~2);
exit when ((done(I)=true> and (done(2)=true));
wait on cI.sync,c2.sync;
end loop;
end send;
procedure send(signa1 cl : inout channel ;signal dl : inout St&logic ;
signal c2 : inout channel ; signal d2 : inout std-logic ;
signal c3 : inout channel ; signal d3 : inout std-logic) is
variable done :bools(I to 3) := (others => false) ;
variable reset:bools(I to 3) := (others => false);
begin
cI.dataright <= zero-extend(d1);
c2.dataright <= zero-extend(d2);
c3.dataright <= zero-extend(d3);
loop
sendhandshake(done(I),reset(I),cI);
sendhandshake(done(2),reset(2),~2);
sendhandshake(done(3),reset(3),~3);
exit when ((done(I)=true) and (done(2)=true> and (done(3>=true)>;
wait on cI.sync,c2.sync,c3.sync;
end loop;
end send;
procedure send (signal c I : inout channel ;
signal dl :inout std-logic-vector) is
variable done:bools (I to I> := (others => false);
variable reset:bools(I to I> := (others => false);
begin
cI.dataright <= zero-extend(d1);
loop
send-handshake(done(I),reset(I),cI);
exit when (done(I)=true);
wait on cI.sync,cI.pending-send,cI.pendingrecv;
end loop;
end send;
procedure send(signa1 cl : inout channel ;signal dl : inout std-logic-vector;
signal c2 : inout channel ; signal d2 : inout std-logic-vector) is
variable done:bools(I to 2) := (others => false);
variable reset : bools(1 to 2) := (others => false) ;
begin
cI.dataright <= zero-extend(d1);
c2.dataright <= zero-extend(d2);
loop
send-handshake(done(I),reset(I),cI);
sendhandshake(done(2),reset(2),~2);
exit when ((done(I)=true) and (done(2)=true>);
wait on cI.sync,c2.sync;
end loop;
end send;
procedure send(signa1 cl : inout channel ; signal dl : inout std-logic-vector;
signal c2:inout channel ;signal d2 :inout std-logic-vector;
signal c3 : inout channel ; signal d3 : inout std-logic-vector) is
variable done:bools(I to 3) := (others => false);
352 VHDL PACKAGES

variable reset:bools(l to 3) := (others => false);

begin
cl.dataright <= zero-extend(d1);
c2.dataright <= zero-extend(d2);
c3.dataright <= zero-extend(d3);
loop
send-handshake(done(l),reset(l),cl);
sendhandshake(done(2),reset(2),~2);
send_handshake(done(3),reset(3),~3);
exit when ((done(l>=true> and (done(2)=true) and (done(3)=true));
wait on cl.sync,c2.sync,c3.sync;
end loop;
end send;
procedure recv-hse (variable done : inout boolean;
variable reset: inout boolean;
signal than: inout channel) is
begin
if (done = false) then
if (reset = false) then
if ((chan.pending-recv='Z') and
(chan.sync='Z')) then
champending-recv<='l';
end if;
if (chan.sync='l') then
chan.pending-recv<='Z';
end if;
if ((champending-send='l') and
(chaupending-recv='l') and
(chan.sync='Z')) then
chan.sync<='l';
end if;
if ((chan.pending-send='Z') and
(chan.pending-recv='Z') and
(chan.sync='l')) then
chan.sync <= 'Z';
reset:=true;
end if;
elsif (than . sync= Z > then
done :=true;
end if;
end if;
end recv-hse;
procedure recv-hse (variable done : inout boolean;
variable reset : inout boolean;
signal than: inout channel ;signal data:out stdlogic) is
begin
if (done=false) then
if (reset=false) then
if ((chan.pending-recv='Z') and
(chan.sync= 'Z')) then
chan.pending-recv<='l';
end if; 9
if (chan.sync='l') then
chan.pending-recv<='Z';
end if;
if ((champending-send='l') and
 CHANNEL. VHD 353

(chawpending-recv='l') and
(chan.sync='Z')) then
chan.sync<='l';
data<=chan.dataright(O);
end if;
if ((chan.pending-send='Z') and
(chan.pending-recv='Z') and
(than. sync=' I'>> then
chan.sync<='Z';
reset :=true;
end if;
elsif (chan.sync='Z') then
done:=true;
end if;
end if;
end recvhse;
procedure recv-hse (variable done : inout boolean;
variable reset : inout boolean;
signal than : inout channel ;
signal data:out std-logic-vector) is
begin
if (done=false) then
if (reset=false) then
if ((chan.pending-recv='Z') and
(chan.sync='Z')) then
chan.pending-recv<='l';
end if;
if (chan.sync='l') then
chan.pending-recv<='Z';
end if;
if ((chan.pending-send='l') and
(chan.pending-recv='l') and
(chan.sync='Z')) then
chan.sync<='l';
dataC=chan.dataright(data'length - 1 downto 0);
end if;
if ((chan.pending-send='Z') and
(chan.pending-recv='Z') and
(chan.sync='l')) then
chan.sync<='Z';
reset :=true;
end if;
elsif (chan.sync='Z') then
done :=true;
end if;
end if;
end recv-hse;
procedure receive (signal cl:inout channel) is
variable done:bools(l to I) := (others => false);
variable reset:bools(l to I) := (others => false);
begin
loop
recvhse(done(l),reset(l),cl);
exit when (done(l>=true>;
wait on cl.pending-send,cl.sync,cl.pendingrecv;
end loop;
354 VHDL PACKAGES

end receive;
procedure receive (signal cl : inout channel ; signal dl : inout std-logic) is
variable done:bools(l to 1) := (others => false);
variable reset:bools(l to 1) := (others => false);
begin
loop
recvhse(done(l),reset(l),cl,dl);
exit when (done(l)=true);
wait on cl.pending-send,cl.sync,cl.pendingrecv;
end loop;
end receive;
procedure receive (signal cl : inout channel ; signal dl : inout stdlogic ;
signal c2 : inout channel ; signal d2 : inout std-logic) is
variable done:bools(l to 2) := (others => false);
variable reset:bools(l to 2) := (others => false);
begin
loop
recv-hse(done(l),reset(l),cl,dl);
recvhse(done(2),reset(2),c2,d2);
exit when ((done(l)=true> and (done(2>=true>>;
wait on cl.pending-send,cl.sync,cl.pendingrecv,
c2.pendingqsend,c2.sync,c2.pendingrecv;
end loop;
end receive;
procedure receive (signal cl : inout channel ; signal dl : inout stdlogic;
signal c2 : inout channel ; signal d2 : inout std-logic ;
signal c3 : inout channel ; signal d3 : inout std-logic) is
variable done:bools(l to 3) := (others => false);
variable reset:bools(l to 3) := (others => false);
begin
loop
recv-hse(done(l),reset(l),cl,dl);
recvhse(done(2),reset(2),c2,d2);
recv_hse(done(3),reset(3),c3,d3);
exit when ((done(l)=true) and (done(2>=true> and (done(3)=true));
wait on cl.pending_send,cl.sync,cl.pendingrecv,c2.pendingsend,
c2.sync,c2.pending_recv,c3.pendingsend,c3.sync,c3.pendingrecv;
end loop;
end receive;
procedure receive (signal cl : inout channel ; signal dl : inout stdlogic-vector
> is
variable done:bools(l to 1) := (others => false);
variable reset:bools(l to 1) := (others => false);
begin
validate( dl >;
loop
recv-hse(done(l),reset(l),cl,dl);
exit when (done(l)=true);
wait on cl.pending-send,cl.sync,cl.pendingrecv;
end loop;
end receive;
procedure receive (signal cl : inout channel ; signal dl : inout std-logic-vector ;
signal c2 :inout channel ;signal d2 :inout std-logic-vector
.) .is
variable done:bools(l to 2) := (others => false);
variable reset:bools(l to 2) := (others => false);
 HANDSHAKE. VHD 355

begin
validate( dl );
validate( d2 );
loop
recv-hse(done(l),reset(l),cl,dl);
recv_hse(done(2),reset(2),c2,d2);
exit when ((done(l)=true) and (done(2>=true>>;
wait on cl.pending-send,cl.sync,cl.pendingrecv,
c2.pending-send,c2.sync,c2.pendingrecv;
end loop;
end receive;
procedure receive (signal cl : inout channel ; signal dl : inout std-logic-vector ;
signal c2: inout channel ;signal d2 :inout std-logic-vector;
signal c3: inout channel ;signal d3 :inout std-logic-vector
> is
variable done:bools(l to 3) := (others => false);
variable reset:bools(l to 3) := (others => false);
begin
validate( dl );
validate( d2 );
validate( d3 );
loop
recv-hse(done(l),reset(l),cl,dl);
recv_hse(done(2),reset(2),c2,d2);
recv_hse(done(3),reset(3),c3,d3);
exit when ((done(l>=true) and (done(2)=true) and (done(3)=true));
wait on cl.pending_send,cl.sync,cl.pending.recv,c2.pendingsend,
c2.sync,c2.pending_recv,c3.pendingsend,c3.sync,c3.pendingrecv;
end loop;
end receive;
function probe( signal than: in channel ) return boolean is
begin
return ((chanpending-send='I') or (chan.pendingrecv='l'));
end probe;
end channel;

A.3 HANDSHAKE.VHD

This package defines assign and guard functions on signals.

library ieee ;
use ieee.std-logic-1164.all;
use work.nondeterminism. all;
package handshake is
procedure assign(signa1 sig: inout std-1ogic;constant val: stdlogic;
constant 1: integer ; constant u : integer) ;
procedure assignkignal sigl : inout std-logic ; constant vail : stdlogic ;
constant 1I:integer;constant ul:integer;
signal sig2 :inout std,logic ;constant val2:stdlogic;
constant 12:integer ;constant u2:integer);
procedure assign(signa1 sigl : inout std-logic; constant vall : stdlogic ;
constant 1l:integer; constant ul:integer;
signal sig2 :inout std,logic ;constant val2:stdlogic;
constant 12: integer;constant u2: integer;
356 VHDL PACKAGES

signal sig3 :inout std-logic ;constant val3:stdlogic;

constant 13:integer ;constant u3:integer);
procedure vassignCsigna1 sig: inout std-logic ; constant val : stdlogic ;
constant Linteger; constant u:integer);
procedure vassign(signa1 sigl: inout std-logic; constant vail : St&logic;
constant 1l:integer ;constant ul:integer;
signal sig2 :inout std-logic ;constant val2:stdlogic;
constant 12:integer ;constant u2:integer);
procedure vassign(signa1 sigl: inout std_logic;constant vall: stcllogic;
constant 1l:integer;constant ul:integer;
signal sig2 :inout std-logic ;constant val2:stdlogic;
constant 12:integer ;constant u2:integer;
signal sig3 :inout std-logic ;constant val3:stdlogic;
constant 13:integer ;constant u3:integer);
procedure guard(signa1 sig: in std,logic ; constant val: sthlogic) ;
procedure guard-or (signal sigl : in stdlogic; constant vall : stdlogic ;
signal sig2: in std-logic ;constant va12: stdlogic);
procedure guard-or (signal sigl: in stdlogic ;constant vall:stcLlogic;
signal sig2: in std-logic ;constant val2:stdlogic;
signal sig3: in std-logic ;constant val3:stdlogic);
procedure guard-and(signa1 sigl: in stdlogic; constant vall: stdlogic;
signal sig2: in std-logic; constant va12:stcLlogic);
procedure guard-and(signa1 sigl : in stdlogic ; constant vall : stdlogic ;
signal sig2: in std-logic ;constant val2:stdlogic;
signal sig3: in std-1ogic;constant va13: std-logic) ;
end handshake;
package body handshake is
procedure assigncsignal sig: inout std-logic ; constant val: St&logic ;
constant 1: integer; constant u: integer) is
begin
assert (sig /= val) report "Vacuous assignment" severity failure;
sig <= val after delay&u);
wait until sig = val;
end assign;
procedure assigncsignal sigl : inout std-logic ; constant vall : stcLlogic;
constant 1l:integer;constant ul:integer;
signal sig2 : inout std-logic ; constant va12 : stdlogic ;
constant 12:integer ;constant u2:integer) is
begin
assert (sigl /= vall or sig2 /= va12)
report "Vacuous assignment )) severity failure;
sigl <= vall after delay(ll,ul);
sig2 <= va12 after delay(12,u2);
wait until sigl = vail and sig2 = va12;
end assign;
procedure assign(signa1 sigl: inout std-1ogic;constant vall : stdlogic;
constant 1l:integer ;constant ul:integer;
signal sig2 :inout std-logic ;constant val2:stdlogic;
constant 12:integer ;constant u2:integer;
signal sig3 :inout std-logic ;constant val3:stdlogic;
constant 13:integer ;constant u3:integer) is
begin
assert (sigl /= vall or sig2 /= va12 or sig3 /= va13)
report "Vacuous assignment" severity failure;
sigl <= vall after delay(ll,ul);
sig2 <= va12 after delay(12,u2);
 HANDSHAKE.VHD 357

sig3 <= va13 after delay(13,u3);

wait until sigl = vail and sig2 = va12 and sig3 = val3;
end assign;
procedure vassign(signa1 sig: inout St&logic; constant val : stcllogic ;
constant 1: integer ; constant u : integer) is
begin
if (sig /= val) then
sig <= val after delay(l,u);
wait until sig = val ;
end if;
end vassign;
procedure vassign(signa1 sigl : inout St&logic; constant vail : std-logic ;
constant 11: integer;constant ul : integer;
signal sig2 :inout std,logic ;constant va12:stdAogic;
constant 12:integer ;constant u2:integer) is
begin
if (sigl /= vail) then
sigl <= vall after delay(ll,ul);
end if;
if (sig2 /= va12) then
sig2 <= va12 after delay(12,u2);
end if;
if (sigl /= vail or sig=! /= va12) then
wait until sigl = vail and sig2 = val2;
end if;
end vassign;
procedure vassign(signa1 sigl: inout stdAogic;constant vall: std-logic;
constant 1l:integer ;constant ul:integer;
signal sig2 :inout std-logic ;constant val2:sbLlogic;
constant 12:integer ;constant u2:integer;
signal sig3 :inout std-logic ;constant va13:stdAogic;
constant 13:integer ;constant u3:integer) is
begin
if (sigl /= vail) then
sigl <= vall after delay(ll,ul);
end if;
if (sig2 /= val2) then
sig2 <= va12 after delay(12,u2);
end if;
if (sig3 /= val3) then
sig3 <= va13 after delay(13,u3);
end if;
if (sigl /= vail or sig2 /= va12 or sig3 /= va13) then
wait until sigl = vail and sig2 = val2 and sig3 = va13;
end if;
end vassign;
procedure guard(signa1 sig: in std-logic; constant val: stcLlogic) is
begin
if (sig /= val) then
wait until sig = val;
end if; ,
end guard;
procedure guard-or (signal sigl: in std-logic ;constant vall:stcllogic;
signal sig2: in std-logic ;constant val2:sbLlogic) is
begin
if (sigl /= vail and sig:! /= val2) then
358 VHDL PACKAGES

wait until sigl = vall or sig2 = va12;

end if;
end guard-or;
procedure guard-or (signal sigl :in std-logic ;constant vall:std-logic;
signal sig2: in std-logic ;constant val2:stdAogic;
signal sig3: in std-logic ;constant val3:stdJogic) is
begin
if (sigl /= vail and sig2 /= va12 and sig3 /= val3) then
wait until sigl = vall or sig2 = va12 or sig3 = va13;
end if;
end guard-or;
procedure guard-andkignal sigl : in std-logic ; constant vall : St&logic ;
signal sig2: in std-logic ;constant val2:stdJogic) is
begin
if ( sigl /= vail or sig2 /= va12 > then
wait until sigl = vall and sig:! = val2;
end if;
end guard-and;
procedure guard-and (signa 1 sigl: in std_logic ;constant vall:stdAogic;
signal sig2: in std-logic ;constant val2:stdAogic;
signal sig3:in std-1ogic;constant val3:stdAogic) is
begin
if (sigl /= vail or sig:! /= va12 or sig3 /= va13) then
wait until sigl = vail and sig2 = va12 and sig3 = va13;
end if;
end guard-and;
end handshake;