ECE 343

Lab 3 Report
MOS Amplifier Design Parts 1 & 2

AJ Schroeder ajschro2
Partner: Viren Mascarenhas vmasca2
Section Q
Introduction:
This lab was heavily focused on the design of amplifiers using MOS transistors and
creating/testing these designs in PSPICE. In the first part of the lab (phase 1), our goal was to
design a single-stage amplifier circuit based off given specifications in the lab manual. To start,
we constructed the DC bias circuit for an amplifier. We then investigated the impact of coupling
capacitors on the amplifiers frequency response. After that, we studied the effect of a changing
input and output resistances on the amplifiers performance. The specified characteristics of
phase 1s amplifier from the lab manual are shown below.
Table 1: Specifications for Lab 3 Phase 1 amplifier

Mid-band Gain, | | 20 V/V

DC Operating Point = 1.5
Number of DC Voltage Sources Allowed 1, where = 3
Maximum Resistor Value Available = 10

In the second part of the lab (phase 2), we designed a two-stage amplifier circuit to
satisfy additional specifications given in the lab manual. We achieved these specifications
through two kinds of two-stage amplifier. We, again, examined the effects of coupling
capacitors and changed input/output resistances on the amplifiers responses and
characteristics. The new specifications of the cascade amplifier are shown below.
Table 2: Specifications for Lab 3 Phase 2 amplifier

Overall Mid-band Gain, | | 16 V/V

Load Resistance Values = 500
Lower 3-dB Cut-off Frequency of Amplifier = 1
Number of DC Voltage Sources Allowed 1, where = 3

Of course, the MOSFETs used in the lab have parameters inherent to the transistor as
we discovered in Lab 2. The table below shows these characteristics for the MOSFETs used in
our PSPICE schematics.
Table 3: Internal Parameters of MOSFETs used within Lab 3 designs in PSPICE
Theory:
A two-stage amplifier is a very straightforward amplifier you create one amplifier, and
connect it in series to another for an overall gain. The overall gain is simply calculated the
overall gain is the gain of the first amplifier multiplied by the gain of the second amplifier. This
is a useful concept as many times it is easier to string together multiple amplifiers because one
amplifier may not always be able to easily provide that desired gain. We use DC biasing to place
the circuit (the MOSFETs) in the correct region of operation. Regarding DC bias, we can treat all
capacitance in the system as open circuits to correctly bias our circuit. We then use coupling
capacitors in the circuit to block the DC voltage between stages of the amplifier but pass the
AC signals. This way we can ignore the DC biasing of stage 1 while working on stage 2, etc. but
our amplified AC signal will pass through. This is due to the nature of capacitors; low
frequencies (such as DC voltages with f=0Hz) are blocked with a high impedance but higher
frequencies (the AC signals in our design) will pass with lower impedances.
Another theoretical problem is deciding which MOSFET amplifier topology we should use for
our design. The three topologies we chose from were given in the lab manual, and they are
shown below in the figure.

Figure 1: Three amplifier topologies in Lab 3

The common source (CS) amplifier on the left has large output voltage swings, and is good for
achieving a large voltage gain. The common gate (CG) amplifier is good to use as a current
buffer. The common drain (CD) amplifier is good for use as a unity-gain buffer. The gain of each
amplifier is shown in the figure.
Phase 1 Design Methodology and Results:
From our investigation above, we can see that the CD amplifier can never have a gain above 1,
so we wont choose that for our 20 V/V gain amplifier. We can also see from the description
above that a CS amplifier is best for a high gain therefore, we chose a CS amplifier as our
topology for Phase 1. In order to design our amplifier to have a gain of 20 V/V, we first identify
the equation for a CS amplifiers gain:

=
We then write the equation for the current going through the drain of the MOSFET:

=

Using the values from Table 1, we can find:
= 3.0 1.5 = 1.5 .
Next, we can use the magnitude of the gain equation to assist us in finding and :

= ,
2
Where = from the lab manual.

Substitution yields the following:

2
| | =

Which reduces to:
= 0.15.
We can now solve for drain current using the equations given in lab 2:
1
= ( )2
2
Algebra yields

= 9 106
Finally, can be calculated:
1.5
= = 166.667.
9 106
From the lab manual, the maximum resistance allowed is 10k. So, we can use multiple
transistors to scale up our total current such that the resistance comes within the allowed
value. In the end, we find:

= 10
Where M is the number of transistors.
= 16.6667
In PSPICE, we can use that number for M, but for real-world applications and for correctness, M
should only be positive integers (only whole transistors are allowed). So We set M=17 and find
= 9803.

Next, since we found , we must also find .

=
Substituting in earlier calculated and given values:

= .15 + .8 = .95.
= 0 = .95.
To achieve this gate voltage, we must use a voltage divider network as we are only allowed 1
voltage source.
2
=
2 + 3
When we use . 95 = , 3 = , we see that
2
= 2.15789
3
For simplicity, we used 2 = 10, and that forces 3 = 4.63.
For coupling capacitors, we were told 2 microfarads was an acceptable value for both
capacitors in the lab by the TAs before designing.

Now that we have completely determined the circuit parameters for our CS amplifier, we built
it in PSPICE. The following figures show our completed design and its power consumption.
 Figure 2a: PSPICE design of our CS amplifier circuit in Phase 1 of Lab 3

Figure 2b: Power dissipation of CS amplifier design in Phase 1 of Lab 3

The amplifier is essentially meeting all requirements besides a few small differences in some
voltages due to rounding errors of resistances in our algebra. We then looked at the transient
response and frequency response of the amplifier and found its 3-dB point. However, we found
the 3-dB frequency incorrectly it should be the point where gain is equal to the square root of
two multiplied by the maximum, not one half. This was said to be ok in the lab.
Figure 3a: Frequency response and 3-dB point of Phase 1 CS amplifier

Figure 3b: Transient response of Phase 1 CS amplifier

Phase 2 Design Methodology and Results:
In the second phase of the lab, we were to design a two-stage amplifier that meets the
requirements detailed above in the Introduction (Table 2). As stated earlier, the overall gain of
a two-stage amplifier can be written as:
= 1 2
For simplicity, we didnt change our original circuit from Phase 1. Therefore, 1 = 20, and
= 16 from Table 2. Therefore:
16
2 = = .8 .
20
We first used another CS amplifier in our second stage to achieve the overall gain. We put a
coupling capacitor between each stage in order to set each DC operating point without
considering previous stages. We set our DC operating point similarly to how we set it in Phase
1. For ease, I will refer to each resistor as their name in the figure below.

We fixed 7 = 10. Therefore, you can see below that is in parallel with 7 . So we can
write:
= ( ||7 )
Since = 500, and = .8, we can solve for :
.8
= = 0.00168.
500||10
Using an equation from our Phase 1 calculations with
2
=

We used = 0.2 as given in the lab manual:
0.00168 0.2
= = 1.68 104 .
2
Again, we needed to find a scaling factor M:
1
= ( )2
2
Which, using the values given above reduces to
= 10.5.
Again, we set M = 11 in our PSPICE simulations for real-world accuracy.
Lastly, we must set = 1 to satisfy = with = .2 and = .8. Since
= 0, = 1. To achieve this, we used a simple voltage divider:
6
=
6 + 5
Which we used to find
6 = 6 5 = 3
We used large values for these resistors to avoid any issues with the first stage of the circuit.
Otherwise, we would destroy the DC operation points of our circuit.
Figure 4 below shows our final design of the CS-CS two-stage amplifier. Capacitors C1 and C2
were set to 2 microfarads at the discretion of the lab TAs.

Figure 4: CS-CS two-stage amplifier for Phase 2 of Lab 3. Here, the load resistor is 500 ohms and the right-most
capacitor C3 was set to 16nF to achieve the 3-dB frequency of 1kHz specified in the lab manual.

We then viewed the transient and frequency response of our amplifier to verify proper
functionality. We then changed the load resistance values to 250 ohms and 100 ohms and
repeated the experiment. The circuits and transient responses for the other load resistances
will not be shown, but the accompanying C3 value will be described below.
Figure 5: Frequency response of CS-CS amplifier with load resistance of 500 ohms. The C3 capacitor was 15.5nF.
Gain is 16.122, 3-dB frequency is 988.339Hz, and 3-dB bandwidth is 60.331khZ from the markers.

Figure 6: Frequency response of CS-CS amplifier with load resistance of 250 ohms. The C3 capacitor was 14.2nF.
Gain is 8.203, 3-dB frequency is 1.04kHz, and 3-dB bandwidth is 67.631khZ from the markers.

Figure 7: Frequency response of CS-CS amplifier with load resistance of 100 ohms. The C3 capacitor was 13.5nF.
Gain is 3.3274, 3-dB frequency is 1.07kHz, and 3-dB bandwidth is 70.414kHz from the markers.
Figure 8: Transient response of Figure 4s CS-CS amplifier with a load resistance of 500 ohms. The gain is about 15.8
from the markers.

As one can see, the gain decreases as the load resistance decreases. To keep the 3-dB
frequency at 1kHz, the capacitor value decreased as the load resistance decreased. Our
responses met the specifications of the lab fairly well, so our designs were successful. The small
errors in gains and other parameters were due mostly to our rounding errors in finding
resistances and human error when placing markers on the response plots.

We then re-designed the two-stage amplifier with the second stage being a CD amplifier. From
above, the gain of a CD amplifier is

= .
1 +
Again, setting = .8 and = 500:

0.8 =
1 + (500)
Which yields
= 0.008.
We then solved for :
2
=

0.008(0.2)
= = 8 104 .
2
We then again found the scaling factor M:
1
= ( )2
2
Which reduces to:
= 50.
Now, we need to find source voltage because it is no longer 0.

=

Substituting in all values besides rearranges to find that
= 0.4.
Now we can calculate :
=
=
0.2 + 0.8 = 0.4
= 1.4.
Again, using a voltage divider and large resistance values to ensure correct DC operation we
find that 5 = 8 and 6 = 7.
Now we have determined all the parameters for the CS-CD amplifier. It is shown below note
that the resistor at the output is set to 100 MegaOhms to simulate an open circuit.

Figure 9: CS-CD amplifier for Phase 2 of Lab 3 for a 500ohm load resistance. Capacitor C3 was set to 1.55pF to
achieve the 1kHz 3-dB frequency.
Again, we looked at the frequency response and the transient response of this amplifier. We
again changed the load resistance to 250 and 100 ohms, but I will only show their frequency
responses so that the 3-dB frequency can be seen.

Figure 10: Frequency response of CS-CD amplifier with load resistance of 500 ohms. The C3 capacitor was 1.55pF.
Gain is 15.619, 3-dB frequency is 985.019Hz, and 3-dB bandwidth is 53.960kHz from the markers.

Figure 11: Frequency response of CS-CD amplifier with load resistance of 250 ohms. The C3 capacitor was 1.50pF.
Gain is 14.047, 3-dB frequency is 1.079kHz, and 3-dB bandwidth is 49.040kHz from the markers.
 Figure 12: Frequency response of CS-CD amplifier with load resistance of 100 ohms. The C3 capacitor was
1.48pF. Gain is 11.380, 3-dB frequency is 1.067kHz, and 3-dB bandwidth is 42.584kHz from the markers.

Figure 13: Transient response of Figure 9s CS-CD amplifier with a load resistance of 500 ohms. The gain is about
16.2 from the markers.
The following tables compile the results from both two-stage amplifiers investigations.

Table 4: Various statistics for CS-CS amplifier shown in Figure 4

Table 5: Various statistics for CS-CD amplifier shown in Figure 9

As shown in the above figures, both of our two-stage amplifiers were able to meet the required
specifications. The small deviances from the requirements were due to small differences when
rounding during calculations.
Also, from these tables one can see that the power consumption across the two amplifiers was
interesting we did not find any power difference with different load resistors using the CS-CS
amplifier (this is probably wrong), however we found rather significant change (~50%) in power
when changing load resistance using the CS-CD amplifier. The gain changes more significantly
when changing the load resistance of the CS-CS amplifier; I explained this a bit earlier when I
described the CS amplifier as having large output voltage swings. Because of the expression
for gain in a CS amplifier, changes in load resistance affect total drain resistance and change the
gain. This effect is smaller due to the formula for gain of a CD amplifier. Also notice the
differences in bandwidth we found the 3-dB bandwidth of the CS-CS amplifier to increase as
load resistance decreased. We found the 3-dB bandwidth of the CS-CD amplifier to decrease as
load resistance decreased. I believe that the CS-CD two-stage amplifier is probably the more
practical choice in most situations.
Conclusion:
This lab was a great way to learn how to construct a proper MOS amplifier and then
daisy-chain a few together to create a larger overall effect. It was also a great learning
experience in seeing the difference basic kinds of amplifiers (CS and CD) and learning how to
build them and view their function and responses. We also learned how to do the large amount
of algebra needed to calculate the various circuit parameters with DC biasing. Additionally, we
learned of capacitor coupling to block the DC current and voltage so that pieces of our circuit
are not interfered with. Overall, it was a fun way to learn about and actually design amplifiers
and investigate their properties without having to go through the trouble of building them on a
breadboard.