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Typical Fast Slow: Process Voltage Temperature

The .lib file contains timing and power parameters for cells in a semiconductor technology that are obtained through simulation under various conditions. Cell delay is calculated based on the input transition time and output load. The document then discusses wireload models, timing arcs, unateness, pin capacitance, linear delay models, area, and pin functionality specifications contained in a .lib file.

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swathikomati7870
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69 views

Typical Fast Slow: Process Voltage Temperature

The .lib file contains timing and power parameters for cells in a semiconductor technology that are obtained through simulation under various conditions. Cell delay is calculated based on the input transition time and output load. The document then discusses wireload models, timing arcs, unateness, pin capacitance, linear delay models, area, and pin functionality specifications contained in a .lib file.

Uploaded by

swathikomati7870
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Lib

The .lib file is an ASCII representation of the timing and power


parameters associated with any cell in a particular semiconductor
technology
The timing and power parameters are obtained by simulating the cells
under a variety of conditions.
How to calculate cell delay

Cell delay = [input transition time, the output load]

Tsmc18 PVT Values


process voltage temperature

typical 1 1.8 25

fast 1 1.98 0

slow 1 1.62 125

Wireload model syntax:

Wire_load (tsmc18) {
Resistance:
Capacitance:
Area
Slope
Fanout_length:
}

Timing arc:
Positive unateness: if a rising transition on an input causes the output to
rise
If a falling transition on an input causes the output to
fall

Negative unateness: if a rising transition on an input causes the output to


falling
If a falling transition on an input causes the output
to rising
Non-unateness: the output transition cannot be determined.

** Unateness is important for timing as it specifies how the transition can


propagate through a cell and how they appear the output of the cell

Pin capacitance:
Every input and output of a cell can specify capacitance at the pin.
In most cases, the capacitance is specified only for the cell inputs and not for
the outputs, that is, the output pin capacitance in most cell libraries is 0.

Linear delay model


Where the delay and output transition time of the cell are represented as
linear function of the two parameters.

Input transition time and output load capacitance.

D= D0 + D1* S + D2 * c

S = input transition time c= output capacitance D0, D2, D1 are constant.

**the linear delay models are not accurate over the range of input transition
time and output capacitance for submicron technologies.

** NLDM [Non Linear- Delay- Model] is used to not only for the delay but
also transition time at the output of a cell

Area: the actual silicon area used by the cell

Ex: area: 2.35;

Function: specify the functionality of a pin

Pin (z) {
Function: IN1 & IN2
.
}

The above specifies the functionality of the Z-pin of two input and cell

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