4 Passive Components

In this chapter, a brief summary of the main characteristics of the passive compo-
nents that are essential to the design of any integrated circuits will be given.

4.1 MOS Capacitors

The analysis of the MOS capacitor is generally the first step in the study of the
MOSFET transistor. As a matter of principle, we can regard it as a capacitor hav-
ing plane and parallel plates, the polysilicon gate and the doped silicon, with the
gate oxide as insulator.
In practice, it is possible to fabricate a capacitor by contacting the source and
drain junctions of a transistor, as depicted in Fig. 4.1.

Fig. 4.1. Fabrication of a capacitor from a MOS transistor

For the simplest configurations to fabricate a capacitor realized by directly con-

tacting the p substrate (Fig. 4.2), three different configurations should be distin-
guished. Lets consider the p-type substrate connected to ground.
72 4 Passive Components

VG Silicon oxide

p substrate

VG < 0
Accumulation

p substrate

VG > 0 Depleted zone has no

free charges.
Depletion

Xd

p substrate

VG >> 0
Free charges
Maximum Xd

Inversion

p substrate

Fig. 4.2. Operating regions of a MOS capacitor: accumulation, depletion, and inversion

Accumulation. Applying a negative voltage to the gate (VG < 0), a layer of holes
is induced at the oxide-semiconductor interface. The net charge of the semi-
conductor is, hence, positive, owing to the accumulation of the holes in excess
with respect to the equilibrium.
 4.2 CMOS Technology Capacitors 73

The value of the capacitance is then C = H/tox, where H is the silicon oxide per-
mittivity and tox is the oxide thickness. In this case, all of the voltage drop, VG, is
located between the conductive plates or entirely in the oxide.

Depletion. As the gate voltage increases, i.e. as VG becomes positive, the p-type
mobile charge is removed from the oxide-silicon interface. A depletion region
having thickness xd and voltage drop <S forms, where:
VG Vox  <S (4.1)

Inversion As VG further increases, also xd increases. If the voltage applied to the

gate is above a critical value, referred to as threshold voltage, VTH, a layer of
electrons is induced at the oxide-silicon interface, inverting the polarity of the
silicon. When VG > 0 but below VTH, the value of the capacitance is given by the
series capacitors related to the two regions, the oxide and the depleted region.

4.2 CMOS Technology Capacitors

In a typical CMOS process, several types of capacitors are theoretically available:

- Poly/n-well capacitor with low or high voltage oxide;
- PMOS capacitor with low or high voltage oxide;
- Poly1/poly2 capacitor.
For the present technological processes, the value of the specific capacitance for
the n-well capacitors is around 1.5 fF/Pm in case of HV capacitors, 3 fF/Pm in
2 2

case of LV capacitors, and 2 fF/Pm in case of interpoly capacitors. The gate ca-
2

pacitance of a MOS transistor equals the value of a MOS capacitor having the
same oxide thickness.
The n-well capacitors are designed like p-channel transistors without source
and drain diffusions (Fig. 4.3). The value of capacitance as a function of the gate
voltage with grounded n-well is shown in Fig. 4.4.
Such a structure (poly/n-well) has a constant value of capacitance in both ac-
cumulation and inversion. In accumulation, a negative charge crowding is located
at the bottom plate of the capacitor. The inversion zone, i.e. the positive charge
crowding in the silicon, can be obtained only at low frequency, since the positive
charge accumulation is a slow phenomenon. Therefore, we can deduce that the
poly/n-well capacitor satisfactorily operates only if the gate voltage is positive
enough.
The PMOS capacitor is instead a p-channel transistor having the drain shorted
with the source, as sketched in Fig. 4.5. In this case, the inversion region is
+ +
reached faster owing to the presence of p -type diffusions. In fact, the p regions
provide the positive charge for the inversion.
74 4 Passive Components

VG

n+

n-well

p substrate

Fig. 4.3. Practical realization of a poly/n-well capacitor

Capacitance [pF]

Inversion Depletion Accumulation

Low frequency

High frequency

Region for low VG [V]

frequency working
VTH

Fig. 4.4. C-V characteristic of a poly/n-well capacitor

Lets consider the practical case of a device in which both positive and negative
charge pumps (see Chap. 15) are present and operate at the frequency of 30 MHz.
In the positive charge pumps, which are able to generate voltages higher than
the supply voltage, the poly/n-well capacitors operate in the accumulation region
since the poly gate has a higher voltage than the n-well. Hence, the majority car-
ries (electrons) that are present at the oxide-semiconductor interface are provided
by the bulk at a time rate that is negligible with respect to the switching frequency.
The case of the negative pumps, which generate voltages below the ground poten-
tial, is different. In fact, in this case, the MOS system operates in the inversion re-
gion and the minority carriers (holes) can be provided only by the bulk at a rate
+
that can be measured in seconds. Two p diffusions are therefore added to the ca-
pacitor structure so as to generate minority carriers. At low frequency, the channel
+
is in thermal equilibrium with the p regions, and we can assume that the required
carriers are instantaneously provided to the interface. At high frequency, the holes
+
are not able to diffuse from the p regions toward the middle of the channel with
 4.2 CMOS Technology Capacitors 75

the speed required to follow the signal applied to the gate. This causes channel RC
parasitic effects that become more relevant when the carrier mobility is low and
+
the distance between the p regions is great.

VG
VDD

p+ p+ n+

n-well

p substrate

Fig. 4.5. PMOS capacitor

Lets now calculate the maximum frequency of the gate signal that can be ap-
plied to this type of capacitor in inversion. The time constant associated with the
channel can be expressed as:
W ch Rch C (4.2)
where C, which is the capacitance associated with the gate oxide, can be calcu-
lated starting from the channel dimensions:
C Cox W L (4.3)
Rch is the channel resistance and can be obtained from the characteristic of the
MOS transistor in the linear region:
1 W
P eff Qinv (4.4)
Rch L
Qinv is the charge per unit of area in the inversion layer and Peff if the effective mo-
bility. Based on the three foregoing equations, we can calculate the frequency as-
sociated with the channel RC:
1 1 P eff Qinv (4.5)
f ch
2SW ch 2S C ox L2
In particular, we can notice that the frequency of the pole scales down as the
+
square of L, which is the distance of two p diffusions. This is the reason why it is
very important to accurately determine the value of L of the capacitors of the
negative charge pumps.
It is also possible to fabricate capacitors without using the silicon as plate, such
as in the case of the poly1/poly2 capacitor. The CMOS processes that use two lay-
ers of polysilicon, i.e. the processes for non-volatile memories, offer this possibil-
ity.
76 4 Passive Components

Furthermore, metal layers can also be used to fabricate capacitors. The main
limitation is in the value of capacitance that can be obtained. For a typical process,
the thickness of the gate oxide ranges between 120 and 150 , whereas the in-
ter-metal dielectric that forms the insulating layer between the two metal plates is
some thousands of Angstroms thick. Therefore, the size of a capacitor fabricated
with metal plates (i.e. metal1/metal2) is nearly 50 times larger than a poly1/poly2
capacitor having the same capacitance.
Moreover, the quality of the insulator is much different in the two cases. The
gate oxide is the best possible solution offered by the present technology, since it
has been studied and refined to fabricate all the transistors. Generally, the inter-
mediate dielectric of the metal1/metal2 capacitor does not have such a high
qua ity1.

4.3 Integrated Resistors

The available resistors are all those that can be fabricated with the various layers
produced by the technological process. In Table 4.1, the available layers are sum-
marized with the value of resistance and its variation for a typical 0.35 Pm CMOS
process.
It is common practice to calculate the value of an integrated resistor in squares
(indicated with the symbol ). In fact, the layout is a top view in which only the
sides of the rectangles are dimensioned, whereas the depth is fixed and defined by
the process. Therefore, we typically refer to the sheet resistance. Once the sheet
resistance is known, we can obtain resistors of the required value by placing one
or more squares (or fractions of squares) in series.

Table 4.1. Sheet resistence of different layers

Layer Sheet Resistance [/]
+
n (active area) 50 60
n-well 600 1200
Poly2 with silicide 57
Poly2 without silicide 50 100
Metal1 0.08
Metal2 0.04

1
By the way, it is worth telling this story. The authors participated in the design of a device
that included an A/D converter realized with metal1/metal2 capacitors. Once the devices
were delivered, many of them were returned by the customers since they did not work
properly and were considered as failures. After further tests, many of them resulted to
be good either immediately or after a night in the oven. The problem was due to the mate-
rial used to planarize the dielectric layer between the metal plates. Such material absorbed
humidity, modifying the value of capacitance due to the ions present in the water. The
subsequent heating removed the charge and the devices worked fine.