I NV E N TIV E

Cadence CPF
Methodology Guide
Version 1.1
 2007-2009 Cadence Design Systems, Inc. All rights reserved worldwide.
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2 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Introduction

The CPF Methodology Guide is

An introduction to low power design and concepts
CPF creation flow for the most popular Low Power architectures
Description of the tool flow to support those architectures
CPF and RTL coding style guidelines to help enable LP design
Tips and techniques to help in the Cadence Low Power solution
Including a known problem and solution section

It is meant to be a resource to improve the first pass

success at writing CPF and using the Cadence design
flow
It is not a replacement for detailed tool training nor is it meant to
cover every feature of every CPF command.

3 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Notes on this Document

This document is based on CPF 1.1

This document is available as both a PowerPoint slide
show and a PDF
Navigating the document
The document contains numerous hyper links to help navigate
There are normal links indicated by underlined title
Blocks in a block diagram often include links as well
The in the top-right corner will pop up a level in the
document hierarchy
The in a power point presentation will jump into a custom
show that will provide additional detail for a topic.
Note: when finished with a topic the esc key will return
back to the main presentation
Note: This button has no effect in the PDF version.

4 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Table Of Contents

Introduction to Low Power Design + LP techniques

Low Power Design and Verification Flows

Low Power Design Guidelines

Tips and special Topics

Known Problem and Solutions

Please refer to Cadence Low Power Flow KPNS.ppt
What's New

5 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Introduction
Low Power Basics
What is CPF?
What are the common low power techniques and how do they
compare?
Power Techniques
Detailed discussion on each technique, how to write the CPF, and
how they impact the verification and implementation flows.
Power Shutoff (PSO)
Multiple Voltage Supplies (MSV)
Standby Mode
Dynamic Voltage And Frequency Scaling (DVFS)

6 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Cadence Low Power Solution
Chip Estimation
Verification Planning
Cadence Low Power Solution CtoSilicon
Chip Planning &
Creating CPF with CLP GUI
Architectural Exploration CPF checking and validation
Power Intent
Creation & Checking Low Power simulation and emulation
LP Assertions and coverage
Emulation
LP Functional Verification
Synthesis and optimization
Frontend Design LP DFT
and Optimization Power analysis
Power exploration
Closed Loop Verification
Closed loop design and verification
Digital Implementation Low Power design Checks
Low Power equivalency checking

Power verification & Signoff

Physical design considerations
Tips and recommendations
Click on an oval to jump to that section

7 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Flow Topics

Hierarchical Design flow

Macro Modeling

Domain Mapping

IP Reuse Example

Naming Style Consistency

Name Mapping Flow

8 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Guidelines

CPF coding Style

TCL Tips

RTL Coding Style

CPF Language Details

9 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Tips and Techniques
How to model Hard macro with power intent
Macro Modeling ( details in macro modeling section)
I/O pads
Voltage_regulator
Level Shifters and Combination Isolation/level shifting cells
Roms, Flash Memory (details in RTL coding style section)

What are secondary domains (details in CPF topics)

How do avoid rush current due to power control logic
How do I design reusable Power aware IP blocks (details in IP reuse section)

Handling designs with Instantiated LP cells

Understanding Isolation on Constants and Tie Cells
Conformal LP Tips

CPF Support Matrix

Table with each CPF features, tool, support status (with tool version)

10 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Introduction to Low Power

Click here to return to table of Contents

11 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Introduction
Low Power Basics
What is CPF?
What are the common low power techniques and how do they
compare?
Power Techniques
Detailed discussion on each technique, how to write the CPF, and
how they impact the verification and implementation flows.
Power Shutoff (PSO)
Multiple Voltage Supplies (MSV)
Standby Mode
Dynamic Voltage And Frequency Scaling (DVFS)

12 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Common Power Format (CPF)
Common Power Format = Single specification of power intent
used throughout design, verification, and implementation
HDL Language neutral
ASCII File that captures:
Design intent Technology information
Power domain
Level shifter cells
Logical: hierarchical modules as
domain members Isolation cells
Physical: power/ground nets State-retention cells
and connectivity
Analysis view: timing library Switch cells
sets for power domains Always-on cells
Power Logic
Level Shifter Logic
Isolation Logic
State-Retention logic
Switch Logic & Control Signals
Power mode
Mode and transitions

13 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Design, Verification, and Implementation with
Power Permeating Throughout
Specification
Quick architectural exploration

Re-use pre- Function, Timing, Power Functionally verify

Instantiate single verified IP advanced power
RTL with different
power profiles
? implementation
techniques
Design Iterate RTLRTL
+ CPF Iterate
Verification
b
Constraint Coding Formal

Testbench Automation
Equivalence Checking

Verification Coverage
Generation Analysis

Constraint Validation
Synthesis Structural
& Func Checks

Design for Test Simulation

Acceleration
SVP & Emulation

Constraints CPF Netlist Hand off to drive

implementation
Golden specification Implementation
eliminates Chip Integration
LEC/CLP
Constraint Validation

assumptions and Prototyping Automatic partitioning of

DFT
miscommunications power domains
Physical Synthesis

Analysis
LVS/DRC/Ext

Automatic scheduling of
Single power Routing
ATPG

test modes
specification used from Sign-off
specification to GDSII
14 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems,
GDSII Inc. All rights reserved
 Common Power Format (CPF)
Multiple Contributors
Architect specifies initial CPF to describe system behavior and modes
Implementation engineer provides technology information
RTL designer provides detailed level CPF
Verification engineer updates based on simulation results and requirements

TIP : Keep the CPF under revision control by the technical lead of the
project.
We have seen projects where there are multiple/contradicting CPFs

CPF is a single source for all portions of the flow

But not all commands are recognized by all tools
Each tool in the flow supports the set of CPF commands relevant to that tool
define_library_set specifies the timing libraries (.lib files) to be used in
synthesis and physical design is not recognized by the simulator and is
ignored during simulation
Create_assertion_control is a for verification and is ignored by synthesis and
placement.

15 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 What CPF is not

CPF is not to:

Extensions to
Synthesis/Timing Libraries
SDC
Verilog
System Verilog
Pragmas added to RTL
Tools specific script or workarounds

16 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF Reference Material

Common Power Format User Guide, Version 1.1

Common Power Format Language Reference, Version 1.1
Low Power Simulation Guide
Low Power in RTL Compiler
Encounter Common Power Format Migration for Low
Power Commands
Whats new in Common Power Format, Version 1.1

17 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Introduction
Low Power Basics
What is CPF?
What are the common low power techniques and how do they
compare?
Power Techniques
Detailed discussion on each technique, how to write the CPF, and
how they impact the verification and implementation flows.
Power Shutoff (PSO)
Multiple Voltage Supplies (MSV)
Standby Mode
Dynamic Voltage And Frequency Scaling (DVFS)

18 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 What are the common low power techniques?
DVFS
The CPU can Power Standby
Reduce voltage and When not being used
Frequency when the memory can go in
running lower CPU Mem a standby or very low
performance tasks voltage mode
1.1V/0.9V 1.1V/Standby

MSV
DVFS & Power shutoff
The Audio processor Audio When not in use the
runs at lower clock
0.9V GPU graphics engine can be
frequency so can use 1.1V/0.9V/off
a lower voltage turned off. For high
USB performance ops it can
0.9V/off also take on the high
voltage.
Power shutoff
When no device is
plugged in, the USB can
complete power off

19 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Common Low Power Architectures (MSV)
Multiple Supply Voltages
Multiple Supply Voltages
PD_v13
1.3V
PD_v11
Power Shutoff 1.1V
PD_v09
0.9V
Standby/Sleep Mode
Multiple Supply Voltages
- Each domain gets the lowest voltage that
Dynamic Voltage and meets performance requirements
- Level Shifting may be required between
Frequency Scaling domains
Summary
Leakage Power Savings : Med
Dynamic Power Savings : Med
Verification Complexity : Med
Implementation Complexity : Med

20 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Common Low Power Architectures (PSO)
V1.1 Power Shutoff
Multiple Supply Voltages Switch Shutoff

PCM
Save

State Ret

Power Shutoff PD_PSO Isolate

1.1V/Off

Standby/Sleep Mode
Power Shutoff (PSO)
- Turn off power supply via a physical switch
Dynamic Voltage and - Isolation to protect downstream logic
- State retention to save state (optional)
Frequency Scaling
Summary
Leakage Power Savings : High
Dynamic Power Savings : High *
Verification Complexity : Med
Implementation Complexity : Med
*similar dynamic savings from clock gating

21 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Common Low Power Architectures (Standby)
Standby Mode
Multiple Supply Voltages

PCM
Sel1.1V V1.1 or V0.7
Sel0.7V VR

Power Shutoff PD_STBY

0.7/1.1V
Standby/Sleep Mode
Standby mode
- Normal operation at full voltage
Dynamic Voltage and - Standby reduces voltage to minimum
required to maintain state
Frequency Scaling - Any change of input corrupts state
- Need to isolate or gate inputs
Summary
Leakage Power Savings : Med
Dynamic Power Savings : High
Verification Complexity : Med
Implementation Complexity : Med
22 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Common Low Power Architectures (DVFS)
Dynamic Voltage & Frequency Scaling
Multiple Supply Voltages Cntl
Sel1.1V

PCM
V1.1 or V0.9
Sel0.9V VR

Power Shutoff Clk PD_DVFS

HW VCO
0.9/1.1V
Monitor
Standby/Sleep Mode
Dynamic Voltage & Frequency Scaling
- Each domain gets the lowest voltage and
Dynamic Voltage and frequency that meets performance
- Voltage regulator to control voltage
Frequency Scaling - Frequency generator to get target freq
Summary
Leakage Power Savings : Med
Dynamic Power Savings : Med
Verification Complexity : High
Implementation Complexity : High

23 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Click to return to Main Window

24 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Introduction
Low Power Basics
What is CPF?
What are the common low power techniques and how do they
compare?
Power Techniques
Detailed discussion on each technique, how to write the CPF, and
how they impact the verification and implementation flows.
Power Shutoff (PSO)
Multiple Voltage Supplies (MSV)
Standby Mode
Dynamic Voltage And Frequency Scaling (DVFS)

25 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Introduction to Power Shutoff
V1.1 Power Shutoff
How Does Power shutoff Switch Shutoff
work?

PCM
Save

What are the components of a State Ret

power shutoff design PD_PSO Isolate

How is power shutoff 1.1V/Off

controlled?
How to restore the state after
power shutoff
Power Shutoff (PSO)
- Turn off power supply via a physical
How do I define the Power switch
intent for power shutoff? - Isolation to protect downstream logic
- State retention to save state
Summary
How does my design flow Leakage Power Savings : High
Dynamic Power Savings : High*
change for Power shutoff? Verification Complexity : Med
Implementation Complexity : Med
*similar dynamic savings from clock gating
26 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Components of Power shutoff Power
Switch
Power Domains
Define the collection of instances that have the common Power
power architecture
The logic that will be powered off
Control
Power Switch
The physical switch that disconnects power for the domain
Switch can be internal to the device or external Power Shutoff V1.1
Power Shutoff Control (shutoff_condition)
Control signal that determines when the power switch is on/off Switch Shutoff

PCM
Isolation for Power Shutoff Save
Isolation cells protect the interfaces between domains
Ensures a stable value across interface during power shutoff State Ret
State Retention Isolate
PD_PSO

PD_ON
State retention is used to retain some or all of a domains
state during power shutoff 1.1V/Off
There are a number of retention policies
Specialized state retention cells with a small latch to retain the
state when power is off
Saving state to a memory
Power Control Sequence
The sequence of events that is required to power on or
power off a domain Power
Ex: Isolate->Save->Power shutoff -> Power Up->restore->
Remove Isolation domain

State Isolation
Retention

27 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Shutoff Sequence
V1.1 Power Shutoff
Shutoff
Power Off Switch

PCM
Save
Gate clocks before PSO
Isolate the paths from the State Ret
power shutoff domain PD_PSO Isolate
Save the state of any 1.1V/Off
critical registers
Regs
(optional)
Power shutoff

Power On
Power up switch
Apply any Async resets
Restore the critical state
elements
Remove Isolation
Remove Clock Gating

28 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Introduction to Power Shutoff
V1.1 Power Shutoff
How Does Power shutoff Switch Shutoff
work?

PCM
Save

What are the components of a State Ret

power shutoff design PD_PSO Isolate

How is power shutoff 1.1V/Off

controlled?
How to restore the state after
power shutoff
Power Shutoff (PSO)
- Turn off power supply via a physical
How do I define the Power switch
intent for power shutoff? - Isolation to protect downstream logic
- State retention to save state
Summary
How does my design flow Leakage Power Savings : High
Dynamic Power Savings : High
change for Power shutoff? Verification Complexity : Med
Implementation Complexity : Med

29 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Shutoff Specification Flow

Identify Power domains

Define Power Shutoff Control

Define Isolation Requirements

Define State Restoration Design Step

Define Modes of Operation

Verification & Exploration

Define Technology Info

Golden CPF
Update CPF for Synth
Front End Design Flow
Synthesis, LP Design &
Equiv checking
Define operating corners

Power & Ground Switch +Network

Updates for Phys impl

Physical Implementation
& Signoff Flow
30 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 PSO Understanding Initial Power intent
How to determine which groups of
logic should be power shutoff
Identify Power domains How to define PSO domain in CPF
Define voltage transition times

Define Power Shutoff Control How to specify control of power

shutoff
Define voltages used in the design

Define Isolation Requirements What is isolation

Common styles
Guidelines for specifying

Define State Restoration State Restoration Styles

Guidelines for State Retention

Define Modes of Operation How to define the power shutoff

control
How to define valid power
Note: The block diagram links on this page modes/configurations for the
only work in PowerPoint and not in the PDF

31 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 PSO CPF For Synthesis and Implementation
How to generate Technology data

Define Technology Info

Defines libraries, LP Cells,
voltage levels, etc

Update_*_rules Update rules for synthesis+P&R

Update_power_mode Add SDC + switching activity

Define operating corners and Data for Multi-mode/Multi-

analysis views Corner optimizations in P&R

Power & Ground Switch +Network How to specify and connect the
power and ground network
Switches, special cells, etc
Note: The links on this page only work in PowerPoint
and not in the PDF
32 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Introduction to Power Shutoff
V1.1 Power Shutoff
How Does Power shutoff Switch Shutoff
work?

PCM
Save

What are the components of a State Ret

power shutoff design PD_PSO Isolate

How is power shutoff 1.1V/Off

controlled?
How to restore the state after
power shutoff
Power Shutoff (PSO)
- Turn off power supply via a physical
How do I define the Power switch
intent for power shutoff? - Isolation to protect downstream logic
- State retention to save state
Summary
How does my design flow Leakage Power Savings : High
Dynamic Power Savings : High
change for Power shutoff? Verification Complexity : Med
Implementation Complexity : Med

33 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Shutoff Design Flow

Low Power Design flow

General description of the low power design and verification flow

Power Shutoff Specific flow

Evaluating when Power shutoff will be useful
Simulating Power Shutoff

34 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Evaluating Power Shutoff

Can the block be disabled during specific modes of operation

How long can it be disabled
How much power is saved by powering off
Need to factor in power consumed by the shutdown and power up process

System Performance Issues

What is the performance impact due to time it takes to power on/off
Consider physical aspects to powering up and down combined can typically
take on the order of us to ms, plus overhead of saving and restoring state
registers
Is it possible to wake up fast enough to respond to external triggers?

What is the impact of power shutoff

Impact on operation performance and design and verification flow
Overhead of power switches and routing resources
Area, timing and power due to state retention and isolation

35 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Defining what goes into a domain (PSO)

Power Domains define a set of instances that share a common power architecture
Define the set of hierarchical instances and macro instances that are connected to the same
power sources
Created with create_power_domain
In CPF, most of the power and ground connectivity is done via power domain definitions.
No need to directly connect power nets in most cases
Domains include
Module instances
Instantiated cells
Macro Models cells that have a macro model
Blackboxes leaf level cells with no function
I/O Cells marked as is_pad
Boundary Ports
Power Control signals
Power shutoff conditions
Guidelines for defining power domains

# Command: Create_power_domain
# Basic Power shutoff definition
create_power_domain -name PD_v11 -default
create_power_domain -name PD_PSO -instances {inst_A} shutoff_condition {pcm/pse}

36 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Guidelines for defining Power Domains
Power domains typically follow logic hierarchy
Common to group siblings in a hierarchy tree
CPF supports grouping of nodes from different hierarchy trees
Physical hierarchy
Power domains often relate to physical floorplan regions/fences
In some cases, may be split into smaller regions for floorplanning
Make domains reasonable sized
A lot of small domains can make the physical implementation more difficult
There is overhead associated with each domain (power and ground routing,
level shifting/isolation between domains, etc)
Minimize the number of unique voltage levels
While the optimum configuration may be one domain 0.95V and another at
0.93V, it doesnt make sense at a physical implementation level
Typically we see differences in the range 150-200 mv
Instance list specification
The instance list is hierarchical, an instance inherits its parents domain setting
Common to use wildcards at leaf level : A/B/C/MEM_*
Note: Click here for restrictions on using wildcards

37 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Shutoff

Power Shutoff Types and Control

Power Modes and Mode Transitions

Isolation Requirements

State Retention and Restoration

Power Switch Network Definition

Example

38 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Shutoff Control Vdd

Power Control is specified primarily with -

shutoff_expression of
create_power_domain
Unswitched*
Power Domain Types
Un-switched
The domain is always on or the power is Vdd_base
controlled and switched outside of the design
(testbench CPF can describe this for functional
verification)
create_power_domain name PD_unsw
enable
instances A
Vdd
Internally switchable
The power switch and control will be internal to
the design
create_power_domain name PD_PSO
shutoff_condition pcm/pso instances B Internally switchable*

Internally Controlled, externally switchable Vdd_base

The power switch is outside of this design,
either at the board level, or outside this IP block
The control signal is generated or at least
visible in the design (used for simulation, and Vdd
checking) enable
create_power_domain name PD_EXT
shutoff_condition pcm/pso_ext instances
C externally_controlled_shutoff

On Chip Controlled/Externally Switchable*

Note: Anything outside of box is not visible inside the block

39 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 PSO Guidelines on Power Control

Control
For front end design and simulation
Control is specified with the shutoff expression on create_power_domain
Ex: create_power_domain name PD_PSO shutoff_expression pso_en
For physical implementation, the create_power_switch rule is used
Power switch rules provides detailed specification of actual power switch
Click here for an example:
Conformal LP checking
Checks that the switch enable is the inversion of the shutoff condition
Guidelines
Avoid complex logical expression in shutoff condition
To control rush current, multiple power control pins that are delayed from each
other are often used. (example CPF)
The Shutoff condition of the power domain, and the switch enable are typically
inversions of each other.
In some cases, this relationship does not exist typically due to having multiple parallel
switches to balance rush current
In this case, it is up to the user to ensure consistency between these signals
Simulation is required to verify the functionality of the shutoff expressions

40 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Hierarchical Power Control

Power domains can have nested VDD_2

power control PD_TOP
In the diagram, the PD_PSO PSE_2
domain is powered off based on
its control (PSE_1) and whenever VDD_1
PD_MID is powered off.(PSE_2
PD_MID

Example PSE_1
Create_power_domain name PD_MID
VDD_PSO
shutoff_condition PSE_2
base_domains PD_TOP
instances .
Create_power_domain name PD_PSO PD_PSO
shutoff_condition PSE_1
base_domains PD_MID
instances .

41 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Shutoff

Power Shutoff Types and Control

Power Modes and Mode Transitions

Isolation Requirements

State Retention and Restoration

Power Switch Network Definition

Example

42 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Modes (PSO)
Power modes define the set of valid voltage
configurations of all the domains in the design.
PD1 PD2 PD3
Modes are defined as a list of MA 1.1V off 1.1V
PowerDomain@nominal_condition
Where a nominal condition defines the state, voltage MB 1.1V off off
and libraries to use:
Create_nominal_condition name off state off voltage MC 1.1V 1.1V off
0.0
Click here to learn about nominal Conditions

How are power modes used? create_power_mode name MA domain_conditions

{PD1@v11 PD2@off PD3@v11}
Simulation create_power_mode name MB domain_conditions
Determine the voltage and state of domains {PD1@v11 PD2@off PD3@off}
Learn about domain States create_power_mode name MC domain_conditions
{PD1@v11 PD2@v11 PD3@off}
Coverage metrics to ensure all valid modes are entered
during simulation
Error checking on illegal modes and transitions
Used to check completeness of isolation rules
RTL-Compiler, SOCE and CLP
Self-document the valid power states for the design.

43 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Guidelines on Power Modes

Verification flows can use power mode to develop power

aware testbenches
Coverage, assertions, and even generation of stimuli can use
power modes
Verification Planning with power modes is critical to ensure
verification closure
Use create_mode_transitions
Hierarchical power modes
Simplify Mode specification
Help with IP reuse

44 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Tracking Mode Transitions in Simulation (PSO)
Via Power Shutoff conditions
The simulator monitors the power shutoff conditions for all domains
The shutoff conditions signals the start of a domain transition
When all domains have finished transitioning, the simulator recalculates the
power mode
An error is issued if the mode has not been defined with a create_power_mode
Via Mode Transitions
The create_power_mode_transition command is used to define the legal set of
mode transitions
It can also specify a start_condition that can be used to initiate a change in
power mode.
Ex: create_mode_transition name T1 from M1 to M2 start_condition S1
When S1 is true and the current mode is M1, then simulator expects to see a transition
to M2
It will produce an error if any other transitions occur
Mode Transitions Provide
Additional coverage and checking for a design
Mechanism to control the power mode before all the detail control signals have
been fully defined.

45 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Create_mode_transitions
Create_mode_transition can be used to
define the legal set of transitions
between power modes
MA
Mode Transition Provide:
Coverage collection can verify that all
possible transitions have occurred
Error checking to ensure legal transition MC MB
and sequences of transitions
In the example, a transition from MA to MB
would flag an error
Prevents transient mode coverage
Different transition times on each domain
can make it appear that more modes
where executed. create_mode_transition from MA to MB start_condition mab
create_mode_transition from MB to MC start_condition mbc
Control of power mode transitions create_mode_transition from MCto MA start_condition mca
The start_condition defines when the create_mode_transition from MCto MB start_condition mcb
domain will start to transition
The end of the transition is one of:
All power domains have finished
their voltage transition
-end_condition has been triggered
Typically these are used mutually
exclusively.

46 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Create_mode_transitions - Notes

Controlling the transition

Define that there is a valid path between to modes
Define a start_condition that triggers the mode
transitions
Notes
If no mode transitions are defined for a design, then ALL
mode transitions are considered legal
If one or more mode transitions are defined, any
unspecified mode transitions are considered illegal
The Start conditions of mode transitions with the same
-from mode need to be unique
Otherwise tool can not determine which mode to transition
to, the following would be illegal:
Create_mode_transition from MA to MB start_condition C
Create_mode_transition from MA to MC start_condition C

47 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Shutoff

Power Shutoff Types and Control

Power Modes and Mode Transitions

Isolation Requirements

State Retention and Restoration

Power Switch Network Definition

Example

48 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Isolation for Power Shutoff

What is isolation
What are the Common Isolation Styles
Styles and examples
Recommendations and Guidelines for Isolation
Isolation on feedthrough nets

49 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Isolation For Power Shutoff
Isolation For Power Shutoff
Method of protecting logic downstream from a power shutoff
A power shutoff domains outputs are floating during PSO
Isolation ensures a valid voltage and value at the outputs
Reduce power consumption at during power up/down

Isolation Specification includes

isolation_value
Defines the value to drive on the net when the power domain is shutoff
(high, low, hold, tristate)
Isolation_condition
Control signal/expression to enabled/disabled isolation
Isolation_location
where in the physical hierarchy the isolation is placed
Typically the default is used, which is in the to domain
See the create_isolation_rule documentation for additional
options/details

50 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Common Isolation Styles
Create_isolation_rule name ISO1 from PDA

Output Isolation
Output Isolation
a_out
Output isolation is very common PDA PDB
Typically used when the output value is c_out
the same regardless of destination
A bus interface for instance
Not all outputs have to isolate the same
way PDC
Can be specified at the chip level or Iso_en
block level
CPF allows a lot of flexibility
Specify unique isolation for each from/to
pair of signals (Cout->PDB, Cout-PDC)
Input Isolation
Input Isolation: PDA
a_out
PDB
Isolation is specific at the destination
Isolation from c_out to PDC c_out
Common in IP blocks
The IP block specifies what it expects
the inputs to be if their power is shutoff
PDC
Using Default isolation_condition
allows isolation to be defined even if the
isolation condition is not known to the Iso_en
IP(see next page)
Create_isolation_rule name ISO2 to PDC

51 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Isolation Examples and Recommendations
Recommended Isolation Technique
Description
Define a general isolation rule
Use from, -to, or combination of from and to
-from and to together provides more detailed control over the isolation behavior
Can help prevent un-necessary isolation
Set isolation_type to most common value (typically low or high)
Use exclude to exclude pins that isolate to the non-default value
Define a specific rule for the non-default pins
Pros:
Handles most common isolation cases where majority of pins can be isolated
the same way
Explicit list of less common isolation value
More concise and maintainable than listing explicitly listing each pin
Isolation is well defined and will work in all CPF based flows
Cons:
Missing pins automatically added using first isolation rule
Can be difficult to detect if this was an incorrect setting for that pin
More verbose than some techniques
#Block PDA.cpf
set hi_pins {PDB/a_in}
create_isolation_rule name ISO_LOW to PDB from PDA exclude $hi_pins
isolation_type low isolation_condition iso_en
create_isolation_rule name ISO_HIGH to PDB from PDA pins $hi_pins
isolation_type high isolation_condition iso_en

52 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Isolation Examples and Recommendations
Isolation with Explicit pin definitions
Specification
For each isolation_type
Create an isolation rule for that type listing out exactly which pins should be
isolated
Pros:
Explicitly setting the pins ensures that consistent operation in all CPF enabled tools
Missing isolation ports are easily flagged by CLP
If a new port is added the user actively decides what isolation type it should be
In other techniques the port will be added to the default case, which may or may not be the
correct isolation_type for this port
Cons:
More verbose specification and more maintenance
Pin list needs to be manually maintained by the user
List of pins could be hundreds of items
Isolation rules may not work when pins are introduction mid flow like during DFT

#Block PDA.cpf
set hi_pins {PDB/a_out}
Set low_pins {PDB/c_out
create_isolation_rule name ISO_LOW from PDB pins low_pins
isolation_type low isolation_condition iso_en
create_isolation_rule name ISO_HIGH from PDB pins $hi_pins
isolation_type high isolation_condition iso_en

53 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Isolation Examples and Recommendations
Isolation for IP Blocks
Input isolation in hierarchical CPF
Specification
Lower level block specifies input isolation
Without specifying the isolation_condition
Top level Block instantiates the block cpf
Defines its power domain with Default isolation_condition
Pros:
Block can be reused in power aware or non poweraware instances
The isolation rule is ignored if the driving domain is not a power shutoff
The IP block does not need to know the environment it is instantiated in
Facilitates design reuse
Top level CPF creator does not need to know as much about the block
Cons:
Relies on tools to resolve any conflicts with isolation
Top block may have an isolation from its outputs that conflicts
CLP rule checking can verify

#Block PDC.pf
#an isolation rule with no isolation_condition will pick up the #default isolation condition from the
driving domain
create_isolation_rule name ISO1 to PDC pins {b_out} isolation_type low
create_isolation_rule name ISO1 to PDC pins {a_out} isolation_type high
#Block TOP.cpf
Create_power_domain name PDA -shutoff_expression pse
default_isolation_condition iso_en
Include block_PDC.cpf

54 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Isolation Guidelines
Common Options and recommended settings
Using naming styles to simplify isolation specification
A common naming style is to use _n to indicate a low active signal
create_isolation_rule from PDA pins {a/b/*_n} isolation_type high

Isolation_value
High and low isolation are the most common in design
Isolate to inactive value of signal
hold has specific uses, but can increase verification space and is more expense in area and power
Verification would need to prove the circuit worked when the isolation latch was 1 and when it was 0.
tristate isolation is not currently supported by all tools in the flow

Isolation_location (set with update_isolation_rule)

Most users do not need to set the location
The default isolation location is in the to domain
This allows a simple isolation cell connected to the destinations power supply
In some cases, the from domain is used
Typically used when an IP block wants to have a fully contained LP intent
Usually requires an isolation cell with 2 sets of power pins
Larger, slower cells
-within_hierarchy allows the isolation to be placed based in the specified hierarchy. This often is used to
allow the isolation to be placed at the top-level to give place and route more flexibility in placement

NOTE: IES does not support the isolation_location directives

This is still functionally equivalent but may impact hierarchical verification as the isolation cell may be at a different level in
the hierarchy

55 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Isolation Guidelines
-pins option
Using pins is a very robust method of isolation
Missing isolation is easily detected in CLP and in simvision waveforms
Other techniques rely on a default isolation value can inadvertently assign the wrong
isolation type, very difficult to debug
This is a classic trade off between ease of specification and ease of detecting an issue
If multiple rules are used make sure you understand
Rule Precedence in CPF
Isolation rules can be optimized away
if the driver is not a power shutoff domain
If the driver and all destinations are in the same power domain
Rule precedence
Synthesis optimizations
Pushing constants across boundaries
Dead code removal
Note: Synthesis and Simulation have different abilities in this area, so there can
be differences.
These differences are not functional differences as the rule will only be optimized away
only if it is non-functional.

56 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Isolation on Feed through Paths
Feed throughs should
not be corrupted
It is common for a net to pass
through a power shutoff domain

These nets are not part of that

domain, and will not be corrupted
when the domain powers off
PSO
Power aware implementation tools
like RTL compiler and EDI will
ensure that any buffers inserted will
be placed in proper domain or be
always on buffers

Note: Any hand instantiated cells will

be corrupted
Hand Instantiated buffers on feed
If buffers/invertors were inserted by through will be corrupted unless they
the user the user must ensure that are always on.
they remain active during the PSO

57 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Assign in RTL
Handing instantiated buffers
PDA PDC PDB
When Hand instantiated buffers are inserted, the simulation
view of the design and the implementation view can differ
if a regular buffer is used then the tools will need to insert
isolation on its output
The RTL would not have this isolation and would simulate
differently
Solutions
Allow the tools to do all buffer insertion
Insert AlwaysOnBuffers when inserting into a power shutoff
domain
For a design that needs to inserts ISO ISOC
Insert a buf explicitly in RTL before RTL simulation
assign a =rare
This is a very b; case; modifying the RTL to insert buffers is After Modification by designers
generally not recommended

Hand instantiated ISO

create_nominal_condition -name vdd_12 -voltage 1.2 with BUF insertion
create_nominal_condition -name vdd_off -voltage 0.0
PDA PDC PDB
create_power_mode -name PM1 -domain_conditions { \
DEFAULT@vdd_12 PDA@vdd_12 PDB@vdd_12 PDC@vdd_12 \
} -default

create_power_mode -name PM2 -domain_conditions { \

DEFAULT@vdd_12 PDA@vdd_12 PDB@vdd_12 PDC@vdd_off \
}

create_isolation_rule \
-name IS_PDC2PDB \
-from PDC -to PDB \
-isolation_output low \
-isolation_condition !ISOC

58 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved ISOC
 Power Shutoff

Power Shutoff Types and Control

Power Modes and Mode Transitions

Isolation Requirements

State Retention and Restoration

Power Switch Network Definition

Example

59 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 State Retention and Restoration

State Restoration Styles

Guidelines and recommendations

60 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power up and State restoration

When a design is powered off, all the internal logic becomes floating and
with indeterminate values
In simulation, this is modeled by forces xs on the logic
At power up, the design needs to be placed into a valid state

There are several methods of doing this

Power on Reset
State Retention strategies
Partitioning a block into always on and power shutoff regions
State retention and power gating cells
On critical control and configuration logic
On most/all registers
Reading/Writing critical registers to a on memory or register file
Standby Mode

Guidelines on State Retention

General guidelines
Guidelines on create_state_retention_rules
Important RTL Simulation Information

61 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 State Restoration
Power On Reset
Power on Reset is highly recommended
Ensures that all registers get to a known good state
Typically reuses the blocks initial power on reset
Easy to implement and specify
Can be used with other State retention strategies
Used in many cases where there is no need to maintain state between
uses, like a floating point unit, where one computation is unrelated to
the next.
Disadvantages
Used by itself, no memory of previous state or configuration is retained
Latency issues:
If the device needs to be configured before used, this entire configuration
process needs to be redone
Could be very time consuming which adds latency to the overall power
sequence
Places an additional requirement on the HW/software, as it must know to
issue the reset on power up
Where latency is an issue, most designs will include a state retention
strategy
62 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 State Retention Strategies
Partitioning into PSO and non-PSO
Instead of the entire block being power shutoff, a
portion of the block is keep always on
Useful if the logic is well partitioned already and Bus I/F Config Reg
only a small % of logic is needed to be on
Some pipelined designs and I/O blocks are naturally
partitioned this way PSO
This technique is useful when initially developing a
design, but can be difficult to implement on existing
blocks
Pro:
Maintain block configuration throughout power
shutoff
May already be required to keep bus interface alive BlkA BlkB
during shutoff
Conceptually simple and easily verified
Existing power on Reset used for the PSO section
Con:
Requires two domains
Often the always on logic is merged into an existing
higher level domain
Always on logic is still consuming power during
shutoff
Standby mode could improve
May complicate physical design and power planning
May be difficult to implement on existing IP
63 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 State Retention Strategies
State Retention Cells
Define a subset of the registers in the design to be state VDD
retention cells
These cells have a small, power efficient latch that is tied to a PwR
secondary power supply Switch
The latch is loaded prior to power shutoff
After power up, the latched value is transferred to the main flop
Use create_state_retention_rule to define VDD VRET
Usage Modes D Q
Selective (recommended) SRPG
A small % of flops are designated as state retention Clk Cell
Maximum power savings as only small # of components are active Retention
during PSO Ret Latch
Challenge: its difficult to determine the minimum set of flops to retain
Verification of correct power up can be difficult
Global VSS
Set all or most of the flops in a domain as state retention
Easy to specify, but expensive in terms of hardware and power
consumption
Each SR cell has extra logic, some of which is always on
Secondary power grid needs to be sized for larger # of items
(more routing resources required)
Verification is easier as the design state is fully restored on power up
Consider using Standby mode if this option is appealing

64 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 State Retention Control

There is a wide variety of State retention control options

The control depends on design decisions and vendor requirements
There is no right answer to which type of control is best
Restore Edge single control signal
Most common case
Saves the data on the rising edge of RET, and restores it on the falling edge.
Create_state_retention_rule name SR1 restore_edge RET instances A/b/cntrl*
Restore is keep active during state retention (sometimes called RETAIN signal)
Save and Restore Level
Independent level sensitive control for save and restore
Data is stored based on save_level input control
Data is restored based on restore_level
create_state_retention_rule name SR2 instances A/B/cntrl*
save_level SAVE restore_level RESTORE
Save Edge single control signal
This is not common and very vendor specific
Data is saved on rising edge of the -save_edge
Data is restored automatically on power up.
Create_state_retention_rule name SR1 save_edge SAV instances A/b/cntrl*
Typically requires a specialized cell not available in most libraries.

65 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 State Retention Strategies
Standby Mode Standby Mode

Standby Mode can be considered instead of PSO VR

Useful when large % of registers need to be retained
V1.1 or V0.7
Very fast turnaround time

Isolated or LS

Gated Inputs
Improved physical implementation flow
Requires Bias net + voltage regulator
But not power switches, secondary power and retention control PD_STBY
PSO is typically better when device can be powered off for 0.7/1.1V
long periods of time
See the table for a comparison

Criteria General SRPG Standby Mode

Leakage Power Large # of small latches active All logic is active but at a reduced voltage
Secondary power network typically with bias to further reduce leakage
power.

Dynamic Power No dynamic power No dynamic power

Area each flop is larger Input isolation
isolation cells Output Isolation or LS
Power switches Multiple voltage supplies
Secondary power grid
Flow Complexity Power switches Bias net needs to be routed and connected
Secondary power and ground
Save/restore control
Latency Save/Restore is quick but Smaller voltage transition == shorted delay
PSO cycle is long No separate save/restore
66 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 State Retention Strategies
Using external memory
Use an external memory to store the state Shut- Power
Prior to shutdown store key elements in system down Down

Isolation

Isolation
memory (on / off chip). power Block
logi
Restore the registers after power up c
Assumes an existing memory that is on while n
registers
this device is powered off
Keep-
Pro: alive
Better leakage power than other techniques power n bit
The entire block can be powered off State
Machine memory
Con:
Long latency State Retention
Additional hardware required to implement
Typically larger dynamic power during both save
and restore (especially if external memory is
used)
Assumes an existing memory to store to.
Summary
Only useful when power shutoff windows are very
long and there is a memory available that must be
on for other reason

67 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 State Retention Guidelines

Which State retention strategies are most common?

Selecting which registers should be retained
Important note on Simulation support of State retention
Common checks
Clock gating
Restore_precondition, save_precondition checks
RTL and CPF coding guidelines
Using the create_state_retention_rule CPF command

68 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 State Restoration Selection Guidelines
The state restoration process is very design specific
The most common techniques are:
Power up reset,
Power up reset with selective state retention
Use power up reset if :
If the block has no memory of previous uses
If the block is always fully re-configured between uses
Use Power up reset + selective State retention
If there is a set of well defined configuration and mode registers that need to be
maintained between each use of the block
If there are tight performance requirements for powering up
Ex: I/O channels are often configured with speed, check bits, base address, etc.
Saving this information can significantly improves latency
Saving all registers
Avoid saving all regs this expensive in terms of power, area, and routing
Typically used If the device needs to power up in exactly the same state it was in
prior to power shutoff
Like hibernate mode in a laptop
Consider Standby Mode instead of power shutoff. this has less power savings,
but better latency on power up and considerably less area and routing resources

69 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Specifying State Retention Registers
Use the CPF create_state_retention_rule command to identify registers that are
state retention
-instances : Specific registers and latches
all registers and latches in a hierarchical instance **
-domain : Specifies all registers and latches in a specific domain**
-exclude : Excludes specific registers from the general lists above
** Simulation support
IES supports the full syntax of the create_state_retention_rule
IES does not have a synthesis engine, so it has a simple view of what is considered a
register
Verilog: any verilog reg in an always @{} block
VHDL: Any VHDL signal not identified as a feedthrough or simple assign
This view can cause more logic to be retained than is intended by the user
This can lead to false positives in simulation
What works
Specify specific registers
Simple wildcards that match a good naming style
Example : -instances a/b/c/*_reg; where only signals with suffix _ref are
sequential elements
Using domain or module instances where the above definition of a register holds true
This is rare, but is sometimes true for register files, etc.
Avoid using
Very general wildcards
Module and domain instances
Please refer to the KNPS section for more details and workaround
70 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Guidelines on State Retention
Clocks should be gated prior to state retention
Ensures the saved value is a known good value
Clock gating requirements on some State retention cells
Clock intolerant State retention cells
Some library cells require a specific value on the clock line in order to
maintain the retained valued
Clock tolerant
Typically want a constant value, but it can be 0, or 1

Ensuring proper operation of State Retention Cells

State retention may place requirements on the clock and resets of the
state retention registers
CPF provides
-save_precondition and -restore_precondition options to
create_state_retention_rule for this reason
Example:
Create_state_retention_rule name SR1 restore_edge RET
-restore_precondition {clk=1b0 && reset = 1b1}
Recommend using the -lps_alt_srr flag for the most pessimistic modeling
of these requirements (corrupts the logic if the preconditions are not met).

71 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 State Retention Guidelines RTL coding

RTL coding Style

Recommend a consistent naming style for registers that should be state
retention
Blocks that are designed with power shutoff in mind can then use
simple wildcards to easily match the required registers
Block Level CPF
The block level designer is typically the most knowledgeable about
which registers would need to be state retention
The block designer can provide a CPF file that only contains the state
retention logic
CPF provides a method to specify power domain level control of state
retention, so the block designer does not need any knowledge of the power
control signals in order to specify the state retention
Alternately the user can use port mapping to pass the control signals to the
block level CPF

72 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Create_State_Retention_Rule - Guidelines
Save/restore control expressions
Use single variable or simple expressions (and, or, not) for control expressions
Use set_equivalent_pins If there is a need to stagger the signals to avoid spikes
Equivalent pin example
Expression should include only signals that directly drive the control pins of the retention
cell.
Use *_precondition to add checks for clock and reset state onto the retention cell
-save_level and restore_level
The simulator optimized the save and restore level logic to improve performance
Despite the level_sensitive designation:
save occurs at the rising edge of save
If the register changes after the rise of save_level, it will not be latched
This is typically not an issue as the clocks are gated at this time, so no change would occur.
restore occurs at the falling edge of the restore
This restore occurs later then it could, but should pose no issue to verification
Wildcards only at leaf level of hierarchy
Click here to see wildcard support information
Explicit list of state retention registers
If large % of domain is state retention, used exclude to avoid unnecessary retention logic.
State retention mapping
Allow the synthesis tools to choose proper state retention cells
CPF can specify the technology cell to use cell per rule, but generally not required.
target_type is not currently supported by any CDN tool

73 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Shutoff

Power Shutoff Types and Control

Power Modes and Mode Transitions

Isolation Requirements

State Retention and Restoration

Power Switch Network Definition

Example

74 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Switches A front end perspective
The power switches define when the power to a power
shutoff design is turned on and off
From a front end design and early power exploration
point of view this is very simple: PD_BASE
Pso_en
create_power_domain name PD_PSO VDD_PSO
-shutoff_condition pso_en
-base_domain PD_BASE
PD_PSO
When pso_en =1, the power to PD_PSO is turned off
All the logic inside PD_PSO becomes inactive
When pso_en = 0, the voltage is provided by the
PD_BASEs input voltage
PD_BASE is the base_domain for PD_PSO
PD_BASE can also be a power shutoff domain, leading to
a nested power switch
whenever PD_BASE is off PD_PSO is also off
This model is sufficient for RTL simulation and
synthesis
In physical design, actual power nets are defined and
connected
75 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Shutoff

Power Shutoff Types and Control

Power Modes and Mode Transitions

Isolation Requirements

State Retention and Restoration

Power Switch Network Definition

Example

76 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Example PSO CPF
PD1

PD1 Always on PD2

Inst_A Inst_B
Includes : The top-level of the
design, top, inst_C and
pm_inst

PD3
PD2 Power shutoff domain External
Power Switch
Inst_C
Includes: inst_A and inst_B Inst_D

PD3 Power shutoff

Pge_enable
Pse_enable
iso_enable
inst_D can be switched on
and off independently from pm_inst

inst_A and inst_B

Externally power switch
Pm_inst contains the power
control logic for the domain

77 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF Example for PSO - technology.cpf
#################################################
# Technology CPF file Contains all technology specific information
#################################################
# group libraries characterized for same operating condition
define_library_set -name set1_wc -libraries {lib1_wc lib2_wc}
define_library_set -name set1_bc -libraries {lib1_bc lib2_bc}
include library1.cpf

#################################################
# Library1.cpf Library Cell definitions
#################################################
# define the isolation cells Always_on_* options
define_isolation_cell -cells ISOLN* -enable EN -valid_location on always_on_pin EN only used in simulation
# define the always on cell
define_always_on_cell -cells "BUFGX2M BUFGX8M INVGX2M INVGX8M" for Instantiated Isolation
# define the state retention cell + Retention cells
define_state_retention_cell -cells *DRFF* -restore_function RETN
always_on_components reg
# define the power switch cells
define_power_switch_cell -cells "hd8DM hd16DM hd32DM hd64DM" \
-stage_1_enable SLEEP -type header
define_power_switch_cell -cells "hd8M hd16M hd32M hd64M" \
-stage_1_enable !SLEEP -type header

Legend RC, CLP, EDI CLP, EDI Verification

78 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 PSO CPF Top
#################################################
# Top-level CPF file: top.cpf
#################################################
set_cpf_version 1.1
set_hierarchy_separator .
# identify the design for which the CPF file is created
set_design top

#################################################
# Included technology and library definitions
#################################################
Include technology.cpf

#################################################
# Design part of the CPF
#################################################
# specify the operating voltages used in the design
create_nominal_condition -name off -voltage 0
create_nominal_condition -name on -voltage 1.1
# specify which library set to use for a specific nominal condition
update_nominal_condition -name on -library_set set1_wc

# identify portions of the design that are switched on or off simultaneously

create_power_domain -name PD1 -default
create_power_domain -name PD2 -instances {inst_A inst_B} \
-shutoff_condition {pse_enable[0]} base_domains PD1
# Domain with external control shutoff indicates the power switch is external to the chip
create_power_domain -name PD3 external_controlled_shutoff -instances inst_D \
-shutoff_condition {pse_enable[1]} base_domains PD1

Legend RC, CLP, EDI CLP, EDI Verification

79 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 PSO CPF Top Modes + Isolation + Retention
# associate the nominal conditions with the power domains
create_power_mode -name PM1 -domain_conditions {PD1@on PD2@on PD3@on} -default
create_power_mode -name PM2 -domain_conditions {PD1@on PD2@off PD3@on}
create_power_mode -name PM3 -domain_conditions {PD1@on PD2@off PD3@off}

# create rules for isolation logic insertion

create_isolation_rule -name iso1 -from PD2 \
-isolation_condition {pm_inst.ice_enable[0]}
update_isolation_rules -names iso1 -location to -cells ISOLNX2M

create_isolation_rule -name iso2 -to PD1\

-isolation_condition {pm_inst.ice_enable[1]} -isolation_output high
update_isolation_rules -names iso2 -location to -cells ISOLNX2M

# create rules for state retention insertion

create_state_retention_rule -name st1 -domain PD2 \
-restore_edge {!pm_inst.pge_enable[0]}
create_state_retention_rule -name st2 -domain PD3 \
-restore_edge {!pm_inst.pge_enable[1]}

# specify the timing constraints and activity information

update_power_mode -name PM1 -sdc_files pm1.sdc
update_power_mode -name PM2 -sdc_files pm2.sdc
update_power_mode -name PM1 -activity_file top.tcf -activity_file_weight 100

include physical_designcpf

Legend RC, CLP, EDI CLP, EDI Verification

80 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 PSO-CPF Physical Implementation: Physical_Design.cpf
Legend RC, CLP, EDI CLP, EDI Verification
# physical_design.cpf
#
#####################################################
# Additional Information for Physical Implementation
#####################################################
# declare power and ground nets
create_power_nets -nets VDD -voltage 1.1
create_power_nets -nets {VDD_SW1 VDD_SW2} -internal
create_ground_nets -nets VSS -voltage 0
# add implementation info for power domains
update_power_domain -name PD1 -primary_power_net VDD -primary_ground_net VSS
update_power_domain -name PD2 -primary_power_net VDD_SW1 -primary_ground_net VSS
update_power_domain -name PD3 -primary_power_net VDD_SW2 -primary_ground_net VSS
# create rules for power switch insertion
create_power_switch_rule -name SW1 -domain PD2 -external_power_net VDD
#Note: No power switch rule for PD3 it is an externally controlled shutoff
update_power_switch_rule -name SW1 -cells hd32M -prefix CDN_
update_power_switch_rule -name SW2 -cells hd32M -prefix CDN_
# create operating corners
create_operating_corner -name BC \
-process 1 -temperature 0 -voltage 1.21 -library_set set1_bc
create_operating_corner -name WC \
-process 1 -temperature 125 -voltage 0.99 -library_set set1_wc
# create analysis views
create_analysis_view -name AV_PM1_bc -mode PM1 -domain_corners {PD1@BC PD2@BC PD3@BC}
create_analysis_view -name AV_PM1_wv -mode PM1 -domain_corners {PD1@WC PD2@WC PD3@WC}
create_analysis_view -name AV_PM2_bc -mode PM2-domain_corners {PD1@BC PD2@BC PD3@BC}
create_analysis_view -name AV_PM2_wc -mode PM2-domain_corners {PD1@WC PD2@WC PD3@WC
create_analysis_view -name AV_PM3_bc -mode PM3 -domain_corners {PD1@BC PD2@BC PD3@BC}
create_analysis_view -name AV_PM3_wc -mode PM3 -domain_corners {PD1@WC PD2@WC PD3@WC}

# indicate when the power information for the design ends

end_design

81 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Introduction
Low Power Basics
What is CPF?
What are the common low power techniques and how do they
compare?
Power Techniques
Detailed discussion on each technique, how to write the CPF, and
how they impact the verification and implementation flows.
Power Shutoff (PSO)
Multiple Voltage Supplies (MSV)
Standby Mode
Dynamic Voltage And Frequency Scaling (DVFS)

82 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Introduction to Multiple Supply voltages
Multiple Supply Voltages
What are the components
of an MSV design PD_v13
1.3V
PD_v11
How do I define the Power 1.1V
PD_v09
intent for MSV? 0.9V

How does my design flow Multiple Supply Voltages

change for MSV? - Each domain gets the lowest voltage
that meets performance requirements
- Level Shifting may be required
between domains
Example CPF for MSV Summary
Leakage Power Savings : Med
Dynamic Power Savings : Med
Verification Complexity : Med
Implementation Complexity : Med

83 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 MSV
Multiple supply voltages are conceptually simple
The design has more than one static voltage sources
Each domain is assigned the lowest voltage that still makes
timing
Whenever a path crosses between domains of different voltages
a level shifter is required
Level Shifters
Level shifters have two voltage supplies
Source voltage on input
Destination voltage on output
The cell is designed to transfer the voltage
These are large and slow devices
Partitioning to a large number of small voltage domains can be
very expensive in hardware
LS cells have a defined range of voltage swing that they can
support

84 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Multiple Supply Voltage Specification Flow

Identify Power domains

Design Step
Define Mode of Operation

Verification & Exploration

Define Technology Libraries

Golden CPF
Define Level Shifting Requirement
Front End Design Flow
Synthesis, LP Design &
Equiv checking
Define operating corners

Updates for Phys impl

Physical Implementation
& Signoff Flow

85 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 MSV Power intent
How to determine which domains
Identify Power domains are candidates for MSV
Define which groups of logic should
be at the same voltage

Define Modes of Operation Define voltage level for each

power domain using power mode
Explore using RC-DEX
Define technology libraries
Define libraries to use for each
voltage level

Define Level Shifter Requirements

Create_level_shifter_rule

Define operating corners and

analysis views Setup Multimode/multicorner
optimizations in backend
Update level shifter location
Note: The links on this page only work in Powerpoint and not in the PDF
86 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 MSV Power Mode
Power modes define the set of valid voltage
configurations of all the domains in the design.
For a Purely MSV design, there is a single Power PD1 PD2 PD3
Mode defined.
PM 0.8V 1.0V 1.2V
Modes are defined as a list of # Create power domains
PowerDomain@nominal_condition create_power_domain -name PD1 -default
The nominal condition can be used create_power_domain -name PD2 -instances instance_B
Define voltage levels for power, ground and bias create_power_domain -name PD3 -instances instance_C

Libraries specific to those voltage

# specify the operating voltages used in the design
Operating conditions to use
create_nominal_condition -name low -voltage 0.8
Click here to learn more about nominal Conditions create_nominal_condition -name medium -voltage 1.0
create_nominal_condition -name high -voltage 1.2

How are power modes used? # associate the nominal conditions with the power domains
Used to drive and check level shifter insertion create_power_mode -name PM -domain_conditions
RTL-Compiler, SOCE and CLP {PD1@low PD2@medium PD3@high} -default
RTL-Compiler, SOCE use these for timing, synthesis
and optimization
Self-document the valid power states for the design.

87 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 How to determine candidates for MSV

Constraint analysis
Blocks with lower clock frequency
Blocks with timing slack
Often need to experiment with the design to determine the slack,
as area and power optimization tends to remove slack
Early Estimation
Chip Estimate can be used to estimate the timing and area of
blocks at different voltages.
A first pass estimate for planning purposes
When RTL is more complete
RC has DEX feature to explore different configurations of
domains to determine the optimal voltage for the domain

88 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 MSV Design Flow

Low Power Design flow

General description of the low power design and verification flow

MSV Specific flow

Verification of MSV
Since the voltage domains are static dynamic simulation is not effected by
MSV
CLP is used to verify all voltage domain crossings
Ensures proper level shifting is in place
Exhaustive proof
Implementation of MSV
Each voltage domain need power planning and routing
Level shifter insertion and connectivity
Domain aware buffer insertion
Domain aware DFT ensure scan chains have minimal domain crossings

89 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Example MSV CPF
top
Inst_C
Level Shifters
Inst_A
Inst_B
0.8V 1.0V

PD2 0.8V 1.2V

(1.0V) 1.2V
1.0V
PD3(1.2V)
PD1 (0.8V)

Domain Voltage Instances Libraries libSet

PD1 0.8V Top,Inst_A Lib1,lib2 set1

PD2 1.0V Inst_B Lib3 set2

PD3 1.2V Inst_C Lib4 set3

90 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF Example for MSV - technology.cpf
#################################################
# Technology CPF file Contains all technology specific information
#################################################
# group libraries characterized for same operating condition
define_library_set -name set1_bc -libraries {lib1_bc lib2_bc}
define_library_set -name set1_wc -libraries {lib1_wc lib2_wc}
define_library_set -name set2_bc -libraries lib3_bc
define_library_set -name set2_wc -libraries lib3_wc
define_library_set -name set3_bc -libraries lib4_bc
define_library_set -name set3_wc -libraries lib4_wc

include library1.cpf

#################################################
# Library1.cpf Library Cell definitions
#################################################
#
define_level_shifter_cell -cells LVLLHEHX* \
-input_voltage_range 0.8 -output_voltage_range 1.0 \
-output_power_pin VDD -ground GND -direction up -valid_location from
define_level_shifter_cell -cells LVLLHX* \
-input_voltage_range 0.8 -output_voltage_range 1.2 \
-output_power_pin VDD -ground GND -direction up valid_location to
define_level_shifter_cell -cells LVLLHELX* \
-input_voltage_range 1.0 -output_voltage_range 1.2 \
-output_power_pin VDD -ground GND -direction up -valid_location to

Legend RC, CLP, EDI CLP, EDI Verification

91 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 MSV CPF Top Legend RC, CLP, EDI CLP, EDI Verification

#################################################
# Top-level CPF file: top.cpf
#################################################
set_cpf_version 1.1
set_hierarchy_separator .
Include tech.cpf
# identify the design for which the CPF file is created
set_design top
# identify portions of the design that operate on the same voltage
create_power_domain -name PD1 -default
create_power_domain -name PD2 -instances instance_B
create_power_domain -name PD3 -instances instance_C

# specify the operating voltages used in the design

create_nominal_condition -name low -voltage 0.8
create_nominal_condition -name medium -voltage 1.0
create_nominal_condition -name high -voltage 1.2

# associate the nominal conditions with the power domains

create_power_mode -name PM default
-domain_conditions {PD1@low PD2@medium PD3@high} \

# specify which library set to use for a specific nominal condition

update_nominal_condition -name low -library_set set1_wc
update_nominal_condition -name medium -library_set set2_wc
update_nominal_condition -name high -library_set set3_wc
# create rules for level shifter insertion
create_level_shifter_rule -name lsr1 -from PD1 -to PD2
create_level_shifter_rule -name lsr2 -from PD2 -to PD3
create_level_shifter_rule -name lsr3 -from PD1 -to PD3

92 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 MSV-CPF Physical Implementation
Legend RC, CLP, EDI CLP, EDI Verification

# physical_design.cpf
#
#####################################################
# Additional Information for Physical Implementation
#####################################################
# declare power and ground nets
create_power_nets -nets VDD1 -voltage 0.8
create_power_nets -nets VDD2 -voltage 1.0
create_power_nets -nets VDD3 -voltage 1.2

# add implementation info for power domains

update_power_domain -name PD1 -primary_power_net VDD1
update_power_domain -name PD2 -primary_power_net VDD2
update_power_domain -name PD3 -primary_power_net VDD3
# indicate when the power information for the design ends

93 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Introduction
Low Power Basics
What is CPF?
What are the common low power techniques and how do they
compare?
Power Techniques
Detailed discussion on each technique, how to write the CPF, and
how they impact the verification and implementation flows.
Power Shutoff (PSO)
Multiple Voltage Supplies (MSV)
Standby Mode
Dynamic Voltage And Frequency Scaling (DVFS)

94 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Introduction to Standby Mode
Standby Mode
What is Standby

PCM
Sel1.1V V1.1 or V0.7
Sel0.7V VR
How do I define the Power
intent for Standby Mode? PD_STBY
0.7/1.1V

How does my design flow

change for Standby Mode? Standby mode
- Normal operation at full voltage
- Standby reduces voltage to minimum
required to maintain state
- Any change of input corrupts stat
Summary
Leakage Power Savings : Med
Dynamic Power Savings : Low
Verification Complexity : Med
Implementation Complexity : Med

95 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Standby Mode
The domain operates at two voltages
Normal voltage
Standby Voltage

At the Standby voltage

The voltage is just high enough to maintain the state of all internal logic and
sequential elements
It is too low to calculate or store any new values
Bias is usually used to further reduce the leakage power during standby
Power consumption
Dynamic power is 0, because all inputs, clocks and resets are gated
Leakage power is reduced because the voltage reduction and bias voltage

Requires
Isolation or gating of input signals to ensure stability
Isolation or level shifting of outputs to ensure valid domain crossing
Multiple voltages
Typically voltage is a single voltage rail is used for the standby domain
Voltage Selection
Most often done off chip
On chip voltage regulators are also supported by CPF

96 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Standby Flow

Going into Standby

Gate clocks
Isolate all inputs
Either isolation cells in CPF or simple gating logic outside of the standby
domain
In many cases, this may be as simple as clock gating on the domain
Isolate Outputs
If output isolation not used, then level shifters are required on outputs
See next slide for details
Transition to standby voltage

Powering up to full voltage

Transition to full voltage
Disable input && output isolation
Enable clocks

97 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Output Isolation or Level Shifting

What is needed
During standby the domain has a reduced voltage supply
The outputs of the domain are still connected to the original higher voltage
The low-high voltage crossing typically needs level shifting to operate correctly
But if the outputs are not used, a simple isolation cell could protect the interface
Isolation vs Level shifting
Isolation
Cells are smaller, faster, simpler
If placed in destination, can be simple an AND gate, no special power routing or
connections
Isolation value is statically determined in the CPF
Level Shifting
Advantage is that the outputs maintain their current value
It is design dependent as to whether this is the correct thing to do or not, in some
case isolation to inactive values is preferred
Level shifting cells are more expensive
Large, more power consumption, require second power and ground pins to
handle voltage transitions.
Recommendation
Use Isolation if it meets functional requirements

98 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Standby Design Flow

Low Power Design flow

General description of the low power design and verification flow

Standby flow
Verification of Standby
Assertions on inputs to ensure stable during standby mode
Simulation corrupts logic if inputs change in standby mode
CLP is used to verify all voltage domain crossings
Ensures proper level shifting or isolation is in place
Currently CLP will complain if isolation is used instead of level shifting. This
is an enhancement being investigated
Implementation of Standby
Each voltage domain need power planning and routing
External or internal voltage selection is required
Typically a standby domain looks like a single power supply domain
Level shifters insertion and connectivity
Domain aware buffer insertion
Domain aware DFT ensure scan chains have minimal domain crossings
Generation and routing of BIAS net, if used.

99 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Standby Mode Specification Flow

Identify Power domains

Design Step
Define Isolation Requirements

Define voltage control

Define Mode of Operation

Verification & Exploration

Define Technology Libraries

Golden CPF
Define Level Shifting Requirement
Front End Design Flow
Synthesis, LP Design &
Equiv checking
Define operating corners

Updates for Phys impl

Physical Implementation
& Signoff Flow

100 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Standby ModePower intent
Define which groups of logic should be
at the same voltage

Identify Power domains

Input isolation to gate logic
Output Isolation or Level Shifting
Define Isolation Requirements
Define when standby mode voltage is
enabled
Define Voltage control
Define voltage level for each power
domain using power mode
Define Modes of Operation Explore using RC-DEX

Define technology libraries Define libraries to use for each voltage

level

Define Level Shifter Requirements Create_level_shifter_rule

Define operating corners and Setup Multimode/multicorner

analysis views optimizations in backend

Update level shifter location

Note: The block diagram links on this page only work in Powerpoint and not in the PDF
101 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Standby Power Mode
Power modes define the set of valid voltage PD1 PD2 PD3
configurations of all the domains in the design.
PM_Normal 1.1V 1.1V 1.1V
Modes are defined as a list of PM_Standby 1.1V 0.8V 0.8V
PowerDomain@nominal_condition
Click here to learn more about nominal Conditions
# Create power domains
The power mode can define one or more domains create_power_domain -name PD1 -default
to be in a standby state create_power_domain -name PD2 -instances instance_B
create_power_domain -name PD3 -instances instance_C
The nominal condition for those domain have a
state of standby
# specify the operating voltages used in the design
create_nominal_condition -name stby -voltage 0.8
How are Standby power modes used? state standby
Simulation: Whenever the domain is in a standby create_nominal_condition -name op1 -voltage 1.0
state, all the standby mode semantics are applied to -state on
simulation
The inputs are checked for stability # associate the nominal conditions with the power domains
The logic cone for any input that changes is corrupted to create_power_mode -name PM_normal -domain_conditions
x {PD1@lop1 PD2@op1 PD3@op1} default
The voltage level is used to drive and check level create_power_mode -name PM_Standby -domain_conditions
shifter insertion {PD1@op1 PD2@stby PD3@stby} -default
RTL-Compiler, SOCE and CLP
RTL-Compiler, SOCE use these for timing, synthesis
and optimization.

102 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Introduction
Low Power Basics
What is CPF?
What are the common low power techniques and how do they
compare?
Power Techniques
Detailed discussion on each technique, how to write the CPF, and
how they impact the verification and implementation flows.
Power Shutoff (PSO)
Multiple Voltage Supplies (MSV)
Standby Mode
Dynamic Voltage And Frequency Scaling (DVFS)

103 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Common Low Power Architectures (DVFS)
Dynamic Voltage & Frequency Scaling
What is DVFS Cntl
Sel1.1V

PCM
V1.1 or V0.9
Sel0.9V VR
How do I define the Power
intent for DVFS Mode? VCO
Clk PD_DVFS
HW 0.9/1.1V
Monitor

How does my design flow

change for DVFS Mode? Dynamic Voltage & Frequency Scaling
- Each domain gets the lowest voltage and
frequency that meets performance
Example CPF - Voltage regulator to control voltage
- Frequency generator to get target freq
Summary
Leakage Power Savings : Med
Dynamic Power Savings : Med
Verification Complexity : High
Implementation Complexity : High

104 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Dynamic Voltage and Frequency Scaling (DVFS)
Description Voltage Island Voltage Island

Varies the frequency and voltage of A B

Programmable
a design
Mode Voltage
Done Real time Control Regulators
Commonly used in processor design Voltage Island

Based on system demand C

Power Savings
Optimal voltage/Frequency level per Mode Domain A Domain B
task per domain
Improves both dynamic and leakage High Perf. 1.2V 1.2V
voltage 800mhz 600mhz
Reduced frequency produces less Med Perf 1.0V 1.2V
switching power 600mhz 600mhz
Reduced voltage means
Idle 0.8v 0.8v
Less dynamic power
400 mhz 400mhz
Less leakage power
105 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Dynamic Voltage-Frequency Scaling
Speed/
Description Power
Match the voltage and frequency of a Delivered
domain to the system demands Required
Without DVFS the same performance is
delivered regardless of operation Time
With DVFS the performance is matched MPEG decode Disk r/w Text entry
to demand
Done Real time
Commonly used in processor design
Power Savings
Optimal voltage/Frequency level per
Speed/
task per domain Power
Improves both dynamic and leakage
Delivered
voltage
Reduced frequency produces less Required
switching power
Time
Reduced voltage means
MPEG decode Disk r/w Text entry
Less dynamic power
Less leakage power

106 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 DVFS Specification Flow

Identify Power domains

Design Step
Define Modes of Operation

Define Mode Transitions + Control

Verification & Exploration

Define Technology Libraries

Golden CPF
Define Level Shifting Requirement
Front End Design Flow
Synthesis, LP Design &
Equiv checking
Define operating corners

Updates for Phys impl

Physical Implementation
& Signoff Flow

107 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 DVFS Power intent
How to determine which domains
Identify Power domains
are candidates for DVFS
Define which groups of logic should
be at the same voltage
Define Modes of Operation + control
DVFS Power Modes and
Transitions
Define technology libraries
Define libraries to use for each
voltage level
Define Level Shifter Requirements
Create_level_shifter_rule
Define operating corners and
analysis views
Setup Multimode/multicorner
optimizations in backend
Update level shifter location

Note: The block diagram links on this page only work in PowerPoint and not in the PDF

108 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 How to determine candidates for DVFS

DVFS candidates are generally identified by system performance

analysis
Blocks that functionally have multiple modes of operation are good
candidates
If some applications have lower performance requirements than others
If it can be determined that this set of transactions do not require full
performance
Example in our SOC Kit the fifo is designed such that if the fifo is getting
full, the device will increase its clock frequency to empty the fifo faster. If
the fifo is low then it decreases performance to save power.
Power estimation can provide information about whether a particular
voltage/frequency combination is viable that it saves the expected
power.

109 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 DVFS Power Modes
Mode PD1 PD2

Power modes define the set of valid voltage High Perf. 1.2V 1.2V
configurations of all the domains in the design. 800mhz 600mhz
For a DVFS, each mode of operation defines the Med Perf 1.0V 1.2V
operating voltage and the clock frequency 600mhz 600mhz
CPF defines the voltage levels directly Idle 0.8v 0.8v
Each mode can include a separate SDC file to adjust 400 mhz 400mhz
the frequency used during implementation

Modes are defined as a list of # specify the operating voltages used in the design
PowerDomain@nominal_condition create_nominal_condition -name low -voltage 0.8
create_nominal_condition -name medium -voltage 1.0
The nominal condition can be used create_nominal_condition -name high -voltage 1.2
Define voltage levels for power, ground and bias
Libraries specific to those voltage # Create power domains
Operating conditions to use create_power_domain -name PD1 default \
Click here to learn more about nominal Conditions -active_state_conditions {low@c1 med@c2 high@c3}
create_power_domain -name PD2 -instances instance_B \
-active_state_conditions {low@c1 high@!c1}
How are power modes used?
Used to drive and check level shifter insertion # associate the nominal conditions with the power domains
RTL-Compiler, SOCE and CLP create_power_mode -name high_perf -domain_conditions
{PD1@high PD2@high } default
RTL-Compiler, SOCE use these for timing, synthesis create_power_mode -name mid_perf -domain_conditions
and optimization {PD1@med PD2@high } -default
Self-document the valid power states for the design. create_power_mode -name idle -domain_conditions
{PD1@low PD2@low } -default

110 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 DVFS and Power Mode Transitions

The simulator tracks the voltage level of each domains in one of two
ways:
Active state Conditions
The active state condition defines when a specific voltage is to be
applied to a domain
Create_power_domain name PD1 \
active_state_conditions {NC1@ctrl1 NC2@ctrl2}
When ctrl1 switches to active, the domain will begin to transition to the
voltage defined in the nominal_condition NC1
Create_mode_transitions
The create mode transition defines when the design will switch between
modes
Each domain will get the voltage level specified by the mode it is
transitioning into.

111 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 About Active State Conditions

Active State Conditions are one-hot

Only one can be active at a time
Shutoff condition has priority over active state condition
In a design with both shutoff and active state, if the shutoff
expression is true, the domain is considered off.
Usage models
Active state drives a voltage regulator
Active state is the digital output of a voltage regulator
An analog voltage regulator can be used in the CPF flow by
converting the voltage to a set of active state conditions for a
domain

112 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Create_mode_transitions
Create_mode_transition can be used to
define the legal set of transitions
between power modes
MA
Mode Transition Provide:
Coverage collection can verify that all
possible transitions have occurred
Error checking to ensure legal transition MC MB
and sequences of transitions
In the example, a transition from MA to MB
would flag an error
Prevents transient mode coverage
Different transition times on each domain
can make it appear that more modes
where executed. create_mode_transition from MA to MB start_condition mab
create_mode_transition from MB to MC start_condition mbc
Control of power mode transitions create_mode_transition from MCto MA start_condition mca
The start_condition defines when the create_mode_transition from MCto MB start_condition mcb
domain will start to transition
The end of the transition is one of:
All power domains have finished
their voltage transition
-end_condition has been triggered
Typically these are used mutually
exclusively.

113 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 DVFS Influence on the Design Flow

Tracking of power mode and

CPF checking
transitions
Tracking of voltage levels
Level Shifters based on Verification must cover all
Functional Verification power modes and transitions
power modes
Consistency between power
modes + active state Synthesis + DFT
Multi-mode Timing and
optimization
LP Eq Checking Clock gating, selection,
Multi-mode, multi-corner supporting the multiple clock
optimization and timing frequencies
analysis Physical Implementation Additional Level Shifters
Clock gating and
distribution.
Physical Verification

114 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 DVFS Design Considerations

Design and verification implications

Frequency changes requires very well defined clock boundaries and
interfaces
STA and functional verification must be done using all possible modes
and combinations.
Can lead to drastic increases in verification complexity.
Transitions between modes need to be verified
Requires more complex voltage regulation and clock generation

Trade-off analysis
Requires understanding of real world applications
How long will the design be in specific modes of operation
What is the power consumed by each mode
Need effective power estimation tools with correlation to synth & P&R
Latency between mode transitions
can fifos, etc keep up if demand for performance goes up quickly.
What are the full costs of implementing

115 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 DVFS Example

TDSP_CORE can operate in two

modes: PLL_CLK TDSP_CORE
0.8V @ 100Mhz
1.0V @ 125Mhz RefClk

FreqCntl
The top design operates at 0.8V
TDSP_CORE

The design needs level shifters Pm_inst

from the top-level to the
Clk_en
TDSP_CORE Clk
FSel VSel

The pm_inst controls :

Voltage with Vsel
Clock with Fsel

116 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 DVFS example: Library CPF

set_cpf_version 1.1
#################################################
# Technology part of the CPF
#################################################
set libdir ../LIBS
set lib_0v8_wc " $libdir/timing/lib0d8_wc.lib
set lib_1v0_wc " $libdir/timing//lib1d0_wc.lib \
# define the library sets
define_library_set -name ao_0v8 -libraries "$lib_0v8_wc"
define_library_set -name ao_1v0 -libraries "$lib_1v0_wc "
# define the level shifters
define_level_shifter_cell -cells LVL*HLD* \
-input_voltage_range 0.792:1.0:0.099 \
-output_voltage_range 0.792:1.0:0.099 \
-direction down \
-output_power_pin VDD -ground VSS \
-valid_location to

117 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 DVFS example: Design CPF
#################################################
# Design part of the CPF
#################################################
set_design dtmf_recvr_core
set_time_unit ms
set_hierarchy_separator "/"
set constraintDir ../mmmc
Include library.cpf

# create nominal conditions

create_nominal_condition -name high_ao -voltage 0.99
create_nominal_condition -name low_ao -voltage 0.792

# create power domains

create_power_domain -name AO -default
create_power_domain -name TDSPCore -instances TDSP_CORE_INST \
-active_state_conditions {low_ao@"!VC" high_ao@"VC"}

# create power modes

create_power_mode -name full \
-domain_conditions {AO@low_ao TDSPCore@high_ao} -default
create_power_mode -name slow \
-domain_conditions {AO@low_ao TDSPCore@low_ao}

# create rules for level shifter insertion

create_level_shifter_rule -name LSRULE_L2H -from AO -to TDSPCore

# Optional Information for RTL Simulation

#####################################################
update_power_domain -name TDSPCore -transition_latency {low_ao [email protected]:1.2}
update_power_domain -name TDSPCore -transition_latency {high_ao [email protected]:0.3}

118 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 DVFS example: Implementation CPF

#####################################################
# Additional Information for Logic Synthesis
#####################################################
# associate library sets with nominal conditions
update_nominal_condition -name high_ao -library_set ao_wc_0v99
update_nominal_condition -name low_ao -library_set ao_wc_0v792
update_nominal_condition -name low_tdsp -library_set tdsp_wc_0v792
# specify timing constraints
update_power_mode -name full \
-sdc_files ${constraintDir}/dtmf_recvr_core_gate.sdc
update_power_mode -name slow \
-sdc_files ${constraintDir}/dtmf_recvr_slow_gate.sdc
# Additional Information for Physical Implementation
#####################################################
# declare power and ground nets
create_power_nets -nets VDD -voltage {0.792:0.99:0.198}
create_power_nets -nets VDD_TDSP -voltage {0.8:1.0:0.20}
create_ground_nets -nets VSS
# add implementation info for power domains
update_power_domain -name AO -primary_power_net VDD -primary_ground_net VSS
update_power_domain -name TDSPCore -primary_power_net VDD_TDSP \
-primary_ground_net VSS
end_design

119 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Design Flow

120 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Detailed view of the Low Power Flow
Power Intent
Architect
RTL TB
Power Exploration and Verification
w/o iso.cell, SRPG, including PSO Functional validation
CPF LS, Power Switch. patterns. Functional PSO, SRPG and isolation verification
Initial CPF consistency check
Conformal LowAnalysis
Power 1. Structural check
w/o Formal Power
(formal structural power analysis)
Impl.
IES/vManager/Palladium/ISX

Conformal Low Power+ LEC

info
Front End Design
Functional Verification

Structural Checking -
Synthesis
RTL Compiler
Netlist w/ iso.cell, SRPG, RTL Power Estimation
LS Power domain/mode aware synthesis
Insert ISO, LS and SRPG

CLP
Design
Encounter
for Test
CPF
Synth 1. Power domain aware test synthesis
SoC
Implementation
Encounter 2. ATPG with power modes to model for low power
structures and reduce power during test
3. Scan chain reordering & insertion of ISO/LS into
Netlist w/ iso.cell, SRPG,
LS, Power Switch DFT nets
w/ TimingTiming
Encounter Sign-Off
System
impl. Physical Implementation + Verification
info
CPF IR drop/ power Sign-Off
VoltageStorm Power domain/mode aware P&R
final Incremental ISO, LS and SRPG insertion
GDSII Instantiate & optimize power switches

1. Power domain/mode aware delay calculation

2. STA sign-off verification
January 31, 2010
3. Power domain/mode aware IR drop verification
Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
121
 Cadence Low Power Solution
Cadence Low Power Solution
Cadence Low Power solution Chip Planning &
Complete low power flow from Architectural Exploration
specification through digital Power Intent
implementation Creation & Checking
Single Power intent used
throughout the flow LP Functional Verification
Closed Loop Verification
Each flow step is verified Frontend Design
against the original intent and Optimization
Ensures what was verified in
RTL is the same as what is Closed Loop Verification
implemented by synthesis and
physical design Digital Implementation
Extensive automation and
optimization throughout the
flow Power verification & Signoff

122 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Chip Planning and Exploration
Exec + System
Cadence Low Power Solution Marketing Designer
HW Design
Verification Engineers
Chip Planning & Engineers
Architectural Exploration

Power Intent System Performance

Creation & Checking Spec Spec
Understanding of
Verification design + technology
expertise
LP Functional Verification

Frontend Design
and Optimization
Verification Chip Planning &
Planning Architecture Exploration
Closed Loop Verification

Digital Implementation Verif CPF

Plan Chip Estimate Spec
Power verification & Signoff
Drive Verification Architectural What-if Low Power intent
Environment analysis Drive verification and
Ensure chip is Technology based implementation flows
verifiable estimate of power,
timing, area, and
January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
123
cost
 Chip Planning and Architectural Exploration

Goals
Define the optimal low power architecture that meets the product
requirements and system performance goals
Ensure that architecture can be implemented in a given technology
Ensure that architecture can be verified throughout the flow
Methodology
Chip Estimate
Rapid chip level exploration of technology libraries, IP selection, power
architectures
C-to-silicon
Explore multiple architectures of the same High-level design
descriptions
ESL/TLM level design and exploration
Verification Planning
Ensure that the architecture is able to be verified in a reasonable time
Drive the development of the verification environment

124 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Architecture Exploration
Cadence InCyte Chip Estimator: Chip Level Exploration & Planning
Estimation Results
Design Specification Die Area
Blocks, gate counts (Bounding, Utilization)
Clocks, constraints
Power
Memory, IP, I/Os
(Dynamic, Static)

Performance
(Achievable Speeds)
IP Catalog Data
Early Floorplan
(Visualization)

User Defined IP Packaged Chip Cost

(Yield, package selection)

Customizable Reports
(Datasheet, Charts)
Capture
Perform
Rapid what-if
your
estimation,
design
analysis
visualize
specification
results
EDA Data
Evaluategate
Blocks,
Accurate specification
results
counts,
within
clock
changes
seconds
speeds
quickly (LEF/DEF, CPF, SDC,

and easily
Select
Detailedtechnology
datasheet,node
reports,
and and
process
chip
Verilog, IP-XACT)

visualization
Quantify thememories,
global chipandimpact of Technology
Choose IP, I/O options Models
local
Exportblock changes
results to IC implementation
flow

125 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Chip Planning for Low Power
Explore Low Power Techniques
Architectural power what-if analysis
Quantify impact of strategies such as Vt
blending, clock gating, clock scaling, voltage
scaling, block power down and more.
Sensitivity analysis for switching activities
Overhead of advanced low power techniques

Model multiple power domains and

multiple IC functional modes
Vary low power strategy per functional mode
Optimize for multiple power domains
Export power intent (generate CPF); the
estimate drives implementation plan

Create a complete picture of low

power costs; user does not have to
be a power expert!!
126
 Enable power-aware marchitecture selection
Constraint-driven creation of multiple architectures from
single design source
XBUS XBUS
Biggest impact on power is at
1 clock domain 16 bits
16 bits
@ Y Mhz the architecture
and marchitecture level, but its
Bus Bus
16 bits Interface 8 bits padded 16 bits Interface 8 bits padded
out to 16 out to 16

Bus Read
Operation
Bus Write
Operation
Bus Read
Operation
Bus
Ctrl
Bus Write
Operation not practical to manually
Constraint latency for generated logic to 16 or 32 or 8 clock cycles

Constraint latency for generated logic to 16 or 32 or 8 clock cycles

1 write port
Read
1 read port
Write
1 write port
Read Write
1 read port
evaluate all possibilities
Array Array of 8 cycles and a latency interval of 16 clock cycles Array Array

of 4 cycles and a latency interval of 8 clock cycles

Pipeline generated logic with an initiation interval

Pipeline generated logic with an initiation interval

1 or 2 read 1 or 2 write 1 read port 1 or 2 write
ports ports ports
Process Process Process Process
Columns Rows Columns Rows
pipeline
8 read operations 8 read operations pipeline
II = 4 , LI = 8
II = 8 , LI = 16
D

D
Q

w
w
w
w
w
w
w
w
w
w
w
w

r
r
r
r
r
r
r
r
r
r
r
r

w
w
w
w
w
w
w
w
w
w
w
w

r
r
r
r
r
r
r
r
r
r
r
r
D

D
D

D
Q

requires 8 reads
requires 8 reads
& 8 writes
& 8 writes
2 reads per read
1 read per read
cycle
cycle
D

2 writes per
Q

1 write per write

8 write operations 8 write operations write cycle
cycle

Work
CtoSilcon
Work
1 or 2 write ports
Array
1 or 2 read ports 1 write port
Array 1 or 2 read ports
Allows the same code to be
used for multiple tradeoffs
Serial vs parallel implementation of oops Automates the generation of
Pipeline depth multiple architectures
Memory mArch.
Bus interface
127 2009 Cadence Design Systems, Inc. All rights reserved.
 Verification Planning for Low Power

Verification Planning for low power is:

Define the measurable verification goals to ensure the design
operates as expected and exercises all power features
Define and prioritize the set of power modes and operations in
those power modes that need to be verified
Define a measurable

Outline
Why is planning important for Low Power
What are the common verification tasks
What is verification closure

128 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Why is Planning & Metric Driven Verification
Important for Low-Power Designs?

Power architectures add complexity to verification

Verification space increases with each power mode
The device must be validated in as many modes as possible
Need to understand which features are supported in each mode
All stake holders should agree which features are valid/supported
Architect, software engineers, system designer, RTL designer,
verification engineers etc
Need to ensure modes are entered and exited without errors
Specific checks should be added to monitor this behavior
Tests need to be generated that cover the legal transitions
Planning enables the intent of the power architecture to
be documented and verification execution to be tracked
Ensures communication across teams and functional groups

129
 Planning Required???
Without planning number of scenarios
grows exponentially w/o Planning

s
Scenario
Large % of scenarios verified in each Planning
mode
Is it really necessary?
Only good planning can say
Coverage/metrics required to measure
quality Modes

Number of modes + transitions Modes + Transitions Example

Which mode/Transitions are required Real customer design:
to be verified? 10 power domains
Transition is not just one mode to the Each domain has 3 or 4 states
next, but often have multiple ways to
transition a mode ( HW, SW, > 3^10 ==> 60K modes
Interrupt,) >1M possible transitions
With a Small # of modes verify all
possible modes + transitions
This customers solution == Planning
Large number of modes requires
planning - Verify all full on + combo of with one domain
changing state
Many modes are orthogonal - Complex spread sheet with each mode weighted by
Cover each domain level transition + 4 factors and then target highest priority
targeted transitions - Used Palladium to verify as much as possible
 Who Should be involved in planning?

Planning should include

System Architect
Chip implementation architect
Verification leads
Software developers
Why so many?
Need to understand what is valid in the low power architecture
Prioritize testing based on how the device is going to be used by
target users (software, etc)
Ensure the hardware has all the required features
Ensure a consistent view of requirements across all teams

131 September 12, 2011 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 What Should be Covered in the Plan?
1.2V 0.8V Interaction with
Lib Lib
Chip Chip analog components
Power SW 1.0V
Lib
RTL CPF SDC
management
from
Dynamic
CPU/SW/HW 0.8v/1.0v
VS voltage domain
CPU A C
Standby mode
Multiple modes: and transitions
LS Iso
Mode AC B Power 1.2v Shutoff LS
PM1 0.8 1.2 Management Power off and
SR SR
PM2 0.8 Off
D power on
B

Iso
PM3 1.0 1.2 sequences
PM4 1.0 standby
PCM

Power control Interaction

module for between domains
detailed domain
level control
132
 Capturing Requirements

Define a set of scenarios, tests, transactions and features that

must be covered in each unique power mode.
What is the minimum set of testing required?
System level
Verify sequences of power mode transitions
After transition to mode X, expect a transition to mode Y within a given
number of cycles.
Off->standby maybe a required first step from OFF->HIGH
Power mode crossed with specific transaction
Did I execute an external memory write while in power mode X?

Domain interactions
When domain X is voltage Y, domain Z should be...
Sequences of domain events ( domain X transition before domain Y)
When domain Y is off, ensure the following system level transactions
still work.

133
 Domain/Unit Level Planning
States
Domain Level planning reduces complexity High
Prove domain actions work for at least one mode first
Low
Validate across multiple modes and scenarios as
needed to meet system level coverage goals Standby
Automated Metrics Off
Ensure that each domain has executed all of its possible
states and transitions
Coverage of each domain state, and transition From To
Assertions ensuring proper state transitions High Low
Assertions and coverage of individual control signals
High Standby
Per mode Checks & Coverage
High Off
Define requirements prior to entering mode
Low High
FSM state, external conditions, etc
only powerdown if the FIFO is empty Low Standby
Requirements during a mode Standby High
Clocks, resets gated? Standby Low
Control signals stable?
Off Low
Domain state crossed with specific actions
Did I test transaction X with domain Y turned off?
134
 vPlan
CPF
Verification Closure File
Plan
Defines what verification closure is
and how to measure
Power modes and scenarios, features
per mode A

Instrument A
Advanced Power Aware Testbench
Coverage & assertions to cover : C
Power modes + sequences A C
Behavior during each mode C
Power Control logic
interface between domains
Execute IFV ISX

Formal IES
Conformal
Low Power
Power Aware Simulation, emulation
Measure, Report, Analyze
Functional + Assertions coverage
LP debug
Verification Closure
When All planned features and
goals are met

135 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Automatically generated coverage and
verification plan
Power Domains
coverage of:
shutoff expr
Isolation,
State Retention

Power
Modes

Mode
Transition

136 September 12, 2011 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Intent Creation and Checking
Cadence Low Power Solution
Initial CPF based on LP
Chip Planning & Chip estimate design Exploration
Chip Estimate spec
Architectural Exploration

Power Intent
Creation & Checking
GUI driven CPF entry and
refinement Power Intent Architect
LP Functional Verification

Frontend Design
and Optimization
Extensive CPF + design Conformal LP
Closed Loop Verification checks to ensure complete
and correct LP specifications

Digital Implementation

Qualified CPF ready for Qualified

Power verification & Signoff verification + implementation CPF

137 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Intent Creation
Capture the power intent
CPF is designed to allow for rapid exploration of power architectures
At this early stage of CPF development, only a small subset of LP data is
required
Other specification languages require detailed technology and power and ground
networks in order to even begin analysis
The CPF flow enables a layered approach to enable earlier and easier exploration of
low power architectures.

Tools for the Capture of the power intent tools

Chip planning tools can be used to identify power shutoff domains and evaluate
the results
Conformal Power Intent Architect(PIA)
Provides a GUI based, guided flow for entering power intent
Simplifies the entry and ensures consistency with the design database
Significant productivity improvements especially for macro modeling and I/O pad
Text based entry of the CPF
Use examples provided in this document and in other documentations a starting point

138 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Intent GUI Accelerates design entry
Form and Flow driven entry
Design/Library aware
Guided entry
Minimize mistakes and effort
to learn Power Intent
languages

Library Setup
Read Liberty / Verilog files
Liberty or CPF power info
Create or fix power info
Macro Setup
Read Liberty / Verilog files
Read CPF power info
Create or fix power info
Design Setup
Read VHL / Verilog files
Read CPF power info
Create or fix power info
Power Intent Checks
Library, QC, or Structural

139
 What Power Intent is Required

Links to Power Intent Specification flows

Power Shutoff Specification
Multiple Supply Voltage Specification
Dynamic Voltage and Frequency Scaling
Standby Mode
Links to detailed examples
Power Shutoff Example
Multiple Supply Voltage Example
Dynamic Voltage and Frequency Example

Note: These links are one-way, they will not return to this slide
140 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 About the CPF based flow
CPF is designed for rapid low power exploration and design
Early design tasks can be started quickly with a small low power specification
As the design matures additional constructs are added, and more technology and
implementation specific information is added into the golden CPF
Each step of the flow uses the latest most detail CPF to ensure that implementation
and verification always have the same view of the power architecture
The same Golden LP Specification is used in all tools and flows

Low Power Architecture + Planning

LP Functional Verification
LP Synthesis
Physical Implementation
Golden CPF Golden CPF Golden CPF Golden CPF
-Domains -Domains -Domains -Domains
-Arch (PSO, MSV) -Arch (PSO, MSV) -Arch (PSO, MSV) -Arch (PSO, MSV)
-Isolation -Isolation -Isolation
-State Retention -State Retention -State Retention
-Library definitions -Library definitions
-Analysis views -Analysis views
-update*
-Power nets, switches and connectivity

Time
141 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power intent Architect Intro

Graphical Power intent entry built into CLP

Capture intent without having to be masters of the language
Correct by construction thus avoids syntax errors
Design aware and self checking
Ensures referenced design objects exists
Integrated into CLP for rapid checking
Flow based GUI
Walk the user through CPF creation steps
Simplify specification
A number of ease of use features especially for I/O pads
Design and library aware
Documentation location
http://dsmpubs.cadence.com/icd_pubs_website/doc_development_co
nformal.shtml/LowPower_User.pdf

142 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Intent Architect GUI
Tool Setup
General Options
Low Power Options
Library Setup
Read Liberty / Verilog files
Liberty or CPF power info
Create or fix power info
Macro Setup
Read Liberty / Verilog files
Read CPF power info
Create or fix power info
Design Setup
Read VHL / Verilog files
Read CPF power info
Create or fix power info
Power Intent Checks
Library, QC, or Structural
Export
Write power info in CPF form
Library, Macro, or Design

143
 Power Intent Entry Recommendations

New LP users
Use Power Intent Architect
The guided flow and GUI driven nature makes it easier to enter
the intent without being an expert on the CPF syntax
Advanced LP users
The choice of GUI or text based entry is a personal preference
GUI based can be less error prone, since the options and design
objects can be selected instead of typed.
PIA GUI has advantages for:
I/O pad specification
Specifying a large number of macros
Creations of library CPF

144 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Conformal Low Power
Power Intent CPF Signoff RTL+CPF Sign-Off
Library
Consistency
for
Checks
Simulation
LIB, LEF, CPF
CPF specification can have errors
Syntax, semantic, design object,
inconsistent power intent, and incomplete Power
power intent errors Simulation RTL Intent
Library
150+ checks including
Four key CPF signoff stages
Design object checks RTL+CPF Sign-Off
for
Library CPF checks (Check consistency
Synthesis
between CPF, Liberty, and LEF)
Synthesis
CPF specification inconsistencies
(Example isolation rule specifies
inconsistent physical location)
CPF specification completeness checks
(Example missing isolation rule definition Netlist
between two power domains) Netlist+CPF
CPF Integration checks Sign-Off
for PnR
Benefits
Place & Route
Identify all CPF errors as early as
possible
Help Author reach a clean CPF as fast as
possible to drive simulation, Logic
Synthesis, and PnR PnR netlist

145 2009 Cadence Design Systems, Inc. All rights reserved.

 Power Intent Checking Recommendations

Run early and often

The LP checks should be run early in the
design flow
Run prior to simulation and synthesis.
Run checking for each stage of the design flow
Early on run with high level power intent
Continue to run as more detailed CPF is developed
Find problems before spending resources on
simulation/synthesis/place and route.
Establish CLP checking as gating criteria
for check-in of the CPF files

146 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Conformal LP-Verify Checks

Power Power Iso SR Cell Shifter Switch Power

Verification
Spec Spec Insert Insert Insert Insert Ground
Stage
Syntax Quality Check Check Check Check Check

RTL Power
Spec Checks

Gate Netlist
Checks

P&R Netlist
Checks

147
 LP Functional Verification Chip
Libraries
Spec
Cadence Low Power Solution
Chip Planning + Estimation
Chip Planning &
Architectural Exploration
Switching
Verif RTL CPF Activity
Power Intent
Env
Creation & Checking
Power Intent Entry
LP Functional Verification
CPF Checking
RTL + CPF
Frontend Design
and Optimization
Design verification

Testbench Automation
Power Mgmt

Gatelevel Simulation
Closed Loop Verification
Formal Analysis

Digital Implementation RTL Simulation

SW Acceleration &
Power verification & Signoff Emulation

Verification Coverage

148 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Architecture and Initial Verification

Chip
Libraries CPF checking
Spec
Ensures that input to simulation is
correct and complete
Chip Planning + Estimation
Verification
Switching Low Power Verification Overview
Verif RTL CPF Activity
Env Components of LP verification
How does low power simulation
Power Intent Entry work?
CPF Checking What should be simulated
RTL + CPF

Design verification
Testbench Automation

Power Mgmt
Gatelevel Simulation

SW
Formal Analysis

RTL Simulation

Acceleration &
Emulation

Verification Coverage

149 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Verification Tasks Use The Correct tool for
each verification task
Verify Power Architecture
Is the power intent accurate and complete
Example: Level shifter and isolation requirements
Does the design behavior correctly in all power modes IES + Palladium
Does it behave through all power mode transitions
Can the design power up correctly
Model the low power architecture

Verify the Power Management and Control Palladium

Power management is often a complex mix of Hardware
and Software
Does the power management function correctly
Does it decide to change power modes when expected
Is it able to change the power mode
Does the low level power control work properly
Cycle power correctly, ensure proper isolation and retention
Ensure only legal modes and transitions occur
Is the control logic Alive when needed? Conformal LP

Verify the Implementation

Was the low power intent implemented correctly
Through Synthesis
Through Place and route
Does it obey all LP design rules

150 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Intent Fully Integrated Into
Functional Verification Benefits
Design Intent
Common power specification across all tools
vPlan
RTL CPF Voltage aware verification
Supports advanced LP architectures
PSO, DVFS, standby, MSV
Design verification Improved productivity
No impact to existing verification
Testbench Automation

Verif Mgmt
Gatelevel Simulation methodology
Formal Analysis No golden design file changes
No PLI or custom library development
RTL Simulation
Native implementation
No degradation of runtime
Acceleration &
Emulation Takes advantage of elaboration
optimizations
Verification Coverage Improved Reuse
Same RTL can have different power
architectures
Bottom line: Reduced Risk Enhanced quality
What you design = What you verify
Better predictability
Power issues found early

151 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Components of LP Verification Flow

Design Intent Why is Verification Planning

vPlan
Important for Low Power
RTL CPF
Structural and LP Design Checks
Formal proofs in Conformal LP
Design verification
OVM for Low Power
Verif Mgmt

Incisive Enterprise Simulator

IES, ISX, with e, SV*, OVM

Enterprise Manager Using IES for LP simulation

Testbench Automation

AMS- Mixed Signal Simulation

Gatelevel Simulation
Formal Analysis
IFV + Conformal LP

RTL Simulation Palladium in low power

Incisive Enterprise Sim Dynamic power Analysis using
application software
Acceleration &
Emulation
Palladium When to use Gate level
simulation
Automated Assertion Verification Coverage
and Coverage Enterprise Manager, ICCR,IES

*SV has limited low power support

152 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Verification Methodology for Low Power
Start with existing Verification Methodology
Including Plan-to-closure methodology, OVM, Plan and Metric driven verification,
HW/SW cosimulation.
Extend for Low Power
Planning to include low power modes, control and features
Planning is critical for low power as it can greatly increase the number of operation
modes of the design.
Include IES generated Assertions for Low power control logic
Include IES generated coverage of low power modes and control
Leverage native modeling of low power intent from CPF in the DUT
ALWAYS RUN LP AWARE SIMULATIONS
Extend Testbench environment
Power aware sequence generation
Models, scoreboards may need to be updated to reflect low power behavior
Use Low power system tasks or OVM-LP to link Testbench environment to the DUT low
power behavior
Golden CPF
Always run verification with latest most complete CPF
Even if modifications where specific to backend, always ensure that what is simulated
matches what is implemented.

153 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Guideline: Always Run LP-Aware Simulation
The Low Power verification methodology has two main recommendations
Run Conformal LP early and often
Run all simulations power aware

Why run power aware?

Some vendors recommend only running targeted tests power aware
This tests the expected LP cases and issues
What about unexpected scenarios?
What happens if the software mistakenly writes the wrong address causing an unexpected power
shutoff?
What if there is an error in the control logic that determines when power shutoff should happen?
What happens if the software writes a register in a domain where the power has been shut-off
accidentally

The Cadence LP simulation is fast enough to enable LP simulation all the time
These corner cases will be caught because the will be simulated with power
Cadence incorporates highly optimized, native Low Power modeling
Typically in a full regression run we see only a small <3% increase in runtime
Most of this is elaboration increase of 15-25% due to adding LP logic that does not exist in the
RTL (it is specified in the CPF)
For designs with extensive power shutoff we have seen improvements of 10-25%
This is due to fewer simulation events during power shutoff
Other tools use PLI or API interfaces to handle LP, these are considerably slower hence
they only recommend limited LP simulations.

154 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Architecture Exploration
- Palladium Flow
Performance Analysis
Provide system level testing with software for real-time co-simulation.
ISX can provide coverage of software related to low power
Profiling of power management

DPA Dynamic Power Analysis

Palladium box provides a significantly longer analysis window than
traditional simulation methods.
Allows for identification of true peak power and more realistic average
power.
Can provide true system level power analysis with hardware and
embedded software to allow user to see impacts of software on power.

155 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Palladium Dynamic Power Analysis (DPA) Flow
DPA
(leveraging RTL Compiler Power Estimation)

System-level Model Hierarchy Browser

DPA Processing GUI
C++, SystemC
Peak and average power consumption
Instance-based power navigation
Data processing & filtering
High Level Synthesis

RTL/Gates

DPA Analysis Display

Power Profile and waveform
view displayed in a single window
CPF Optional Analysis based on Instance &
File Signal information in SimVision

Technology
Libraries
DPA Key Benefits
System-level power analysis for large SoC (with software)
High Throughput
No emulation capacity overhead
Palladium III Cycle Accurate
High accuracy leverage RC power analysis
Calculate peak and average power over any time window

156 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 LP Verification Environment Using OVM

Existing Environment Multi-Channel Control

DUT is surrounded by
verification environment Register AHB CPU
REF

Multi-Channel Coverage
Environment stimulates Model OVC MODEL
and monitors the DUT
Low Power Manager SoC DUT
HPM

Initially created and LP Manager

PCM1
configured based on CPF
PD1

LP Model
Monitor
Sys
Consists of OVM Pwr

PCM2
Seq-er
Monitor PD2
Sequencer
Interface to simulator LP
state SW AXI PCI-X
Extensible by user for OVC OVC OVC
stimuli generation and
advanced checking Multi-Channel Checking

157 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CDNS Low Power Simulation

Part of Cadence Closed Loop Verification Methodology

Ensure the same power intent is validated in simulation as is used
throughout the implementation flow
Low Power Simulation used to find design and initialization
problems.
Typical Scenario
Without CPF - Simulation runs fine
With CPF - catastrophic failure - almost all activity in the design stops or a
hang occurs.
Cause there a many possible causes including (but not limited to)
Design errors.
Incomplete state retention or no initialization after power is restored.
Missing isolation or isolation using incorrect levels.
Embedded software errors
Combinations of all of the errors listed
Power Aware Simulation is the ONLY way to find these issues

158 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IUS Power Aware Simulation
Isolation, state retention, and power gating cells do not exist in RTL
IUS models these cells automatically based on CPF
No changes to RTL are required
Isolation forces known value when enabled
State retention saves and restores state based on control signals
Power shutoff introduces xs when shutoff, and restore to random
values or Xs when powered up for synthesizable VHDL/Verilog
(System Verilog Modports & Interfaces)
Native simulation, not PLI based
Very little impact on simulation performance, unlike PLI solutions
Replaces ad-hoc and home grown solutions
Does not require customized PLI or testbenches in order to model the
shutoff behavior
Full Low Power Verification Solution
Simvision has support for low power debug
Automatic Assertion Generation for power control signals
Voltage Ramping, Power Mode support and Voltage Based Corruption
supported.

159 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Aware Simulation
Whats Done for PSO?
-Read CPF information
-Isolation requirements
-SRPG regs Power down
control signals
-Power domains and modes
-Associated control signals Internal regs go
to X
- Simulator tracks power mode, domain voltages, voltage ramps
and domain states.
- Simulator implicitly provides PSO behavior when required
-At power down
-State loss => Force X to variables
-State retention => Read and Store State
-Isolation => Force ports to isolation values
-At power Up
-Release variables
-State restore => Write back saved SRPG values
-Remove Isolation=> Release ports
- Generates Assertions for power control sequences
- Generate Coverage of power modes and control signals
- Extensive LP Debug and analysis

160 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IUS Power Aware Simulation
Power Down Cycle Isolate, Save State, Power shutoff
Annotation of signals with power information in waveforms

Save State
Isolate
Power Shutoff

Isolated Ports

Shutoff
signals
161 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Mixed-Signal Low Power support
Support for multiple-voltage power domains
Power Smart connect module carries the effect of power shut-off, power
active state conditions, power modes and transitions onto analog blocks
Simulator identifies the CPF influence on analog blocks
Automatically Inserts Power-Smart Connect modules
Carries the effect onto analog blocks
The effect is programmable by the user
Power Smart Connect Module
- Auto-inserted by the tool
pso_data PD1 - Tracks Digital Driver
- Performs value conversion
B
A iso
D Q based on power domain PD1 state
D Q
iso_disable - No special setup/controls
required!

Spice block

162 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Verification Guidelines
Always run LP aware simulation
Some vendors recommend running only targeted runs with LP simulation
THIS IS VERY RISKY It can miss errors in the LP control logic that may cause
unexpected power transitions in what was designed to be a non-LP simulation.
In IES, LP simulation adds very little overhead for performance or memory, there is no
reason to assume this risk.
Keep behavioral code out of Power Shutoff blocks
Behavioral constructs have no defined corruption semantics and can cause
unpredictable behavior or errors in simulation
Testbench level CPF can be used to create always_on domains for behavior
sections (like RAMS or IP blocks)
Click here for some examples
Understand VHDL LP simulation restrictions and options
VHDL enumerated types and integers cannot corrupt to Xs
Run Conformal LP pre-simulation
Detect problems early and repair before launching large sets of simulations
Protect the inputs to behavioral code using isolation or gating
Many behavioral models of IP blocks were not designed for low power.
They react badly and can even crash when the inputs to the model go to Xs.

163 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Common Options for Low Power Simulation

-lps_verify
IES generates a set of standard assertions and coverage items based off the CPF file.
Saves verification engineer time and effort, and is always in sync with the CPF
-lps_verbose {1 | 2 | 3}
Provides more detailed logs of low power data
-lps_stime <time>
The lps_stime disables low power simulation until the specified time
Typically used to get past the time 0 initialization of low power control signals
Ex: shutoff_expression, save/restore controls, isolation enables
Can also be used to avoid the automatic assertions firing during power on reset
Recommendation:
Use the smallest time possible for the stime
-lps_mvs, lps_pmode, lps_pmcheck_only
Specify how the simulator will treat power modes and multivoltage designs
-lps_mvs enables tracking of voltage levels
-lps_pmode : enables tracking of power modes in the design, it uses the both the
create_mode_transition command and active state conditions to drive a mode transition.
-lps_pmcheck_only : Similar to lps_pmode, but does only users the active_state_conditions
to drive mode changes. If create_mode_transitions are defined, they are only used for
additional checking..

164 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Auto Generated Assertions and Coverage for LP

What is generated
Coverage
Coverage of power modes, transitions
Toggle coverage of power control signals
Assertions
Check for X on power control signals
Check Sequences of power control signals (ex. isolate before shutoff, save before restore)
Check LP signal properties (ex. Always isolated when shutoff, save stable during PSO)
Verification Plan
Grouping coverage and assertion results*

How is it generated
-lps_verify on the IES command line
Vmanager LP interface*

Why Generate
CPF changes frequently, each change would require changes to the assertions
Exact set of modes and valid transitions
Which domains can be shutoff
The exact control signals used for a domain
Guaranteed consistency with CPF
Manual assertions can get out of sync with hardware

*Note: functionality in the Vmanager interface is being moved to IES over the next few releases, this
provides a simpler more complete interface

165 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Controlling Assertions During Power shutoff
User defined assertions are not always valid during power shutoff
IP blocks not designed for low power
Checking logic in a shutoff domain against Xs
Sequential checks may not expect long delays due to PSO

create_assertion_control - provides the ability to disable assertions during

power shutoff and control how the assertions behave when powered up.
CPF method to specify the control
No need to modify the source assertions
-type reset | suspend if reset, all state information is cleared and the assertions will be
evaluated from the reset state. If suspend, controlled assertions from where they left
off.
Can disable all assertions for a domain, or individual assertions -assertions, -
domains, & -exclude
Recommend: Use -shutoff_condition with a longer window than the actual power
shutoff
The power domains PSO signal will enable assertions before the state has been restored
Using isolation enable is typically a good alternative

create_power_domain -name PD_add_ab \ -instances {add_ab} \

-shutoff_condition {u_pmc/pso_en[0] & u_pmc/cond_3[0] }

create_assertion_control -name ac1 -domains {PD_add_ab} -type suspend

-shutoff_condition iso_en

166 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Logic Netlist - Gate Level Simulation

Why gate level simulation?

Targeted tests to verify timing hazards or as a sanity check of implemented
design
Typically a very small % of the total verification suite
Some customers do not run gate-level at all and rely on static checks from CLP
Inputs:
Original CPF
Name Mapping file produced by synthesis
Defines how to map original names to synthesized names
Handles Bus/register naming styles, hierarchy changes, etc.
Gate level tests and sim environment
Typically the RTL simulation environment cannot be used directly since any references
to the RTL names/objects are likely to have changed
Often directed tests are used for the gate-level simulation
Simulation
Turn off isolation and state retention modeling (lps_iso_off, lps_rtn_off)
Simulator models power shutoff and power switches
Simulator tracks power modes and voltage levels for each domain
-lps_verify automatic assertions and coverage are still valid for gate-level

167 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 LowPowerSim Flow
RTL Versus Gate level simulation
Design type Isolation Retention State Loss
RTL CPF CPF CPF
Gate netlist ISO cells SRPG cells CPF
(LP cells inserted)
RTL and gate User decides

Specific behavior depends on the type of the design:

if RTL design, then all three PSO behaviors need to be provided.
If LP cells already inserted, then only state loss is needed.
User can selectively enable PSO behaviors proper for design

CPF commands used:

define_isolation_cell -cells cell_list -enable pin [-always_on_pins pin_list]
define_always_on_cell -cells cell_list
define_state_retention_cell -cells cell_list [-always_on_pins pin_list] \
[-always_on_components component_list]

168 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Front-end Design and Optimization
Cadence Low Power Solution
RTL CPF
Chip Planning & Libraries
Architectural Exploration Verif
Power Intent Entry
Env
CPF Checking
Power Intent RTL + CPF
Creation & Checking

Verification LP Synthesis + DFT

LP Functional Verification Flow Synthesis
Switching Power Analysis
Frontend Design

Functional Verification
Activity

(Very specific tests)

Gate Simulation
and Optimization DFT

In Parallel Name Power Exploration

Mapping
Closed Loop Verification

Logical
Netlist
Digital Implementation
Conformal LP
Structural + Equivalency
Power verification & Signoff

169 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Flow Front end Design + Synth
CPF checking pre synthesis
Ensures that input to synthesis is correct and
RTL CPF complete
Libraries
Ensure that library data is complete and
Verif consistent
Power Intent Entry
Env Synthesis
CPF Checking Power aware synthesis
RTL + CPF
Inference of LP logic
Connection of LP control signals for state
LP Synthesis + DFT retention and isolation
Verification Power Architecture Exploration
Flow Synthesis
Power Analysis + Estimation
Switching Power Analysis CPF name mapping flow
Functional Verification

Activity
(Very specific tests)
Gate Simulation

DFT
Design for Test
In Parallel

Name Power Exploration

Mapping

Conformal LP
Logical Equivalency checking on CPF+ input RTL vs
Netlist synthesized output + CPF
LP Design checks
Conformal LP
Structural + Equivalency Limited gate-level simulations
Small set of tests to verify LP insertion and timing
Name mapping flow

170 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF in an RC Flow

Power Aware Synthesis

Why Power aware Synthesis
Optimize for dynamic and leakage power
Optimize timing paths due to insertion of LP cells
ISO, LS and SRPG cells
Area/Instance-count increase due to LP cells
RC-Physical flow is CPF-Aware
RC flow

Power analysis and Exploration

RTL design Exploration
Power Analysis
Analyze power savings due to Low-Power architecture specified through
CPF

RTL Based Power Analysis

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 RC CPF flow yes Run
Hierarchical CPF CPF
no Integrator

read_cpf -library

RTL read_hdl; elab

CPF SDC TCF read_cpf

check_cpf CLP

Synthesize -to_map no_incr

reload_cpf; commit_cpf

Synthesize incr Synthesize to_placed EDI

Netlist, SDC

PnR

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 RC Low Power
Read CPF to get technology libraries
CPF Defines the set of libraries to use and which cells in the library are low
power
Check CPF
Pre-synthesis call CLP to ensure input CPF is correct
After synthesis call CLP to ensure that LP logic was correctly inserted
Automated process issued by single command in RC
Generates all scripts necessary and executes CLP
Synthesis
Insert and optimize state retention, level shifters and isolation cells
Multi-mode, multi-VT synthesis
Modes defined by CPF power modes
Optimize all modes and design constraints concurrently
CPF also provides
Links to switching activity files for dynamic power analysis
Optimization constraints for Low Power
Works with existing RC - LP features
Clock gating, operand isolation, advanced dynamic and leakage power optimizations
Re-read/commit CPF
This final step is used to ensure any logic added by test insertion have complete
isolation and level shifting
Analysis
RTL and gate level power analysis and reporting
173 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF Integration and CPF Quality-Check
If CPF is hierarchical (domain_mapping, group_modes) then CPF
integrator has to be run prior to synthesis
Command to run CPF Integrator: integrate_cpf
CPFQuality-Check.
Run Quality check prior to Synthesis
rc:/>set_attr clp_treat_errors_as_warnings {CPF_LIB* CPF_ISO13} /
rc:/>check_cpf
Common Warnings
CPF_ISO1 : No isolation rule specified for power domain crossing
CPF_ISO13 : Isolation rule unnecessary between domains
It is not legal to specify an isolation rule for a crossing between two domains that
are always at the same state (OFF or ON) in every power mode. Review the
detail/verbose message for isolation rule name, from and to domain names, and
analyze the conditions of these domains in all power modes. The power modes
might be incomplete or incorrect or the isolation rule might need to be removed.
CPF_LS6 : Level shifter cell not defined through define_level_shifter_cell command
More then 60 quality-check rules
http://dsmpubs.cadence.com/icd_pubs_website/doc_development_conformal.sht
ml LEC_LowPower_Ref.pdf

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 read_cpf -library
Run Parser and CPF linter
define_library_set : library_domain creation and .lib parsing (set
default LD)
Watch out and act on following
Try to have consistent libcells all over the library-domains
LBR-38 inconsistent nominal operating-condition
LBR-34 Pins used in next-state functions must have setup timing arc.
Otherwise the libcell will be treated as timing-model
LBR-75 Detected a combinational timing arc in a sequential cell
define_*_cell cpf_commands processed
Operating_condition is also set from this default library-domain

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 read_cpf
Reads the Power intent from the CPF file
Level shifters
isolation cells
power modes
Power domains
Associates domain with proper library based on default power mode
Power domain creation and association with library as per default
mode
rc:/>report power_domain -mode
Power Domain PM1 PM2 PM3
PD1(*) 1.2 V 1.2 V 1.2 V
PD2 0.8 0.7 OFF
PD3 0.7 OFF OFF

Read SDC and toggle information from CPF, if provided

Preserve design objects pins which are referred in CPF

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 Synthesize to_map no_incr
State-Retention flop/latch mapping
State Retention Synthesis Status
================================
Category Flops Latches Percentage
-------------------------------------------------------------------------------
Total instances 1627 1 100.0
Excluded from State Retention 1343 1 82.6
- Will not convert 1343 1 82.6
- Preserved 0 0 0.0
- No map flag 1343 1 82.6
- Could not convert 0 0 0.0
- Scan type 0 0 0.0
- No suitable cells 0 0 0.0
State Retention instances 284 0 17.4
---------------------------------------------------------------------

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 commit_cpf

Inserts level shifters and Isolation logic

Flow
Removes existing Isolation and level-shifter cells
Applies the Isolation and level-shifter rules on appropriate pins
rc:/>get_attr pins [find / -isolation_rule ISO1]
rc:/>get_attr cpf_selected_pins [find / -isolation_rule ISO1]
Insert ISO and LS on the basis of location

Notes:
If ISO and LS rules both present on a crossing and location is also
same RC tries to insert Combo (ISO+LS)
If combo not found , separate ISO and LS will be inserted
Level-shifter insertion happens post ISO-insertion
If require LS will be inserted on enable of Combo/ISO-cell
Run reload_cpf before commit_cpf if there is any new PD crossing possible
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 commit_cpf cont..

create_isolation_rule name LS1-from PD1 pins Sub1/Out

Update_isolation_rule names LS1 -location to

Newly created Port

CPF_ISO_ENABLE_.. In LS1 Sub2
PD3
PD2
Sub1
Out
PD1 RC_ISO_HIER..
Switchable
In LS1
Iso Newly created Port Sub3
CPF_ISO_ENABLE.. PD2

Create ports for Control signals

The RTL does not distribute the control signals, they are built up based on CPF
Insert isolation and level shifting
Creates separate hierarchy for easier identification and visualization
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 Isolation/ Level-Shifter insertion on constant nets
commit_cpf will also insert isolation-cells and level-shifter cells on
constants domain crossings.

PD1 PD2
1b1 1b1
commit_cpf

1b0 1b0

synth incr will propagate constant through iso cells if constant

type(1,0) and isolation-type (high,low) matches and following
attribute is enabled.
set_attr constant_prop_through_iso_cell true /

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 CPF in an RC Flow

Power Aware Synthesis

Why Power aware Synthesis
Optimize for dynamic and leakage power
Optimize timing paths due to insertion of LP cells
ISO, LS and SRPG cells
Area/Instance-count increase due to LP cells
RC-Physical flow is CPF-Aware
RC flow

Power analysis and Exploration

RTL design Exploration
Power Analysis
Analyze power savings due to Low-Power architecture specified through
CPF

RTL Based Power Analysis

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 RTL-Based Power Architecture Exploration

RTL power exploration & estimation of:

Multiple supply voltage Lib2 Lib1
Specify different voltage domains 1.0V 0.8V Chip Chip
Dynamic and leakage power estimation Lib3 RTL CPF SDC
based on domains voltage settings 1.2V
Power shutoff
Top
Explore creation of power domains PSO
Define shutoff signal for switchable domains A

Isolation
C
Average power calculated using signal B
probability of shutoff signal
Support for state-retention cell modeling
during shutoff
Dynamic voltage-frequency scaling
Combine multi-supply with multi-mode
Explore power-timing interaction to arrive at Too slow Too hot?
right balance, pre-implementation

Early closure on power architecture

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 RTL Design Exploration
RTL
Target libraries
Quickly explore multiple scenarios Timing constraints
Multiple supply voltage CPF (library info) Power domains
Modes
Power shutoff Power exploration settings
Voltage ranges
Dynamic voltage-frequency scaling Switching activity Iso/shifter/retention
Built natively into synthesis engine Synthesis settings
Timing view Superthread
Optimization/library-aware power
view

Physical interconnect awareness Scenario 1 Scenario 2 Scenario n
Superthread Superthread Superthread
Continuous refinement flow
Early estimation Script Script Script
Report Report Report
Quick mapping CPF CPF CPF
Flow to production synthesis with
physical

Achieve the best timing-power-area balance Tabulated report

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 RTL & Gate Power Estimation Flow
3rd Party
With Encounter RTL Compiler Simulator

VHDL Incisive
Verilog Simulation
System- Incisive
Verilog Palladium
RTL and/or Netlist

Constraints SAIF
SDC
Library Encounter RTL Compiler VCD
.lib
TCF

Frequency Switching Activity:

Operating cond. - Avg: SAIF, TCF
Interconnect Report Power - Peak: VCD
- by category Report
- by hierarchy 90
80
70
60

- static vs dynamic
50
40
30
20
10

- cell vs net 0
Clock Net Cell

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 Capturing Switching Activity

Use to drive power arch. or RTL Default, user-asserted

Arch. decisions

Encounter RTL Compiler

Can start with default or user-
3rd
asserted activity IDTS IES party
Activity propagated to internal TCF, SAIF, VCD
nodes Simulation
Re-use RTL activity at gate-level
Recommendations:
Focus on average power early in VCD
the design cycle
Capture realistic operation Acceleration
Multiple TCFs can be merged and
weighted
Utilize acceleration and emulation
for most accurate profile VCD

Emulation

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 Power Estimation Requires Synthesis Knowledge!
D Q D Q D Q

CLK CLK CLK

D Q D Q D Q

CLK CLK CLK

D Q D Q D Q

CLK CLK CLK

RTL power estimation constraint aware

Power affected by cell sizes and voltage thresholds, and net capacitance
Huge variations in 90nm and below!
Timing-critical logic can consume more power than non-critical after optimization
Automatic power and area optimization will greatly affect power
Understanding what synthesis will do - is crucial to effective power prediction
Timing opt: SDC, available library cells, optimization settings, wire delays, etc.
Power opt: clock gating strategy, dynamic power optimization, etc.
186 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 FAQ: How can I get the most accurate power
estimate?

Use PLE for the most accurate wire loading. You can scale the
model slightly to add pessimism if desired.
(scale_of_cap_per_unit_length and scale_of_res_per_unit_length)

Use accurate clock frequencies in your SDC since they are used to
calculate switching activities. Use path_adjust if you want to
overconstrain synthesis.
Annotate switching activities on primary inputs and sequential
outputs. This can be generated from an RTL simulation.
Fast conditions generally consume a lot more power than slow
conditions - analyze power using fast libraries.
But, it is necessary to synthesis for timing using slow operating
conditions. RC has a solution

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 CPF in an RC Flow

Power Aware Synthesis

Why Power aware Synthesis
Optimize for dynamic and leakage power
Optimize timing paths due to insertion of LP cells
ISO, LS and SRPG cells
Area/Instance-count increase due to LP cells
RC-Physical flow is CPF-Aware
RC flow

Power analysis and Exploration

RTL design Exploration
Power Analysis
Analyze power savings due to Low-Power architecture specified through
CPF

RTL Based Power Analysis

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 RTL Power Prediction in
Encounter RTL Compiler
SDC CPF Switching
lib RTL activity
Early exploration of power
architecture tradeoffs
RTL Compiler
Timing vs. power vs. area
Elaborate
Uses RCs unique technology-
dependent generic cell modeling
report power [-rtl]
Fast turnaround
Accurate insight into synthesis
optimization
Early insight into power bottlenecks RTL power report
Find and fix them before synthesis Sequential
Captures necessary operating profile Combinational
info from simulation Clock tree
I/O
Early and accurate power prediction to drive
Macros
large-effect power decisions
189 January 31, Cadence
2007, 2010 Cadence Methodology
Design Systems, Inc. Guide 2011 Cadence Design Systems, Inc. All rights reserved
 RC RTL Power Estimation
Builds accurate Power models for Power Estimation at the RTL level
Takes into account ALL timing and optimization constraints

Current Capabilities

MSV Aware
Detects power/library domains
Builds separate RTL Power models for each domain
Clock Gating Aware
Takes into account the effect of Clock Gating
Honors all clock gating attributes
Super-threaded
Improves runtime
Same QOR

190 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 RTL Power Analysis (RTLPE) Flow

Import the design

read_hdl
elaborate
Read_sdc
read_tcf/vcd/saif Important for accurate results
apply all other synthesis constraints
Build RTL model
synthesize to_generic
build_rtl_power_models
-clean_up_netlist: removes redundant and un-reachable logic
-clock_gating_logic: Computes power consumed by clock gating logic cells
report power
Detailed power reports
Can dive into individual modules and operators

191 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 RTLPE Sample Output
Starting building RTL power analysis models ...
Preprocessing the netlist for building RTL power models ...
Building RTL power models for domain
/designs/p2002_nexus_top/instances_hier/sc_nex3 ...
25% completed ...
50% completed ...
75% completed ...
100% completed ...
Building RTL power models for top-level design /designs/p2002_nexus_top ...
25% completed ...
50% completed ...
75% completed ...
100% completed ...
Building power models for clock gating logic ...
Done building models for power analysis.
Leakage Dynamic Total
Instance Cells Power(nW) Power(nW) Power(nW)
------------------------------------------------------------------------------------------------------
arm11p_platform_128k 402219 2927535.239 39423132.772 42350668.011

Estimated Power of Clock-gating Logic

--------------------------------------------------------
Leakage Power(nW): 1719.654
Dynamic Power(nW): 309299.989
Total Power(nW): 311019.643

192 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Drill Down Into Top Blocks
After block is targeted, potential course of actions:
Try different constraints/settings
Is timing too overconstrained? Try path_adjust instead
Change max_leakage, max_dynamic, effort level, etc.
Re-allocate power budgets
Re-explore architecture
Apply clock gating?
Explore RTL structures:
20: always @(state) -----------------------------------------------
21: case (curr_state) File Row RTL Switching Leakage
22: 4b001: next_state = 4b001; Power Power
23: 4b001: next_state = 4b010; -----------------------------------------------
24: 4b010: next_state = 4b011; state.v 32 if (rst).. <=0 25321.64 4692.33
25: 4b011: next_state = 4b100; state.v 35 curr_state <= 67098.17 1099.56
26: 4b100: next_state = 4b101; state.v 25 next.. = 4b100 10792.98 6897.12
27: 4b101: next_state = 4b110; state.v 29 next.. = 4b000 9458.34 7124.48
28: 4b110: next_state = 4b111; .
29: 4b111: next_state = 4b000; .
30: .
31: always @ (posedege clk or posedge rst)
32: if (rst) curr_state <= 0;
33: else Re-encode state machine?
34: if (en)
35: curr_state <= next_state;
193 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Design For Test

194 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Tests Advanced Power Management Techniques
Managing Power During Test ,Testing Low Power Designs

Insert Power-Aware DFT Power Aware DFT Reduce Power Power-Aware ATPG for
Structures and Modeling during test managing scan and
Configure Power-Aware capture switching activity
Scan Chains PD1 Power Modes processed
PD2
Power Modes reflected as and analyzed separately
Test Modes MBIST scheduling allows
Power Domains and Scan PTAM for runtime adjustment to
Structures Verified manage power

RTL Scan Power Estimate TestPattern

Test Pattern Flows and CPF Driven DFT
Test Pattern Activity PowerValidation
Power Validation Methodologies
CPF Driven Test Modes
Analysis PMU
Top
Test Pattern Generation
Test Interface with EPS PD1 PD4
(VoltageStorm) Power Test Pattern Analysis
Mem
Calculation Core
Test Pattern IR Drop SR PD2
PD3
Analysis

Power Aware Test Is Active Throughout The Test Flow

19 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
195
5
 RC-DFT Low Power Flow CPF Read CPF

Setup Test
Reading of CPF
Used within the RC environment to address Power
Run
Report
DFTScan_Power
rules checker
Aware DFT features

Early Power Analysis

Estimation of scan power using liberty files Insert scan
insert_dft power gates
boundary_scan

Scan Gating
Locates high fan-out flops for testpoint insertion insert_dft mbist
Testpoint will block shift toggles into functional logic

Power Test Access Mechanism (PTAM) connect_scan_chains

Stabilizes Power Domains during test
Provides control over power controls during test
Enables testing of power manager compress_scan_chains
Power Aware Scan
Scan chain connect can be limited to power domains
Minimizes Power Domains crossings insert_dft ptam

Power Aware Compression

Scan segments defined within a single power domain Scan a power domain
End of Scan Segment is isolated to preserve signature

compress_scan_chains
-power_aware

196 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF Driven Design-For-Test (DFT)
Power Aware Scan Chain Construction
Broadcast Decompressor
Power Domains Identified
Minimized Power Domain Crossing
Scan Chains Targeted to Power Domains Automatically B
Power Aware Compression Insertion A

Scan segments localized to a power domain C

Isolation
Isolation placed to assure stable Signatures Logic

XOR Compressor

PSE : Power Switch Enable

ISO : Isolation Enable
PGE : Power Gate Enable

Chip
Power Manager Block
Power Test Access Mechanism (PTAM)
PSE Stabilizes Power Control Interface
P1 Power
ISO Switchable Enable testing of the Power Manager
P2 Controller
Power
P3 Domain Process power design structures
PGE
Enable Power Mode Selection for Test
PTAM
Interface PTAM
PTE

197 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Encounter Test Low Power Flow
Build Test Module
Reading of CPF
CPF definitions structured for Encounter Test
CPF Build
Prepare
Fault
CPFModel
Data
Power Modes
Power modes mapped to Test modes
Power controls verified for stability Build Test Modes
Power switches state
Isolation state
Retention state Verify Test Modes

Scan Chains
Validated for each power mode configuration Create ATPG Patterns

ATPG
Switching control managed (scan & capture) Analyze Switching
Write Patterns
Targeted test generation for Power Components

Fault Reporting
Finished
Power Component-Aware Fault Reporting
Analysis
Identification of potential high switching patterns
(both during scan shift and capture)

198 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Testing CPF Identified Power Components

PD0 PD1
SI1 1 0
X 0 1 1 1 1 SO1

CPF SI2 0X 1X 1 0 0 0 SO2

retention flop
CPF Library Definitions standard flop

Indicate Power Components

Level Shifter
Isolation Cells
Retention Flops
ATPG Targets Power Components
Fault sub-set of power components can be targeted
Retention flops can be power cycled
Isolation can be placed into multiple states (isolating or not-isolating)
Power switches can be stressed with transition pattern

199 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Managing ATPG Activity Level
For Scan Shift
Maxscanswitching keyword for Encounter Tests ATPG
This is done by controlling the level of random fill data
Provides a means to manage activity level during scan shift

Quality impact low Test Activity high Yield impact

For Capture
Maxcaptureswitching keyword for Encounter Tests ATPG
Utilizes functional clock gating
Manages clock activity during capture portion of test pattern

Excessively High Active Test Patterns Impacts Yield

Excessively Low Active Test Patterns Impacts Quality
200 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Analyzing Test Patterns Activity
INFO (TBM-054): Capture Toggle report categorized by SEQUENCE [end TBM_054]

Switching Activity +=============+===========+============+===========+===========+

| Odometer | Relative | Number | Global | Max |
Can be verified | | Sequence | of | Average | Switching |
| | | Pulses | Switching | Percentage|

For all or each Test Sequence | | | | Percentage| |

+=============+===========+============+===========+===========+
|1.1.1.6.8 | 28 | 3 | 20.97 | 34.63 |
During Scan Shift |1.1.1.6.7 | 27 | 3 | 20.27 | 34.19 |
|1.1.1.15.16 | 222 | 3 | 20.25 | 34.74 |

During Capture Cycles |1.1.1.14.4

|1.1.1.14.10 |
| 178 |
184 |
3 |
3 |
18.00 |
17.98 |
34.73 |
35.01 |
|1.1.1.10.14 | 90 | 3 | 17.98 | 34.83 |
Number of pulses |1.1.1.10.7 | 83 | 3 | 17.98 | 34.90 |
|1.1.1.16.52 | 290 | 3 | 17.95 | 34.66 |

Average across pulses |1.1.1.12.19 |

|1.1.1.10.16 |
159 |
92 |
3 |
3 |
17.86 |
17.86 |
34.63 |
34.76 |
|1.1.1.9.2 | 62 | 3 | 17.84 | 34.46 |
Maximum pulse activity |1.1.1.16.54 | 292 | 3 | 17.78 | 34.55 |

Multiple Reports of Analysis can be generated

Goal to identify violation of activity target goals
Identify test pattern sub-set that requires a detailed power analysis
Validate faster scan shifts to reduce test cost
Determining scan activity, shift frequency and power
201 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Deep Test Power Analysis

Analysis of Sequences at a Coarse Level: Vectored IR Drop

Vector-less TCFFlow
Flow
Toggle Count Format can be generated
Encounter Test
Allows for large Test Pattern set analysis
Allows for regional analysis ATPG
ATPG Test
Test
Patterns
Can be for a single Test Sequence Patterns

Toggle
write_toggle_gram
write_toggle_gram
High
Count
Switching

Analysis to Identify Highly Active Sequences

File
Patterns

Generation of scripts for VCD creation Timing

Windows IR Drop
VCD can be used for scan shift window analysis File
SDF Sub-set of high
Plots
activity cycles

(Optional)
VCD can be used for capture pulses analysis EPS
Scripts also generated to run EPS NCSim
VCD
w/
Timing
Timing
Windows IR Drop
Once Layout Data is Available: File Plots

More detailed power numbers for test

Calculated from probabilities (TCF) EPS
Simulated with VCD

202 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Implementation Verification

Low Power Equivalency Checking

Closed Loop Verification flow
Gate Level Simulation

203 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Closed Loop Verification
Cadence Low Power Solution
Synthesi
Design P&R
s
Chip Planning &
Architectural Exploration RTL Netlist Netlist

Power Intent

Sign-Off

Sign-Off
Sign-Off Verification Verification
Creation & Checking design checks design checks
and LP EC and LP EC
NCsim
LP Functional Verification

Frontend Design
and Optimization CPF

Closed Loop Verification Closed Loop Verification

Guarantees what is implemented matched what was simulated
Guarantees what is simulated and implemented match original LP
Digital Implementation Intent

Process
Power verification & Signoff Every Step is compared against previous step
Every step uses original CPF
Every Step verified against LP design rules

204 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Conformal LP

Closed Loop Flow

Examples of Problems Detected by CLP

Checklist for using Conformal LP

205 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CDNS Closed Loop Methodology
Power Intent
Simulation verifies golden RTL + Architect
TB
golden CPF RTL
Ensures that design intent is correct w/o iso.cell, SRPG, including PSO
patterns.
Ensures that power intent is correct CPF LS, Power Switch.
Initial
Conformal LowAnalysis
Power
Implementation builds the design w/o Formal Power
(formal structural power analysis)
Impl.
Based on power intent and design

IES/vManager/Palladium/ISX

Conformal Low Power+ LEC

info
intent

Functional Verification

Structural Checking -
Synthesis
RTL Compiler
Cadence tools enable automation
Netlist w/ iso.cell, SRPG,
and correct by construction LS
implementation

CLP
Design
Encounter
for Test
CPF
Conformal CLP verifies Synth
Implementation against golden SoC
Implementation
Encounter
power and design intent
Power aware Equivalency Check Netlist w/ iso.cell, SRPG,
LS, Power Switch
Formal structural check of power w/
structures TimingTiming
Encounter Sign-Off
System
impl.
Electrical check of power intent info
CPF IR drop/ power Sign-Off
VoltageStorm
Closed Loop final
Golden Power intent verified
against all implementation
GDSII
transformations
206 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Closed Loop LP Verification Methodology

CPF Quality Checks CPF

Ensure LP intent matched design File Conformal Low Power
Power Intent Architect
RTL simulation
Dynamic validation of LP functional behavior
Equivalence Checking for LP design Conformal Low Power
CPF Quality Check
RTL
Ensure LP optimizations do not introduce logical
errors Incisive Enterprise Simulator
Enable domain aware EC leveraging CPF Functional Verification
Compare logical vs. power aware physical netlist
Check corresponding presence of low power cells Logic Synthesis & DFT
and power domain boundaries Gate netlist

Structural, Rule, and Functional checks Conformal Low Power

Equivalence Checking
Ensure proper insertion of low power cells
Ensure proper connectivity of low power cells Conformal Low Power
Structural & Functional Front-end
Formally validate isolation function
Signoff
Formally validate state retention function Physical Implementation Physical netlist
Supports both logical and physical (power aware)
netlists leveraging CPF Conformal Low Power
Equivalence Checking
Transistor Electrical Verification
Conformal Low Power
Detect Sneak (leakage) paths across power
Structural & Functional Back-end
domain boundaries
Signoff

207 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Conformal LP Design Checks

Low Power Design checks

Check design power structure
Check correct insertion of low power cells
Steps
Read library models
Run library analysis and fix errors
Read synthesized gate netlist and design power intent
Run structural power analysis

208 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Comprehensive Design Checks for
LP Designs
Power Intent Profile Physical Netlist
CPF
Level shifters
Design Object Checks
Power Intent Profiling RTL Placement/Location
Library Checks
Power connectivity
Spec. consistency
Low Power Checks Isolation cells
RTL/Logical Netlist Low Power Assertions Placement/type
Level shifters Power connectivity
Placement Functional simulation
Isolation function
Location State retention cells
Logic Synthesis & DFT
Connectivity Gate netlist Placement
Isolation cells Low Power Checks Power connectivity
Placement Retention function
Isolation type Logic simulation
Power and Ground Switch
Isolation function Power/Ground
Physical implementation
State retention cells Physical netlist Connectivity
Placement Low Power Checks Enable Control Polarity
Transistor net.
Retention function Miscellaneous
LEF.
Transistor Netlist
Miscellaneous Shorts b/n VDD/VSS
Floating nets / pins Transistor Stacking Always-on buffers
Un-buffered Input
Control Polarity Macro Power Associations
209 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Equivalence Checking
Goal: Implementation Functional Verification Keeps design
Golden

Power Intent
RTL vs. Gate
Performs functional insertion CPF consistency checking RTL
of isolation and state retention
Functional simulation
registers into RTL design
database for EC purposes
Logic Synthesis & DFT
Gate netlist
Checks retention register
mapping LP Equivalence Checking

Gate simulation [Optional]

Gate vs. Gate
Front-end
Enables logical gate versus Signoff

physical gate netlist compare

Physical implementation Physical netlist
Enables power domain aware
LP Equivalence Checking
equivalence checking
Final
Signoff

210 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Conformal LP

Closed Loop Flow

Examples of Problems Detected by CLP

Checklist for using Conformal LP

211 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Real Problem Found by LP Checks:
Unprotected Off->On Domain Crossings Due To Test
Points

Do:
Protected always insert
low power
cells after all
Logic iso Logic other netlist
modifications
set

run low power

D
Q
Ti
Te

clr
Q structural
checks early
and often
clk
iso_n Unprotected

212
212 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Examples of CLP Structural and Formal Proofs
Isolation in Receiving Domain

VDD VDD VDD

En2
1 En1
En2 V1 V2
Power 0
Control En1 X
ISO D1 D2
1 VDD

Structurally prove:
En1, En2, and Iso1 are always driven
Formally prove:
En1 = 0 & En2 = 1 Iso1 = 1

213 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Examples of CLP Structural and Formal Proofs
State Retention Check

SRPG
PwrEn1
PwrEn1 VDD VRET Q
Power RTCLK
Controller
D
RET SRPG
V1 RET
V2 RTCLK

RTCLK Dont care

D
Dont care

Q
X
RET
Sleep Wake

Structural Check
Checks that RET signal is powered; VRET tied to continuous Power
Checks that VDD and D pins connect to the same power domain
Functional Checks
Assert when (RETi || RETh) (RTCLK is in off-condition)

214 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Conformal LP

Closed Loop Flow

Examples of Problems Detected by CLP

Checklist for using Conformal LP

215 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Checklist for using Conformal LP

Phase 1 : Preparation and Setup before design analysis

Audit low power library
Can all level shifter, isolation, retention, and switch cells be
modeled?
Are there any special functions that are hand inserted?
Verify library views are consistent
Is the LEF, power intent, and models compatible
Fix library issues before running design analysis

216 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Checklist for using Conformal LP

Phase 2 : Profiling the design

Review messages after reading in the design
Dont ignore messages like HRC3.3 errors
Understand the black boxes
Understand why a cell is black boxed, is it expected?
report black box class > bbox.report
Black boxes with multiple pwr/gnd pins need macro
models?
Did you define pwr/gnd clamp cells correctly?
Are feedthru cells (spacers) modeled correctly?
Are pwr/gnd pads modeled correctly?
Remove non-functional cells (decap and filler cells for
example)
remove <list of cells> ins_mod -all > /dev/null

217 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Checklist for using Conformal LP

Phase 3 : Reading Power Intent

Are all power intent QC errors understood
Do you ignore those that are meaningless?
How do you determine which are meaningless?
Focus on the root cause of the error
Many errors can be grouped by domains
Find the commonality of a group of errors in a
category and fix that common error.
Take advantage of advanced power intent
features
Default isolation condition with isolation constraints
Internal switched domain mapping

218 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Checklist for using Conformal LP

Phase 4 : Power Domain Analysis

Resolve PDM errors
These errors will impact many other checks
Get these fixed first
Structural errors (ISO7, LSH3, etc)
Identify commonality of domain crossing structural errors
and focus on fixing that, many structural errors share a
cause.
Experience in design is helpful to debugging design errors
Insertion rule errors (CPFRULE*, RETRULE*, etc)
Group errors related to a rule together, fixing one error
usually fixes all.
Use report pin driver cell <cell> <isopin> -verbose path
to identify control paths for errors related to wrong control
pins.
219 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Checklist for using Conformal LP

Phase 5 : Macro Models and Hierarchical Errors

Resolve macro1 and macro2 errors
These errors report incorrect power or ground port
connections to the wrong power or ground net.
Understand why CLP checks domain mapping for Soft IP
(hierarchical power intent) and Hard IP
Ensures IP is not used in modes that are not legal
Explain to providers of IP why a complete power spec is
required for complete power verification

220 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Digital Implementation
Cadence Low Power Solution

Chip Planning &

Architectural Exploration Preparing for Physical Design
Power Intent
Creation & Checking
Detailed LP Implementation flow
Floorplanning Considerations for LP
LP Functional Verification
EDI topics
Frontend Design Power switch insertion
and Optimization
Always on cells + In Place Optimization
Closed Loop Verification Level shifter insertion
Isolation insertion
Digital Implementation
Power Verification and signoff
Power verification & Signoff

221 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power flow with implementation
Creating the Power intent
What is CPF is required for implementation?
RTL CPF
All steps in flow use updated CPF
Libraries Including all previously run verification
Verif Power Intent Entry EDI Physical Implementation
Env
CPF Checking Floorplaning & Power Planning
RTL + CPF Placement & routing
Power aware optimizations, buffering, etc

Verification CPF checking Post Physical

LP Synthesis
Flow Ensures that physical implementation is
Name Logical correct and complete
Functional Verification

Mapping Netlist Power switch network, power connectivity, etc

(Very specific tests)
Gate Simulation

Conformal LP
In Parallel

Structural + Equivalency Conformal LP Equivalency checking

Equivalency checking on CPF+ input RTL vs
synthesized output + CPF
Physical
Implementation
Name
P&R Limited gate-level simulations
Netlist
Mapping Small set of tests to verify LP insertion and
Conformal LP timing
Structural + Equivalency Use name mapping flow

Timing/SI Signoff
Physical Verification
GDSII Timing analysis and signoff
IR drop/power Signoff
Voltage storm IR drop/power signoff

222 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Preparing your design for physical
implementation
Libraries
Do I have all the EDA tool views of the low power library cells?
Power switches, level shifters, SRPG registers, isolation cells etc.
Die Size
Have I included overhead for low power structures in my
physical implementation allotted area?
Power switches, separate power nets, SRPG secondary power pin
routing etc

223 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Implementation Flow (Block-Level
Implementation) optDesign can optimize nets
using always-on buffers
Optional:
MSV prototyping

Scan
Design Import Routing
Definition

Load JTAG/Cell Clock Tree Power Switch

CPF Placement Synthesis Optimization

POST ROUTE
Define Pre CTS Clock Aware Post Route

POST CTS
Add Metal Fill
PRE CTS

SIGNOFF
Floorplan Setup Fixing Scan Re-Ordering Setup/Hold Fixing
INIT

Adjust Power Post CTS Detail (Coupled) Signoff (Coupled)

Domains Setup/Hold Fixing Extraction Extraction

Add Power Power Routing Power Routing Post SI

Timing Analysis
Switches (AO/LS/SR) (AO/LS/SR) Setup/Hold Fixing

Update MMMC
Environment Timing Timing Timing Timing
Met? Met? Met? Met?

Power Planning Optional: Timing Signoff

And Routing Buffer Tree
Synthesis

224 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Read and implement CPF in EDI Flow

Load CPF and do the syntax check

Create power domains
Read CPF rules and commit them (if required)
Replace the assign statement with buffer (PD-aware)
Use always-on buf in switchable power domain for always-on
feedthru
Make Global connection
Connect power, ground, and bias nets
Create MMMC Environment
Read in the timing library if it is not loaded in config
Synthesize the logic for the expression of LP enable signal
Make sure inverters and AND/OR gates are available for synthesis
Make the Tie high/low connection
225 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Floorplan General Recommendations

Avoid large number of small domains

Each domain has overhead associated with placement, routing,
isolation, and level shifting
Typically we see 4-8 power domains in a design
Varies based on design complexity and size
Tools support any number of domains (weve seen up 40+)
Need to tradeoff benefit vs extra overhead and verification
complexity
Functionally large domains can be split
Disjoint Power Domain
Additional Recommendations

226 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Disjoint Power Domain Flow
Disjoint PD: One single and non-default power domain can be
floorplanned into two or more disjoint fences/islands physically
Support Type:
Domain members can be hierarchical instances
(hinsts) and fixed blocks. The hinsts need to be
sibling or non-parent-children relation. Domain
members need to be defined in the CPF explicitly. B+C
Each disjoint region can be rectilinear. (region2)
Disjoint PD
Disjoint regions can not be overlapped.
Assign each hinst to one and only one of the
regions.
Example:
members: A, B, C and block1
A region1
B and C region2 A
Add the box of block1 to the domain floorplan (region1)
Note:
All the command with -powerDomain should support
the disjoint power domain.
For the addPowerSwitch, please use -area and - block1
incremental since we want to add the power
switches into different logic modules for disjoint PD
227 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Floorplan Recommendations
Suggested PD fence floorplan:
Try best to create the rectangular or simple rectilinear shapes with mini PD
boundary edges. This will minimize the crossing-PD route patterns and help
ISO/LS placement.

BAD GOOD

Suggested PD fence floorplan:

Do not block the intra-PD connection by big macro or blockage in the PD
area; otherwise, the intra-PD buffering/routing must go outside the PD.

PD
PD
BAD GOOD

228 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Floorplanning Recommendations (Contd)

Suggested PD fence floorplan:

Best to avoid the floorplan where the inter-PD net routes have to
cross the third non-default PD

PD1 PD1

PD2
PD2

PD3 PD3

BAD GOOD

229 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Floorplanning Recommendations (Contd)
Suggested PD fence floorplan:
Try best to avoid too many narrow channels between PDs to avoid
congestion

Narrow channel between PDs

230 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Switch Insertion
Power switch prototype
Estimate how many power switches
addPowerSwitch
Support column and ring Style
Support different power domain shapes
specific area for column
Specific shape for ring
Place power switch
Column type: checkerBoard, skipRows, power grid
Ring type: pattern control
Chain enables (control rush current, IR drop to other block)
BackToBack
connectBottomSWenablePins
loopBackAtEnd
parallelEnable
Spine chain
Make global connection for the added power switches
Commit level shifter rule for power switch enable nets
Power switch enable net should be always-on
For detailed information, please read the PSO Methodology in
Application Notes

231 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IPO Using Always-on Buffer (Contd)

IPO can automatically pick up always-on buffer

whenever it is needed:
For the net with receivers in the switchable power domain : AO buf is used
to keep the net on when the domain is shutoff by connecting the secondary
power pin to always-on power net. This is used to buffer the always-on nets
such as isolation/SRPG/power switch enables.
For the feedthrough net over the always-on or switchable power domain: AO
buf is used to extend the nets driver/receiver power domain outside by
connecting secondary power pin to the driver power net.
Switchable PD

Always-on PD Always-on buf

232
Always-on
January 31, 2010
buf
Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IPO Using Always-on Buffer (contd)
Features Supported in CPF flow
Define always-on buffers in CPF
Make sure always-on buffer are NOT set to dont_use
Automatically connect the secondary power pin to the primary power net
of the secondary domain if always-on buffer is inserted in switchable
domain and there are receivers in the switchable domain
Automatically connect the secondary power pin to the primary power net
of the drivers power domain for feedthrough buffering
Route the secondary power pin to the power net before signal route step
Run CLP to check the secondary power connection
The feature works for both setup and hold IPO in preCTS, postCTS and
postRoute stages
Manually adding Always on Buffers
addBufferForFeedthrough -net <netname>
[-powerDomain domainName]
-power (net:pin) gorund (net:pin)

233 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IPO Using Always-on Buffer (contd)
LP IPO is now more powerful with always-on buffer
IPO can insert an always-on buffer in the net between isolation/level
shifter and power domain boundary when the isolation/level shifter is not
placed close to power domain boundary near the driver/receiver (see an
example in the next slide)

Power Domain B Power Domain B

Power Domain A Libraries B Power Domain A Libraries B
Libraries A Libraries A

This sub net can be buffered

using always-on buffer

234 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Complete full-chip analysis with Encounter Power System

Signoff-driven implementation
Fully integrated signoff engines

Complete full chip analysis

Coverage of all static and dynamic
aspects of power and rail signoff

Analysis for advanced

technologies
Thermal, variation aware, statistical
leakage power analysis and more

235 2009 Cadence Design Systems, Inc. All rights reserved.

 Signoff Power-Grid Analysis

Two-part approach:

1. Steady-state IR-drop andEM

analysis
Reports IR drop through switches
Reports power switches operating in
saturation
Report used to generate placement ECO
for switch optimization

2. Dynamic IR-drop or Transient

analysis
Reports block power-up time using high
capacity circuit simulation
Too fast impacts surrounding logic
Too slow limits performance
Creates Power Grid View to analyze full-
chip impact of power-up on surrounding
logics

236 September 12, 2011 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Flow Topics

Hierarchical Design flow

Macro Modeling

Domain Mapping

IP Reuse Example

Naming Style Consistency

Name Mapping Flow

237 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Hierarchical Design Flows
Bottom-Up Hierarchical integration
Hard Macro
An IP block is being integrated as a hard macro with internal power intent
The intent is already present, so we need to describe the internal power
architecture to integrate at the top level
Use Macro Models
Hierarchical IP Domain Merging
An IP block comes has a CPF to describe the power intent. This IP block
will be merged into the top level design
The CPF Integrator is used to optimize the CPF for this flow.

CPF features for design reuse

Top Down partitioning flow

Can I partition a top-level CPF into smaller pieces to help with
equivalency checking and design implementation?

238 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Hard Macro Flow
RTL CPF
Lib/
Lef Power Intent Entry
Hard Macro
Design CPF Libraries
Macro CPF Integration

Sim CPF Checking

RTL + CPF
Model

1. Circuit designer creates LP Synthesis + DFT

CPF, simulation, and Logical Netlist
lib/lef models
Testbench Automation
Power Mgmt

Gatelevel Simulation
2. Plugs into Top-down flow
Conformal LP
discussed earlier Formal Analysis Structural + Equivalency
3. Simulation model is
passed to verification env RTL Simulation Physical
Implementation
4. CPF is passed into CPF P&R Netlist
Integrator and merged Acceleration & Conformal LP
Emulation
into CPF used by all tools Structural + Equivalency
5. Lib/Lef are used by Verification Coverage Timing/SI Signoff
synthesis and place and
route. IR drop/power Signoff GDSII
Verif
Env

239 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Hard Macro Flow

Components of the design are hard macros

Vendor Hard macro such as RAM/ROM
Hard IP block
Execute LP design flow on a block
Generate a Physical netlist/database to be used in hierarchical integration in
EDI
User creates CPF macro model to describe the power architecture
CPF integrator is used to instantiate the block CPF into top level
The LP flow remains largely the same as Top-Down flow discussed
earlier
Flow topics
Creating Macro Model Descriptions
CPF Integrator is used to instantiate hard macro in top level
Simulation Models of hard Marcos

240 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Bottom up Hierarchical flow
RTL
SDC

Block level Design

Power Intent Capture
Generate RTL and CPF for the
block CPF
Run LP flow through synthesis, CPF Checking
RTL verification, CLP checking,
CLP LEC. Block Block
Integrate hierarchical CPF into Verification Synthesis
top level CPF
Run top down flow with CPF Checking + LEC
integrated CPF
Synthesis : can use RTL design
CPF Integration
or Gate netlist
Simulation : can use RTL or Top-down LP flow
model of block

241 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Bottom-up Hierarchical Flow
RTL CPF

RTL
Power Intent Entry
Block Design Libraries
CPF
Flow Macro CPF Integration
CPF Checking
RTL + CPF

LP Synthesis + DFT
1. Block Level design Logical Netlist

Testbench Automation
Power Mgmt
flow

Gatelevel Simulation
Conformal LP
2. CPF is passed into Formal Analysis Structural + Equivalency
CPF Integrator and RTL Simulation Physical
merged into CPF Implementation
P&R Netlist
used by all tools Acceleration & Conformal LP
Emulation Structural + Equivalency
3. RTL for block is
Verification Coverage Timing/SI Signoff
used in top-level
runs IR drop/power Signoff GDSII
Verif
Env

242 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Bottom Up Flow

The overall LP flow remains largely the same as Top-

Down flow discussed earlier
Flow topics
CPF Integrator is used to instantiate lower level CPF
Domain Mapping
CPF for IP Reuse
Hierarchical Power Modes
Flow Variations
Using synthesized netlist as input into top-level flow (dont
resynthesize the block)
Running block through full implementation flow
Create a macro model and physical design for integration

243 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Top Down Partitioning Flow Overview
CPF-enabled Partitioning Flow is built on top of the EDI regular
hierarchical flow.
Only available in EDI not for RTL level design
partition the chip into several block-level designs and one top-level design
Generate CPFs for each block and top-level design during savePartition
implement blocks and top independently in CPF (low power) flow
Assemble the block and top-level designs

Load chip-level CPF

Chip assembly
EDI hierarchical flow

Top-level data Load chip-level CPF

Block-level data including CPF
Including CPFs
Chip-level Analysis

Block-level implementation Top-level implementation

in CPF flows In CPF flow

244 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF-Enabled Hierarchical Flow
Design Load top-level

TOP IMPLEMENTATION
Initialization CPF
Pre-CTS
Flow
Post-CTS
Load chip-level Flow
CPF Post-Route
Flow
JTAG / Cell
VIRTUAL PROTOTYPING
Design Import
DESIGN INITIALIZATION

ASSEMBLY & SIGNOFF

Placement Post SI
Setup/Hold Fixing
Load Feedthru
Floorplan insertion Timing
Clock / Latency Partition Pin Met?
Load chip-level
Specification Assignment
Assemble CPF
Timing Virtual IPO /
Design
Setup Budgeting

BLOCK IMPLEMENTATION
Partition Design Signoff Extraction
Partitioning Initialization Timing Analysis
Definition
Pre-CTS
Flow Timing
Met?
Post-CTS
Flow
Post-Route
Flow
Signoff
Load block-level Model
CPF Generation

Timing
Met?

245 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Partition
Load Chip-level CPF to capture the low power intents
Support the following floorplans between partition and power domain
Partition is equal to power domain
Partition is smaller than power domain
Partition is larger than power domain
Perform power domain aware feedthrough insertion
Use regular buffer for the partition which is in always-on domain
Use always-on buffer for the partition in switchable domain
Perform MMMC timing budget
Generate viewdefinition.tcl which includes MMMC timing budget,
MMMC setups and power domain library binding for each blocks
viewdefinition.tcl is sourced during design import
Block and top level CPFs do not need to have view definition
Generate Block-level CPFs and top-level CPF in savePartition step
Assign Power domain attribute to each partition boundary pin
Keep or push down necessary CPF rules at top or into block (iso, ls,
power switch and state retention)

246 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Flow Topics

Hierarchical Design flow

Macro Modeling

Domain Mapping

IP Reuse Example

Naming Style Consistency

Name Mapping Flow

247 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Macro Models

A macro model describes the internal power architecture of a hard

macro
Examples: Memories, I/O, complex IP
It defines:
Internal power domains
Internal power shutoff and control
The power domain associated with boundary ports
State retention
The macro model effects the whole flow
Simulation
Synthesis : Level shifter and isolation insertion
Implementation: Power/ground connectivity
The macro model is read into the higher level designs
Macro level power domains can be merged with higher level domains

248 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Macro Model Examples

Macro Modeling Introduction

Example macro models (TBD)
RAM
ROM
I/O Pad Cells
Flash Memory
PSO enabled macro
MSV macro
Complex macro (PSO + MSV)
Instantiating a macro model in a design
Domain merging using integrator

249 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Macro Model

Accurate simulation, implementation, and verification of custom IP

blocks or macros, such as embedded RAM, can be accomplished
by defining the power features using
set_macro_model <name>
power information content
end_macro_model
This independent definition provides verification and
implementation tools the power information necessary to implement
and verify designs using these custom IP blocks.
Another benefit of the macro model definition is that it allows the
original IP block behavioral model to co-exist with the CPF definition
to enable power aware verification at the design level.

250 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 When to use Macro Models

Define a custom IP block as a macro model it contains one or more of the

following features:
Complete power domain support
internally switchable, externally switchable, un-switched
Power mode definition
Input and output boundary isolation
State retention for switchable domains
Feed-through ports
Floating ports
Input port voltage range tolerance

Macro models must be black boxed for implementation and Conformal

verification, example would be an embedded RAM
Macro models are not black boxed for simulation

251 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Macro Model Example

VDD
D1
Multiple power ports (VDD, VPP)
iso1
Switches Different types of domains
iso2 Un-
switched Internally Domain with retention

Isolation
ret (AON) Switched
pwr (PSO)
D4 Domain without retention
State Inputs isolated (D3)
D2 Retention
Inputs not isolated (D2)
Isolation
Outputs isolated (D4)
Outputs not isolated (D5)
Isolation

D3
Externally
D5
Internal crossing with isolation
NC Switched
(EXT) Feed-through (F1, F2)
F1
Floating port (NC)
F2 VSS VPP

252 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Top Level CPF
VDD
set_design top

create_power_domain name PDBlue default

VDD
update_power_domain name PDBlue \ I1 D1
-primary_power_net VDD \ Un- iso1
switched Switches
-primary_ground_net VSS iso2 Un-
(PDBlue) switched Internally

Isolation
ret Switched
(AON) D4
create_power_domain name PDRed \ pwr
State
shutoff_condition pso \ D2 Retention
Switches
-default_isolation_condition I1/iso1 \ Isolation
Internally
Internally
-base_domains PDBlue Switched
Switched
-instances

Isolation
(PDRed) D3 Externally
State Switched
NC (EXT) D5
update_power_domain name PDRed \ Retention
F1
-primary_power_net VDD_SW
-primary_ground_net VSS F2 VSS VPP

end_design

253 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Domain Mapping
VDD

set_design top
create_power_domain name PDBlue default

VDD
update_power_domain name PDBlue \
D1
-primary_power_net VDD \ Un- iso1
switched Un- Switches
-primary_ground_net VSS iso2 Always
switched
(PDBlue)

Isolation
On
(AON) Internally
ret
create_power_domain name PDRed \ pwr
Switched D4
State
shutoff_condition pso \ D2 Retention
Switches
-default_isolation_condition I1/iso1 \
Internally
-base_domains PDBlue
Switched

Isolation
-instances (PDRed)
Externally
D3 Externally
Switched D5
State NC Switched
(EXT)
update_power_domain name PDRed \ Retention F1
-primary_power_net VDD_SW
F2 VSS VPP
-primary_ground_net VSS

set_instance ipInst domain_mapping \

{ {AON PDBlue} {EXT PDRed}}
VSS
include macro.cpf

end_design

254 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 How the macro model information is used at top
level implementation? connect power
VDD
no isolation needed: the driver is already
isolated

no isolation needed: there is no domain

crossing, i.e. both drivers and receivers are VDD

in the same domain D1

Un- iso1
switched Switches
iso2 Un-
isolation may be needed: if the driver (PDBlue) switched Internally

Isolation
ret
domain can be off while the receiver is on, (AON) Switched
D4
pwr
need to have an isolation rule at top level for State
isolation insertion Switches D2 Retention
Isolation
Internally
Internally
Internal Isolation: Any isolation rules that are
Switched
Switched
between internal domains are ignored. The

Isolation
(PDRed) D3 Externally
behavioral mode needs to model these Switched
State NC (EXT) D5
Retention
F1
No isolation needed: pin D3 is isolated
F2 VSS VPP
internally and the crossing is not a domain
crossing because domain PDRed merged
with domain EXT
VSS
No isolation needed: NC is a floating pin
No isolation needed: F1 and F2 are internal
feed-through. At top, the driver and receiver connect ground
255 January 31, 2010
of the net are in the same domain
Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Macro Model Guidelines

Make sure all input and output pins are assigned to the
correct domain
An input pin assigned to a domain means the logic driven by
the input pin inside the macro cell takes the power supply from
this domain
An output pin assigned to a domain means the logic driving the
output pin inside the macro cell takes the power supply from
this domain
If a domain contains registers defined in the behavioral
model, declare the registers in the domain definition using
instances option
Do not make an internal switchable domain as the default
domain for the macro model.
Choose an un-switched domain or an external switchable
domain as the default domain of the macro model
To avoid power shutoff behavior applied to unexpected behavioral
code during simulation

256 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Level Shifters Within Macro Cell

There is no need to describe level shifters between internal

domain crossing.
To describe level shifters at the boundary ports a macro cell,
assign the port to the proper power domain in the macro model
Do not create level shifter rules in a macro model
See also the slide Macro Model Basics
VDD_EXT VDD

Declare port O
Declare port I belonging to the
belonging to the power domain
power domain corresponding to
corresponding to VDD_EXT
VDD_EXT I
Core
O

level shifters
257 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Flow Topics

Hierarchical Design flow

Macro Modeling

Domain Mapping

IP Reuse Example

Naming Style Consistency

Name Mapping Flow

258 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Domain Mapping

A lower scope domain is merged to a higher scope with domain mapping

For a Hard IP (Custom) with a P&R netlist
Domain mapping specifies the top level domain that powers the block domain
Domain mapping guides the connection and verification of the top level domain
power/ground nets to the block level domain power and ground pins.
Simulating the behavior of power domains is via domain mapping, eliminating the
need for the RTL model to incorporate physical power and ground connectivity.

259 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Example: Before Integration

set design Top Switch

Always
On Internal
Switched

X1 X2

I1 I2 I1 I2
Iso Rule

Iso Rule
Always External Always External
On Switchable On Switchable

set design Block1 set design Block1

set_design Block1 ports { IsoExt }

create_power_domain name On instances { I1 }
create_power_domain name Ext external_controlled_shutoff instances { I2 }
create_isolation_rule -name Iso1 from Ext to On isolation_condition IsoExt
end_design
set_design Top ports { Iso Pwr }
create_power_domain name AON
create_power_domain name Int shutoff_condition { !Pwr }
set_instance X1 domain_mapping { { On AON } { Ext AON } } design Block1 \
set_instance X2 domain_mapping { { On AON } { Ext Int } } design Block1 \
-port_mapping { {IsoExt Iso} }
end_design
260 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Example: After Integration

Top Switch
Always
On Internal
Switched

X1 X2

I1 I2 I1 I2

Iso Rule
Always Always Always Internal
On On On Switched

Block1 Block1

set_design Top ports { Iso Pwr }

create_power_domain name AON instances { X1 X2/I1 }
create_power_domain name Int shutoff_condition { !Pwr } instances { X2/I2 }
create_isolation_rule name X2_Iso1 from Int to AON isolation_condition Iso
end_design

low level blocks are integrated

low level isolation rule is
to domain definition at top
deleted at top due to domain
reconfiguration low level isolation rule is
promoted to the top

261 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Hierarchical CPF Integration

CPF 1.1 feature support of hierarchical integration

Domain mapping guides merging of lower scope objects to higher scope
Port mapping guides connections of lower to higher scope control signals
Parameter mapping guides reconfiguration of lower scopes parameters to higher
scopes for individual instances of lower scopes
Automatic rule optimization based on mapping of power domains which may
eliminate isolation, level shifter, switch cell, or retention cell insertion requirements
due to design level power mode configuration and design level domain crossing
environment for individual instances of lower scopes.

262 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Flow Topics

Hierarchical Design flow

Macro Modeling

Domain Mapping

IP Reuse Example

Naming Style Consistency

Name Mapping Flow

263 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IP Reuse Example

An IP with the following specification

Have a single power domain
The power domain may be shutoff by external power control
When the IP is shutoff, some of its states require state retention
The IP supports two types of state retention strategy
single retention control, with only restore pin
dual retention control, with both restore and save pin
IP usage
IP is instantiated twice at top level
one in an always-on domain
one in a switchable domain

264 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Reusable IP Example IP description

myIP
externally Specify virtual ports: port save and
Switched restore do not exist in RTL

State
Retention
Specify parameters: declare parameter
one_ctrl with default value 0.
set_design myIP -ports { save restore} \
-parameters { {one_ctrl 0}}
create_power_domain name PD default \ externally switchable domain
-external_controlled_shutoff
if { [get_parameter one_ctrl] == 0 } {
create_state_retention_rule name sr\
Use parameters: use the parameter
instances foo*\ like a string variable
-save_level save restore_level restore
} else {
create_state_retention_rule name sr \
instances foo* \
-restore_edge restore
}
end_design

265 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Reusable IP Example IP Usage
configure the IP to specify the top level use the IP in a
use single control driver for the virtual switchable domain
retention (overwrite the ports
Instantiate IP CPF model
default parameter value)
include myIP.cpf ;#load in the CPF model for IP
I1 set_design top
top create_power_domain name PDBlue default
myIP1 create_power_domain name PDRed \
internal shutoff_condition pcm/pso base_domains PDBlue
set_instance I1/myIP1 design myIP \
switchable -domain_mapping { {PD PDRed}} \
pso myIP2 -port_mapping { {restore pcm/restore}} \
PCM -parameter_mapping { {one_control 1}}
restore
set_instance myIP2 design myIP \
domain_mapping { {PD PDBlue}}
always-on
end_design

Instantiate the same IP CPF

use the IP in an
model in another instance
always-on domain

266 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Equivalent Flat CPF
include myIP.cpf
set_design top Top Level Flattened CPF
create_power_domain name PDBlue default set_design top
create_power_domain name PDRed \
shutoff_condition pcm/pso base_domains PDBlue
set_instance I1/myIP1 design myIP \ create_power_domain \
-domain_mapping { {PD PDRed}} \
name PDRed \
-port_mapping { {restore pcm/restore}} \ domain mapping
-parameter_mapping { {one_ctrl 1}} shutoff_condition pcm/pso \
set_instance myIP2 design myIP \ instance I1/myIP1
domain_mapping { {PD PDBlue}}
end_design
domain mapping
create_power_domain \
Top Level CPF name PDBlue default \
-instance myIP2

IP Level CPF create_state_retention_rule \

set_design myIP -ports { save restore} \
-name myIP1_sr \
-parameters { {one_ctrl 0}}
create_power_domain name PD default \ -restore_edge pcm/restore
-external_controlled_shutoff -instances I1/myIP1/foo* \
if { [get_parameter one_ctrl] == 0 } {
create_state_retention_rule name sr instances foo*\
-save_level save restore_level restore end_design
} else {
create_state_retention_rule name sr instances foo* \ Note: the state retention rule for the
-restore_edge restore
instantiation of myIP2 is removed since the
}
end_design block level domain is mapped to an always-
on domain at top.
267 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Top Level Integrated View

top I1 I1
top
myIP1 myIP1
internal
switchable

pso myIP2
PCM pso myIP2
restore PCM
restore

always-on always-on

Before Integration After Integration

268 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Flow Topics

Hierarchical Design flow

Macro Modeling

Domain Mapping

IP Reuse Example

Naming Style Consistency

Name Mapping Flow

269 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 How to configure Naming Styles to avoid
Issues
Problem Statement:
The CPF file is consumed by multiple tools. It creates a unique
requirement that the same source needs to apply to both
simulation and implementation tools internal databases
Synthesis and Equivalency checking tools has many options for
how to create the names for different objects:
Register naming
Hierarchy separator
Generate naming style
Parameterized designs
Simulation based tools adhere to a strict interpretation of the RTL
language reference manuals(LRM)
Solution
Configure each tool to use a consistent naming style

270 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Naming Style why is this an issue now?

CPF +
RTL
In the past, RTL simulation and synthesis
had very little interaction
Only the RTL was shared, no need for Switching
consistent naming Activity
RLT
Low Power Sim
RC
Common power intent as input to both sets of
tools Netlist
Names in the CPF must be matched to names
in the tools database Gate
CLP
Needs to be consistent as possible Sim
Power analysis flow passes switching activity SDF
between tools and successful name mapping Backannotation
is required to get good results
Common differences
Generate loops
VHDL records
Array indexes

271 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Guidelines
Use LRM naming style in all tools
Today most implementation tools default to non-LRM compliant
naming styles
The simulation tools are strict about LRM
The easiest way to be compatible is to standardize on LRM
What about cases where the backend flow requires a
specific naming style?
Use Change names to modify the naming style just prior to
output of a netlist
Traditionally many users would use the synthesis tools input
naming style to create the names correctly up front
Moving this step to the output ensures that the CPF can be read in
correctly, without the need for CPF to support all possible name
changes
Use the CPF name mapping flow if required.

272 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Recommended Naming Style Settings

CPF Naming
Hierarchy separate can be either . or /
set_hierarchary_separator .
set_hierarchary_separator /
Field/record separator used needs to be .
Ex: create_state_retention rule instances {a/b/c.field1} .
RTL Compiler naming
set_attr hdl_generate_separator / /
set_attribute hdl_record_naming_style "%s.%s" /
set_attribute ungroup_separator /
Set_array_naming_style [%d]
Conformal Naming
set naming rule "%L/%s" "%L[%d]/%s" "%s" -instance
set naming rule "/" -hierarchical_separator
set naming rule "." "" -field_delimiter
set naming rule [" ]" -array_delimiter

273 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Flow Topics

Hierarchical Design flow

Macro Modeling

Domain Mapping

IP Reuse Example

Naming Style Consistency

Name Mapping Flow

274 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF name mapping flow

What is naming mapping used for?

The CPF flow is designed around a Golden CPF file that is used though out the
verification and implementation flow
The name mapping flow handles the cases where synthesis makes changes to
the design and the naming of objects that need to be reflected in the CPF
Ungroup, change_names, uniquify
No changes to the power intent, just the naming of objects

Flow Description
Golden CPF read into RC
All information of name change is maintained and written to a name mapping file
by RTL Compiler
Other tools read the name mapping file and recognize the changes to names
when reading the golden CPF

275 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF name mapping flow
CPF quality check
Conformal Low Power

CPF based Logic simulation

Incisive Design Team Simulator
All information of name
CPF based logic synthesis and DFT change is maintained in
Encounter RTL Compiler
CPF Power Intent)

a name mapping file

CPF based equivalence check
and LP verification Conformal Low Power created by RTL Compiler
CPF based physical implementation

Name Mapping File

SoC Encounter

CPF based equivalence check Other tools read the

and LP verification Conformal Low Power name mapping file and
CPF based ATPG recognize the change
Encounter Test

CPF based timing sign-off

Encounter Timing System

CPF based leak power/temperature analysis

Encounter Timing System

CPF based IR-Drop, power sgn-off

VoltageStorm-DG

276 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF name mapping flow
e.g. output from RC
read_cpf -library test.cpf
A name mapping file
read_netlist test.v
read_cpf test.cpf

set_attr output_name_mapping_file test.nmf top

set_attr name_mapping_record_name_changes true top
set_attr name_mapping_version 1.0 top
Once design object name is
change_name -pre pre_
change_name -suf _suf changed during synthesis,
ungroup [find / -inst *sub_2*] the name mapping file is
write_hdl -m > changed_name.v updated.
e.g. input to RC
read_cpf -library test.cpf
read_netlist changed_name.v
read_cpf name_mapping_files test.nmf test.cpf

277 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Name Mapper Flow

e.g. input to IES

Add the following to the irun command line:
irun -name_mapper_file <filename>

e.g. input to CLP

read cpf name_mapper_file test.nmf test.cpf write_do_clp

e.g. input to SoCE

EDI9.1(TO be released at the end of Dec, 2009

278 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Limitations
RC
NMF tracks only name change due to
mv
change_name
ungroup
NMF does not track name change due to
Verilog(parameter)/VHDL(generic)
Group (edit netlist or during elab)
Bit blasting
Retiming
Multi-bit flop inferencing
change_link
encrypt
IUS
Current release does not support hierarchical flow with name changes.
Example of unsupported design:
Design has multiple instances at the top level, and each instance has a name
mapper file, or
The top level has its own name mapping file
279 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Guidelines

CPF coding Style

TCL Tips

RTL Coding Style

CPF Language Details

280 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF Coding Guidelines

Recommended structure for CPF file

Using Environment Variables
Using Wildcards
Complex expression used in CPF control conditions
Special Characters and Array Naming
Array Naming Style
Handling array of records in VHDL + CPF
Hierarchy Separator Character
Understanding Rule precedence and organization
Equivalent pins and what how to use
Using Include or Source to load multiple CPF files
281 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Recommended CPF File Structure

Use the same set of CPF files for all tools

Use Revision control for the CPF file
Use multiple CPF Files to more efficiently organize and maintain the
CPF
Testbench level CPF file
Library and technology data
Low power Design Intent
Physical Implementation details
Low Power Design Intent
Group related commands
Nominal Conditions
Domains definitions
Power modes and transitions
State retention, Isolation, and Level shifting rules
Physical implementation related
PSO example

282 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Revision Control
The CPF file must be under revision control
The same CPF is used for the entire flow
Multiple groups/users will add their flow specific content to the file
Without revision control it is easy for changes to be missed or
overwritten between groups
Recommend CLP as check-in criteria
Users should ensure any changes to the CPF are clean before check-in
Recommend periodic review of check-ins and clear ownership
We have seen cases where one group deletes lines of code that are not
needed for its tool but are required for others
Physical design team changes power modes without informing RTL
team
RTL team changes domain definitions and impacts backend teams
physical design
Separate files for different tasks/ownership will assist in this process
Front end vs library vs implementation CPF

283 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Testbench CPF File

Creating a testbench CPF allows the DUT CPF file easily be used in
the verification environment
Allows multiple instances of the DUT in the verification environment
Handles the different instance paths between implementation and
Verification
DUT top but in verification env, the instance may be
testbench.main.top
Testbench CPF
Instantiates the common design CPF
set_cpf_version 1.1
set_design testbench.system.top testbench
set_instance dut_inst
source dut.cpf
The -testbench option relaxes the requirements for the specification of
a default power domain and default power modes
It was designed specifically to simplify the use of the common design CPF in
the simulation environment.
Use Environment variables if necessary

284 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Using Environment variables for CPF paths
The CPF can be written such that environment variables are used to
provide proper paths
This allows the CPF to be used in verification and in implementation
Note: using the testbench CPF style is recommended for most cases
Note: Be very careful about the use of environment variables. Do not
use them to specify different power intent. (like state retention, isolation,
etc) Improper usage can result in simulation not verifying the same
logic as the hardware, resulting in chip failures

csh>setenv TOP test.dut.foo

cpf>set_design $env(TOP)
test
or
dut
csh> setenv TOOL NCV
Cpf> foo
if {$env(TOOL) == NCV) } {
set_design test.dut.foo
} else {
set_design module_foo
}
285 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Using Wildcards in the CPF
Wildcards can greatly simplify the CPF specification
CPF supports a wide range of wild card specification
CPF supports wild cards for most references to design objects
Pins, ports, instances, power_domains, and rules
On arguments that are CPF rule names
Update_isolation_rule name ISO* cells ANDX
CPF supports * and ? as wild cards

Guidelines
Avoid overly general wild cards
they can match more than expected and cause errors that are difficult to find
Wildcards are supported in leaf level hierarchy by all the tools
A/B/C* and A/B/C*D are supported
Note: Please check the KPNS document for known limitations on wildcard
CPF wildcard matching does not support matching the hierarchy separator
a/b/c* will match a/b/c1 but not a/b/c/d
Wildcards can not be used in control expressions
-shutoff_condition, -isolation_condition, -save_edge/-restore_edge, etc.

286 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Understanding Rule Precedence in CPF
Specific rules have precedence over generic Rules
Click here for definition of generic vs specific
A more specific rule has precedence of a less
A rule with both from and to has precedence over one only having
to or from
Lower level hierarchy rules have higher priority
Lower level rule always will overwrite any top-level rules on the same
object
Lower level rules only apply to logic within that lower level hierarchy
and are never propagated up to other logic.
Given rules of the same priority
The last rule wins
Known Problems:
Please refer to the KPNS for known limitations on Rule Precedence.
Rules this applies to:
Create_state_retention_rule, create_isolation_rule
Create_level_shifter_rule, create_power_switch_rule

287 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Generic vs Specific rules (from CPF reference
manual)

Specific rules explicitly specify the targeted design objects. For

example,
Isolation or level shifter rules specify the targeted design objects with
the pins option.
State retention rules specify the targeted design objects with the
instances option.
Generic rules do not explicitly specify the targeted design objects,
but the targeted design objects can be derived from some option
specified with the rule. For example,
Isolation or level shifter rules specified with -from or -to options target
those net segments driven by logic in the domains specified with the -
from option or driving logic in the power domains specified with the -to
option.
State retention rules specified with the -domain option target all
registers or sequential instances in the specified power domain.

288 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF Coding
Control Conditions

Keep expressions simple in control conditions

Isolation_condition, save_edge, restore_edge, shutoff_condition, etc
This simplifies the modeling in all tools, and CPF creation
Ensures the tools have the same interpretation of the data
CPF expressions support
Only the following operators are officially supported: &, |, !
Unsupported: xor/xnor, reduce and/or/xor,
Use set_equivalent_control_pins
Instead of a complicated expression, one can used equivalent pins
Instead of : -shutoff_condition { A|B|C|D}
Use: -shutoff_condition {A}
set_equivalent_control_pins master {A} pins { B C D}

289 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Array Naming Remember to escape bus
indexes {a[0]}

When referring to a bus/array index using signame[0], TCL

requires the [0] to be escaped to prevent execution of the
command 0
There are several method for escaping the name:
Recommendation: use Braces to escape:
create_isolation_rule name ISO1 isolation_condition {a[0]}
Other methods include using \
create_isolation_rule name ISO1 isolation_condition a\[0\]
Both methods are valid, but the braces are easier to specify
if you are using a list of elements or multi-dimensional array:
Ex: { a[0] a[1] b[0][1] b[1][0] } is more clear than
a\[0\] a\[1\] b\[0\]\[1\] b\[1\]\[0\]
This is a common question due to the fact that some EDA tools will
allow the brackets despite the fact that this violates the TCL spec.

290 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Array Naming Style

Array naming style defines how RC generates the names in the

netlist
Set_array_naming_style [%d]
The CPF file contains the original RTL name of the nets/objects
Name mapping Flow is used to reflect the changes
When RC changes object names, the changes are reflected in a name
mapping file. So you dont need to modify CPF.
Name changes by ungroup / change_name / mv are save in a name
mapping file.
After name change, use
Original CPF and
A name mapping file (including change_name)
Note:
When you expand ports with RC command edit_netlist
bit_blast_all_ports, the change is not saved in a name mapping file. In
these cases, the CPF would need to be modified. (this is not a
common user flow)

291 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Wild cards and Arrays
Instance name, module name and port name described in CPF are
design objects.
These often use [ ] as indexes into arrays.
RTL case,
reg [5:4][3:2] c;
reg c1;
Matching multiple Registers (both c1 and c array)
create_state_retention_rule name ret instances c*
As shown in a example above, wildcard can be matched to bus
delimiter.
Matching entire array c
create_state_retention_rule name ret instance c
Matching by first array index (only c[5][3] and c[5][2])
create_state_retention_rule name ret instance c[5]
Matching by second array index (only c[5][3] and c[4][3])
create_state_retention_rule name ret instance c[*][3]

292 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Handling an Array of Records in VHDL + CPF
The default naming style is different for RC, CLP vs IES for arrays of
records
RC/CLP use : path/data[0][field][0]
IES uses: path/data[0].field[0]

Example code:
type myData_Type is
record
PADDR: Std_Logic_Vector(PAMAX-1 downto 0);
PWDATA: Std_Logic_Vector(PDMAX-1 downto 0);
end record;

entity apbmst is
port (
data : out myData_Type(0 to 3);
);
end;

To be able to correctly reference the record throughout the design

flow, use the following tool options:
[RC] set_attribute hdl_record_naming_style %s.%s

[CLP] set naming rule "." "" -Field_delimiter

[CPF] create_isolation_rule -name iso1_l -from PD1 -to PD0 -isolation_condition "!iso" -
isolation_output low -exclude { leon0/mcore0/apb0/datai[0].PADDR.[*] }

293 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Handling Special Characters in CPF
The RTL or netlist may have TCL special characters in hierarchy and
instance names
Types of characters:
List specifiers: , { }
Tcl processing: $, [ ]
Escaped names in the RTL
The RTL allows special characters in the instance and net names when they are
escaped with a \
Escaped names from ungrouping logic during synthesis
When a hierarchy is ungrouped the hierarchy separator character becomes part of the
instance name and does not actually mean a separate level of hierarchy
\top.xy.z is a cell at the top level hierarchy
top.xy.Qis a hierarchical path
In the CPF, there are two methods to escape these special characters
Recommendation: Use { }
Any name inside of the braces will be escaped, its easy to read
Alternative: Using the \
Create_isolation_rule name ISO1 pins { top\[x\].xy.z}
Note: the TCL \ is different then Verilog.
The TCL version only effects the next character.
Verilog version will escape all characters from that point forward.

294 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Hierarchy Separator Character

Recommendation:
Use same hierarchy separator character for all CPF files
The hierarchy separator is scope sensitive, but it is often
confusing to debug designs that change the hierarchy
separator often

295 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Using Include and Source to load multiple CPF
CPF provides two method for loading additional CPF files
Source
The standard TCL method for loading files
Searches for include files relative to the current working directory
Include
A cpf extension to the TCL source modeled after the include in verilog
Search for the included file relative to the current CPF file
Ie. If file a/b/top.cpf include bottom.cpf, it will search in the same directory as the top(a/b )
for bottom.cpf
Recommendations
Use Include to make the CPF more portable
Source often requires the top level CPF to know the location in the file system of the other CPF files.
Typically needs the use of environment variables to make portable

Current directory: <run_dir> Current directory: <run_dir>

<my_dir>/design/top.cpf <my_dir>/design/top.cpf
source ../lib/library.cpf include ../lib/library.cpf
source blocka.cpf include blocka.cpf
Looks for the following files: Looks for the following files:
<run_dir>..//lib/library.cpf <my_dir>/lib/library.cpf
<run_dir>/design/blocka.cpf <my_dir>/design/top.cpf
To get to the files you need:
Source $my_dir/../lib/library.cpf
Source $my_dir/design/blocka.cpf

296 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Guidelines

CPF coding Style

TCL Tips

RTL Coding Style

CPF Language Details

297 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 TCL Tips

Using the line continuation character

Errors often have an error messages like:
([CPF-LINT-121]: Unknown command '-state'.).
Missing line continuation character
create_isolation_rule name ISO to PDA
-isolation_condition iso_cond
Blank line after line continuation
Create_isolation_rule name ISO to PDA/

-isolation_condition iso
Matching { and }
A common TCL error is to have unmatched curly braces
The error is sometimes difficult to debug
Several existing tools and editors have a TCL mode that can be used to highlight
the beginning or end of a pair of braces.

298 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Using Variables in TCL

Environment Variables
$env(ENV_VARIABLE_NAME)
Check existence of environment variable
If [info exists env(MY_ENV_VAR)] { puts exists}
Using Variables in lists
Use
Set tmp $var1/b $var1/c
Note: {$var1/b $var1/c} is not the same. The curly braces escape
the $ character, so these will not be expanded.
Note: If you need to use [] as well, then escape these characters
Ex: set tmp $var/b\[1\] $var/b\[2\]

299 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Guidelines

CPF coding Style

TCL Tips

RTL Coding Style

CPF Language Details

300 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 RTL Coding Guidelines

RTL vs Physical hierarchy

Clock Gating
Initial Block Replay
LP Behavioral Modeling
Naming Conventions
Control Signals and Test Signals
Language Style
Avoid Large delays in initial blocks

301 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 RTL Coding Guidelines
RTL Hierarchy

Align Logical and Physical

This is a general guideline for design.
Simplifies specification of power domains
Improves ECO flow
Verification and diagnosis of problems is easier
Align Physical hierarchy to Power Domains
CPF supports all variations
Power domains can be split over several physical regions
This has some advantages in terms of quality of results
See disjoint power domain flow
Power control Logic
Separate power control logic into its own hierarchy block
CPF requires the power control logic to be specified on hierarchical pins
Ensure that module is not in the same domain as the logic it controls.
Ensure that the power control logic is observable and controllable for
test

302 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 RTL Coding Guidelines
Clock Gating
Power Shutoff
Gate clocks for all power shutoff regions
Gating should start prior to isolation
This ensures the internal logic has the expected state before shutoff
Gating saves power
The clock line consumes a large % of total dynamic power. Even if the power is off, the clock
drivers would see the load
Dynamic Voltage
Gate clocks during voltage transitions
This is not a strict requirement, but it can ensure that no data is lost during the transition
Standby Mode
Gate all clocks for standby domains
This is obvious as a standby domain would lose all of its state if the clock were not gated.
State Retention Cells
Many libraries require that the clock to state retention cells be held to a specific value during
power shutoff.
While we try to avoid technology specific information in the RTL, this is a case that it may be
required.

303 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 RTL Coding
Naming Conventions

Consistent naming style for registers that require state

retention
Simplifies the specification of create_state_retention_rules
Consistent naming of I/O ports active level
Simplify isolation rules, and allow greater use of wildcards
Create_isolation_rule from A pins instA/*_low isolation_type
high

304 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Initial Block Replay

Initial blocks are not replayed automatically after power shutoff

This can often lead to some signals remaining corrupted after a

power shutoff block is powered up.
In many cases, the initial block is used to setup signals used as
constants.

CPF provides an initial_block_replay feature to indicate that

certain blocks should be replayed at power up.
# replay the initial block in the FLASH that initializes the data
set_sim_control -target rom_init -action power_up_replay -modules FLASH
-controlling_domain xFLASH/PD_FLASH

USE WITH CAUTION

This feature can cause potential mismatch between simulation and
Hardware
Use only when can be guaranteed that replaying this logic will match
the hardware behavior.

305 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 RTL Coding
Control signals and Test

When using third party test tools

Most other tools do not understand the test control logic, and will toggle control
signals during scan.
This can have serious side effects like:
Turn off/on power during scan shifting.
Turn off/on isolation
Restore saved values on state retention registers
This can cause a lot of unexpected problems on the tester
Switching activity
Power consumption due to turning on/off power
Scan test failures
Please refer to the tools manual for their recommended solution
In many cases, it will involve gating the control signal with test mode
ex: iso_en = test_mode ? Iso_in : 1'b0;

NOTE:
Encounter Test is fully power aware and designs a power test access
mechanism to ensure that these control signals are stable during power shutoff.

306 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 RTL Coding Style
Language
System Verilog
System Verilog interfaces and modports at power domain boundaries are
supported
All other system verilog constructs and data structures cannot be part of power
down domains

VHDL
Integers, enumerated types, real cannot be corrupted to xs
In IUS 8.2, these corrupt to their DEFAULT value
The default is often the reset state, and in some cases can cause the corruption
to essentially go undetected
In IUS 9.2 and later the corruption is more advanced
Using ranges for integers helps ensure a valid value during corruption
This is particularly important for integers used as an index into an array
SystemC
System C constructs cannot directly touch power shutoff domains. For System C
testbench please use a buffer to isolate the system C from the shutoff.
AMS
Only digital components are supported as part of power shutoff. Verilog or VHDL
AMS components will not be placed in power shutoff domains.

307 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Avoid large delays in initial block

Initial blocks with large delays can not always be

replayed after power shutoff
// e.g. Cannot be executed when power off and on happens before time 100
initial begin :case01
#100 sig1=sig2;
end

Workaround
Disable the initial block on power down
reg pdown;
initial
$lps_link_power_domain_powerdown(pdown);

always @(posedge pdown) begin

disable case01;
end

308 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 LP Behavioral Modeling Examples/guidelines

The following two examples are simplified to show the

behavioral modeling ROM and Flash memories
The actual macro model used in a typical design flow will be
more complex and typically include multiple power domains and
boundary port modeling.
More detailed examples are available from Cadence.
Examples:
ROM
Flash

309 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 ROM Simple Example: //Top verilog
Module Top ()
Desired behavior: ROM ROM1 ()
Entire ROM corrupts when PD_SW powers off .
Endmodule
On power up, the ROM contents should be
restored to original values
// Sample ROM behavioral Model
Solution: Module ROM (Addr, CEb, Din)
Define the ROM to be part of PD_SW power ///Port and variable declarations omitted
domain
PSO modeling will automatically model corruption always @(Addr or CEb or Din)
when PD_SW powers off begin
Use initial_block_replay to reload the contents if (!CEb)
of the ROM at power up begin // read cycle
Specifies that an initial block in the RTL needs to Dout_internal <= ArrayReg[Addr];
be replayed on power up end
The initial block is loads the contents of the ROM else if (CEb)
begin
Dout_internal <= 32'b0;
end
end

assign Dout = Dout_internal;

#TOP.cpf
Create_power_domain name PD_SW initial
-shutoff_condition {pso} begin: rom_init
-instances {ROM1} $display ($stime,": Initializing ROM core");

set_sim_control -modules ROM // read in the ROM data file

-target rom_init $readmemh ( "../testbench/data_file",
-action power_up_replay xROM.ArrayReg);
-controlling_domain PD_SW end

310 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF Modeling of a FLASH Memory

A flash memory needs to behave in the following way:

When powered off, the logic needs to be corrupted for simulation
After power on, the contents are before power shutoff

For this example

Cadence power aware system tasks are used to register for the power
shutoff event
At power shutoff, the contents of the FLASH are written to a file.
The CPF initial_block_replay features is used to reload the FLASH
The cpf command set_sim_control -action power_up_replay is used to
replay an initial block that loads the contents of a file

The example shows the CPF and RTL code needed

311 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Flash Memory Example
Verilog code to save/restore flash

set_macro_model FLASH
Define a simple macro model
# Definition of power domains to include boundary ports and state for the FLASH memory
registers
create_power_domain -name PD_FLASH default
-external_controlled_shutoff

create_state_retention_rule -name SR1 \

-instances State_test_reg \
-restore_edge restore_state_reg
Use Domain Mapping to map
end_macro_model the FLASHs domain to the
top-level domain
create_power_domain -name PD_default -default
create_power_domain -name PD_flash -shutoff_condition pso

create_isolation_rule -name ISO_SRAM1_OUT -from PD_flash \

-isolation_condition iso -isolation_output low Use initial_block_replay in
CPF to load the memory on
set_instance xFLASH -domain_mapping { {PD_FLASH PD_flash} } power up.
source ../cpf/flash.cpf

# replay the initial block in the FLASH that initializes the data
set_sim_control -target rom_init -action power_up_replay -modules FLASH
-controlling_domain xFLASH/PD_FLASH

312 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Flash Memory Example
Verilog code to save/restore flash
Module xFLASH ()
..
// RTL for flash memory not included.
reg [31:0] ArrayReg [0:1023]; /// Memory Array Get this modules enclosing
. power domain
// additional code to store the contents of the FLASH memory before shutting down
reg [1:512*8] pd_reg="";
reg link_pd_arrayreg;
initial
begin Register for power shutoff
$lps_get_power_domain (pd_reg); // this returns the power domain name
$display("Power domain of ArrayReg is: %0s",pd_reg);
events for this modules
$lps_link_power_domain_powerdown(link_pd_arrayreg, pd_reg); domain
end

integer i;
always @(posedge link_pd_arrayreg) On Power shutoff save the
begin
data_file_tag = $fopen("../testbench/data_file","w"); contents of the Flash to
$display ($stime,": Saving contents of ArrayReg in file"); memory
for (i=0; i<1024;i=i+1) begin
$fwrite(data_file_tag,"%h\n",ArrayReg[i]);
end
$fclose(data_file_tag);
end

initial
begin: rom_init Use initial_block_replay in
// read in the FLASH data file
$display ($stime,": Initializing FLASH core"); CPF to load the memory on
$readmemh ( "../testbench/data_file", xFLASH.ArrayReg); power up.
end

313 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Low Power Guidelines

CPF coding Style

TCL Tips

RTL Coding Style

CPF Language Details

314 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF Language Details

Library + Tech

Update Commands for Physical

Power Network and Switches

Details on select CPF commands

315 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Library CPF
Vendor provided library CPF
Ideally vendor provide a technology CPF file
Advantages: maintained and verified by ASIC vendor
Conversion from Liberty
In some cases, the vendor has placed the low power attributes in the liberty
format
Conformal Low Power has a utility to translate that liberty information into CPF
read library <> -liberty -lp
write power intent Library.cpf -cpf lib
Creating a Library CPF using Power Intent Architect (PIA)
PIA provides a very intuitive GUI driven method for creating the library CPF
Reads Liberty format and guides the user to correct syntax and settings
Include some slides to show how, and why this is useful
Manual Creation
A CPF file can be created by hand to describe the low power cells.
A person familiar with the library can typically do this with little effort
Conformal LP can be used to check the library and CPF are consistent

316 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Nominal Conditions create_nominal_condition
Create_nominal_condition
Voltage: Defines the voltages used in this design
Used to specify allowed voltages per domain (modes) and defining analysis views
State : Assigns a domains state for the voltage: (more info)
On normal operating voltage
Off domain is considered shutoff
Standby domain is operating at the minimum voltage that it can maintain state, but not calculate new values
Specify any bias on the voltage
Update_nominal_condition
Associate a library set to the nominal condition
Used by implementation and analysis tools to link in proper libraries

# Command: create_nominal_condition
# Define the set of voltages to use and define the domain state
create_nominal_condition -name high -voltage 1.3 -state on
create_nominal_condition -name V11 -voltage 0.7 state standby
create_nominal_condition -name shutoff -voltage 0.0 state off

# Command: Update nominal Condition

# Associate library set to use for a specific nominal condition
update_nominal_condition name V11 library_set V11_lib_set
Implementation
Power intent
317 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF Synthesis: Technology Setup
# Command: define_library_set
#Define the set of libraries to be used for domain or voltage set
Technology Setup
define_library_set -name v10_lib_set -libraries {$libdir/pads_1v.lib}}
define_library_set -name v11_lib_set -libraries {{$libdir/ss_1v0.lib}}
Define Library sets

Include libTech.cpf # Command: define_isolation_cell

#Define the set of libraries to that can be used for isolation
define_isolation_cell cells { ISO_A ISO_B}
-valid_location to -enable EN always_on_pins {EN}
LibTech.cpf
# Command: define_state_retention_cell
#Define the set of cells that can be used for state retention
define_isolation_cell
Define_state_retention_cell cells {SR_A SR_B}
define_state_retention_cell -save_function {SAVE}

# Command: define_always_on_cell
define_always_on_cell
#
Define_level_shifter_cell Define_always_on_cell cells {AON_1 AON_2} always_on_pins {A}

define_power_switch_cell
# Command: define_level_shifter_cell
#
Define_level_shifter_cell cells {AON_1 AON_2}
MSV/DVFS
Power Shutoff
318 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Associating libraries with a Domain and voltage

Command: define_library_set Define the

#Define the set of libraries to be used for domain or voltage set
define_library_set -name v07_lib_set -libraries {$libdir/ss_0v7.lib}}
libraries
define_library_set -name v11_lib_set -libraries {{$libdir/ss_1v0.lib}}

# Command: create_nominal_condition
# Define the set of voltages to use and define the domain state
Define nominal
create_nominal_condition -name high -voltage 1.1 -state on
create_nominal_condition -name low -voltage 0.7 state standby(get better example)
Conditions +
voltages
# Command: Update nominal Condition
# Associate library set to use for a specific nominal condition Link the libraries
update_nominal_condition name highlibrary_set v11_lib_set to nominal
update_nominal_condition name low library_set v07_lib_set
conditions

# Command: Create_power_mode
# Associate a domain with a nominal condition Link the Domains
Create_power_mode name M1 nominal_conditions {PDA@high PDB@low} to nominal
conditions

319 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF Language Details

Library + Tech

Update Commands for Physical

Power Network and Switches

Details on select CPF commands

320 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 update Isolation_rule/update_level_shifter_rule
update_isolation_rule and update_level_shifter_rule
The placement of the isolation cell can be controlled using this command
location
Specifies where in the hierarchy the isolation cells should be inserted
-within_hierarchy instance
Allow isolation cell to be placed in a specific hierarchy level
Create_isolation_rule name ISO1 from PD_orange
Update_isolation_rule name ISO1 location from within_hierarchy Top

Location From
Top Within_hierarchy Top

InstA

If Location From, without

within_hierarchy If Location to
321 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Update_power_mode for Synthesis
Switching activity information for Power analysis
-activity_file < TCF or VCD file> specifies which activity file used for dynamic power
-activity_file_weight <[0-100] : A relative weight for this mode
If this mode is used 25% of the time, then the weight should be 25
When computing the total power consumption the tool needs to know how often each
mode is active.
Total power is essentially:
Power for MODE * Percentage Time in Mode

SDC files for timing analysis

Provides method to associate SDC files for each power mode
-sdc_files specify a single set of files that apply for both hold and setup
-hold_sdc_files specify files for hold time analysis
-setup_sdc_files specify files for setup time analysis

322 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Operating Corners and Analysis Views
Operating Corner # Command: Create Operating Corner

Defines the corners of interest #Define the operating corners used by timing analysis and
optimization

Voltage, process, temp create_operating_corner -name high_max -voltage 1.3 -library_set lib_1.3
create_operating_corner -name low_max -voltage 1.1 -library_set lib_1.1
Library association
Analysis View
A view specifies an operating
corner for each power domain
Used for Multi-mode, Multi- # Define analysis views for multi-mode/multi corner
# Command: create_analysis_view
Corner analysis and create_analysis_view -name AVdefault_WC -mode PMdefault
optimization in -domain_corners { PDdvfs@PDdvfs1_wc PDpll@PDdvfs1_wc

Implementation create_analysis_view -name AVdvfs2_BC -mode PMdvfs2

-domain_corners { PDdvfs@PDdvfs2_bc PDpll@PDdvfs1_bc }
Can have multiple analysis
views per power mode

323 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF Language Details

Library + Tech

Update Commands for Physical

Power Network and Switches

Details on select CPF commands

324 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF Philosophy on Power Network
Explore & iterate
at domain level
CPF is Power Domain Oriented CPF
The foundation of the LP architecture is the Power

Domains Pwr Network

Domain
Initial LP exploration, verification and Synthesis done based
Verification
on power domains and control logic
Power Network for implementation Synthesis
After LP architecture has be established and verified, the
power network is added to the CPF CLP+ LEC
Advantages of CPF flow
Place + Route
Provide higher level of abstraction to LP Architect
Domain level specification is 2-3x fewer lines of code
Physical implementation details like pwr/ground net names
not needed at this stage
Smaller/fewer
Enables rapid design exploration
iterations at power
Most iterations are done at highest level of abstraction
network level
Improved productivity and ease of specification
Physical design team specifies the power network only after
all major architecture decisions have been made
Improved QOS
Faster iterations allow for more exploration

325 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Base domain

Definition: A power domain that provides primary

power to another domain
VDD_2
Usage:
PD_TOP
Defines nested power domains
PSE_2
Enables more checks on power architecture
prior to having detailed power/ground
connectivity VDD_1
If base_domain is powered off, then all of its
derived domains will also be powered off. PD_MID
IF PSE_2 is active, then both PD_MID and PSE_1
PSO_domain will be powered off, regardless of
PSE_1 signal
VDD_PSO

In the example:
PSO
PD_MID is the base domain for PD_PSO
PD_TOP is the base domain for PD_MID Domain
Create_power_domain name PD_PSO \
base_domains {PD_MID} .

326 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Secondary domain
VDD_2
Definition: Many low power cells have two voltage
supplies feeding them. The secondary domain
defines from where the voltage for the second VDD_1
power supply is derived.
Usage: PD_TOP
Level Shifters, state retention PSE_1
Always on and isolation cells may also define
Typically specified with -secondary_domain
on the create_*_rule commands
PD_PSO
PD_V2
In the example:
SR
State Retention Element (SR) LS
PD_PSO for the main part of the latch
PD_TOP as secondary domain for the retention
portion
Create_state_retention_rule name SR1
secondary domain PD_T0P
Level Shifter(LS)
Primary domain is PD_PSO (where it is placed)
Secondary Domain is PD_V2

327 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Network Connectivity for Non-PSO Domains

Define Power domains

Create Power/Ground nets
Create_power_net, create_ground_net:
create_power_nets -nets vdd108 -voltage 1.08
create_power_nets -nets vssa -voltage 0.0
Associate power and ground nets to each domain
The primary power of all cells in the domain are connected to the associated power and
ground net
Update_power_domain
update_power_domain -name PD_A -primary_power_net vdda108 -primary_ground_net vssa
For MSV designs
Level shifters have two sets of power pins
The define_level_shifter_cell and create_level_shifter_rule define how to connect up the
power.
Primary power is connected to the primary power for the domain in which the cell is placed

FROM_VDD TO_VDD FROM_VDD TO VDD

LS
LS
Placed in from Domain, primary power Placed in to Domain, primary power
is FROM_VDD is TO_VDD
328 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Switch Network For Power Shutoff

Basic Power Switch Network

Single power switch example
Connectivity of LP cells (isolation, state retention)
Advanced Power Switch Networks
Daisy Chain
Mother Daughter
Managing voltage ramp with equivalent pins
Use when multiple switches with enables spread over several
clock cycles are used to control voltage ramp

329 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Net Connectivity
Update Power domain
# Command: Update power_domain
Associates a power domain # Connect power domain to power nets
with a specific set of power and update_power_domain -name PD_A \
ground nets. -primary_power_net vdda25 \
-primary_ground_net vssa
Update_power_switch_rule
update_power_domain -name PD_uart \
Provides additional constraints
-primary_power_net VDDuart\
and connectivity for a power -primary_ground_net VSSsoclib_1.1
switch rule
Constraints:
Peak_ir_drop, # Update power switch rule with constraints
average_ir_drop, # Command: update_power_switch
Connectivity update_power_switch_rule -name pwr_smc_rule \
-peak_ir_drop_limit 0 -average_ir_drop_limit 0
Bias net information
Acknowledge and enable update_power_switch_rule -name pwr_rom_rule \
signals used for daisy chain -peak_ir_drop_limit 0 -average_ir_drop_limit 0
and mother daughter type
power switch networks
See power network for more
details
330 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Network Connectivity for Power Shutoff
Basic Power Switch
Define Power domains
Create_power_domain name PD_VDD
VDD
Create_power_domain name PD_SW shutoff_condition {!PSE}
-base_domain PD_VDD PSE
Create Power/Ground nets
create_power_nets, create_ground_nets:
create_power_nets -nets VDD -voltage 1.08
create_power_nets -nets VDD_SW -voltage 1.08 ISO
-external_shutoff_condition { !PSE } VDD_SW
create_power_nets -nets vssa -voltage 0.0
Associate power and ground nets to each domain SR
The primary power of all cells in the domain are connected to the associated
power and ground net
Update_power_domain
update_power_domain -name PD_VDD -primary_power_net VDD
PD_SW PD_VDD
-primary_ground_net vssa
update_power_domain -name PD_SW -primary_power_net VDD_SW
-primary_ground_net vssa
Define Power Switch rule
Defines where power switches are required
Create_power_switch_rule name SW1
domain PD_SW external_power_net VDD
Default Handling of Special Cells
State retention has 2 sets of power pins
Primary power is connected to the domain VDD_SW because they are in PD_SW
Secondary power used by the save latch and is connected to VDD because
PD_VDD is the base_domain of PD_SW,
Isolation outside of PD_SW will typically have a single power supply connected
to its domains main power( in this case VDD)

331 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Power Network Connectivity for Power Shutoff
Low Power Cells

Isolation placed in the -from domain

Isolation inside the from domain will typically have 2 sets of power and ground
pins
The primary power is connected to the from power domain, in this case PD_SW.
Specify the secondary power using secondary_domain flag (Recommended)
Create_isolation_rule name ISO1 secondary_domain PD_VDD
Use CPF has a default behavior
Connects secondary power to the power domain of the isolation_enable signal

State Retention
The default behavior on the previous slide is used by the vast majority of our
customers, but CPF provides the flexibility to change it.
To override the default behavior for the state retention also use the
secondary_domains flag
Create_state_retention_rule name SR1 secondary_domain {PD_VDD}

332 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF Language Details

Library + Tech

Update Commands for Physical

Power Network and Switches

Details on select CPF commands

333 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Additional CPF Language Details

Create power domain

Update level shifter
Define_isolation_cell
Define_retention_cell
AON cells (always on)
Create_mode_transitions

334 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Create Power Domain Info

CPF spec allows to specify the following instances as power

domain.
Black box (No function in Liberty) cells
e.g. Macro cells (RAM/ROM, etc)
Cells that have is_pad true in Liberty
e.g. IO cells
Modules defined in netlist
Macro models defined by set_macro_model in CPF
Regs inside of a macro model
This is to help model corruption of behavioral models of a macro

335 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Create_level_shifter_rule
Update_level_shifter_rule

Create_level_shifter rule defines a requirement for level

shifter insertion
Example:
Create_level_shifter_rule name LSR1 from PDA to PDB
-pins { list of specific pins on domain to apply the rule}
-exclude { list of pins to not insert level shifting on.
Update_level shifter provides additional location
information for physical implementation
Example
Update_level_shifter_rule name LSR 1 location from
Specifies the level shifter should be placed in the from
domain
-within_hierarchy : is another common option and specifies
exactly where in the logical hierarchy to place the level shfiter.

336 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Define_isolation_cell
Defines which
domain the cell can be
Defines a library cell as an isolation cell placed in.
This information is used primarily for Most often its the to
implementation tools domain of the
-always_on_pins is used by simulation create_isolation_rule
Most Common Options:
define_isolation_cell Some cells
-cells cell_list automatically isolate
[-valid_location { from | to | on | off}] whenever the primary
{ -enable pin | power is turned off
-no_enable {high|low|hold} }
- -power power_pin \ Most isolation cells have
-power_switchable an enable pin to define
switchable_power_pin when the cell is isolated

Used to define
always_on style isolation
cell.

337 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Define_isolation_cell (Additional Options)

[-always_on_pins pin_list] Used by the simulator to define

which pins do not corrupt
-non_dedicated Defines this cell can be used for
both isolation and normal
functional synthesis
-library_set lib_set Defines the library set these cells
can be used with
-power_switchable LEF_power_pin | Used by physical implementation
-ground_switchable LEF_ground_pin} to connect proper switchable
power or ground to cell
-power LEF_power_pin Used by Physical implementation
-ground LEF_ground_pin ] to connect proper power/ground

338 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Define_state_retention_cell

define_state_retention_cell
-cells cell_list [-cell_type string]
{-restore_function expression | -save_function
expression
[-restore_check expression] [-save_check expression]

339 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Define_state_retention_cell (additional options)

[-always_on_pins pin_list] Used by the simulator to define which

pins do not corrupt
[-always_on_components List of components in simulation
comp_list] model that do not corrupt
[-clock_pin pin] Define clock pin, typically not needed
(derived from .lib)
-library_set lib_set Defines the library set these cells can
be used with
-power_switchable LEF_power_pin | Used by physical implementation to
-ground_switchable LEF_ground_pin} connect proper switchable power or
ground to cell
-power LEF_power_pin Used by Physical implementation to
-ground LEF_ground_pin ] connect proper power/ground

340 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 AON Cells
Defines cells that are considered always_on
They are cells in a power shutoff region that are not connected to the output of
the power switch
They are not truly always on, as their power supply can be switched at higher
levels of hierarchy
Usage
Implementation tools connect the proper power and ground to the cell, and can
only replace it with other always on cells (not other non-LP cells in the library)
LP checking

[-always_on_pins pin_list] Used by the simulator to define which pins do

not corrupt

-power_switchable LEF_power_pin | Used by physical implementation to connect

-ground_switchable LEF_ground_pin} proper switchable power or ground to cell

-power LEF_power_pin Used by Physical implementation to connect

-ground LEF_ground_pin ] proper power/ground

341 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Always_on_pins
Always_on_components

Always_on_pins
Always on pins definitions are used for simulation of instantiated low
power cells. (either gate-level netlist or instantiated at RTL)
The always on pins model the fact that these cells are always on and
do not corrupt the way normal cells in a power shutoff would corrupt
Examples are: enable pin for isolation, save/restore for state retention.
The low power behavior of these cells is expected to be in the verilog
simulation model for the cell
Always on components
Provide a method to simulate instantiated state retention cells
The components (registers, UDP) defined will not corrupt during low
power simulation
Typically the SR cell is modeled as having a latch that is listed as
always on.
The rest of the SR cell will be follow normal LP corruption semantics

342 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Create_mode_transitions - Notes

Controlling the transition

Define that there is a valid path between to modes
Define a start_condition that triggers the mode
transitions
Notes
If no mode transitions are defined for a design, then ALL
mode transitions are considered legal
If one or more mode transitions are defined, any
unspecified mode transitions are considered illegal
The Start conditions of mode transitions with the same
-from mode need to be unique
Otherwise tool can not determine which mode to transition
to, the following would be illegal:
Create_mode_transition from MA to MB start_condition C
Create_mode_transition from MA to MC start_condition C

343 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Domain States

CPF defines 3 domain states

ON
The domain is supplied a valid functional voltage
OFF
The domain is considered shutoff
The voltage is typically 0, but is not required to be
Simulation will corrupt the domain
CLP will ensure that isolation is used when ever the domain is in an
OFF mode.
Standby
The domain is in a lower voltage state that maintains value but
cannot compute new values
Simulation will check the inputs and ensure no changes occur
Changes will propagate Xs through the logic and fire a warning

344 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Tips and Techniques
How to model Hard macro with power intent
Macro Modeling ( details in macro modeling section)
I/O pads
Voltage_regulator
Level Shifters and Combination Isolation/level shifting cells
Roms, Flash Memory (details in RTL coding style section)

What are secondary domains (details in CPF topics)

How do avoid rush current due to power control logic
How do I design reusable Power aware IP blocks (details in IP reuse section)

Handling designs with Instantiated LP cells

Understanding Isolation on Constants and Tie Cells
Conformal LP Tips

CPF Support Matrix

Table with each CPF features, tool, support status (with tool version)

Note on Printed Copy: The details for some of the topics above are in different sections of this document and are
not copied here. In presentation mode the links provided will jump to the proper sections

345 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 I/O Pad Cells

Many Variations in I/O Pad design

Some pads have simple power profile, a single voltage
These require no special handling in CPF
Usually are placed in default power domain. Others pad designs are
similar to level shifters
Input Output
Pad Chip Pad Cross multiple domains
Core High V board interface
Input Area Inout
Pad Pad Low V core interface
More than level shifters
Multiple shifted paths

Use macro models to define complex Pads Special low power features

Supports multiple power domains

Macro models must be black boxed for CLP
Use CLP PIA to simplify instantiation
Use TCL for loop for large numbers of instances

346 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 I/O Pad Cell Definition Example
set_macro_model IPad
create_power_domain name core boundary_ports Y
create_power_domain name pad boundary_ports A
VDP VDC update_power_domain name core
A IPad Y
primary_power_net VDC primary_ground_net VSS
VSS
update_power_domain name pad
primary_power_net VDP primary_ground_net VSS
end_macro_model

set_macro_model OPad
create_power_domain name core boundary_ports A
create_power_domain name pad boundary_ports Y
VDC VDP update_power_domain name core
A OPad Y primary_power_net VDC primary_ground_net VSS
VSS update_power_domain name pad
primary_power_net VDP primary_ground_net VSS
end_macro_model

Create macro models without knowledge of design usage

347 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 I/O Pad Cell Integration into Design Example

VHI
x1 xC x3
Domain Mapping VDP VDP
A IPad Y A OPad Y
Depends on how power and Chip VSS VDC
VSS VDC
ground will be connected Core
VDP VDP
Does not depend on driving A Y
Area A Y
IPad OPad
or receiving domains x2
VSS VDC VSS VDC
x4
Switch
VLO
GND
create_power_domain name Lo default
create_power_domain name Core instances xC shutoff_condition OFF
create_power_domain name Hi boundary_ports { list of data I/O }
update_power_domain name Lo primary_power_net VLO primary_ground_net GND
update_power_domain name Core - primary_power_net VSW primary_ground_net GND
update_power_domain name Hi primary_power_net VHI primary_ground_net GND
set_instance x1 domain_mapping { { core Lo } { pad Hi } model IPad
set_instance x2 domain_mapping { { core Lo } { pad Hi } model IPad
set_instance x3 domain_mapping { { core Lo } { pad Hi } model OPad
set_instance x4 domain_mapping { { core Lo } { pad Hi } model OPad

348 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 TIP: Use the PIA GUI to hook up I/O pads
GUI Form allows quicker
entry of IO Pads and their
power/ground mappings
GUI Allows you to define
groups of pins and use buses
One quick GUI form can
replace hundreds of lines of
CPF
Most designs only require a
handful of pad rules to cover all
the I/O
CLP can write out CPF
command equivalents for
use in the rest of the design
flow
349 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Tips and Techniques
How to model Hard macro with power intent
Macro Modeling ( details in macro modeling section)
I/O pads
Voltage_regulator
Level Shifters and Combination Isolation/level shifting cells
Roms, Flash Memory (details in RTL coding style section)

What are secondary domains (details in CPF topics)

How do avoid rush current due to power control logic
How do I design reusable Power aware IP blocks (details in IP reuse section)

Handling designs with Instantiated LP cells

Understanding Isolation on Constants and Tie Cells
Conformal LP Tips

CPF Support Matrix

Table with each CPF features, tool, support status (with tool version)

Note on Printed Copy: The details for some of the topics above are in different sections of this document and are
not copied here. In presentation mode the links provided will jump to the proper sections

350 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Voltage Regulators

Voltage Regulators provide on

chip voltage control
x1 = REG
LDO- low drop out voltage VHI VDD
Voltage scaling VREG
VLO Chip
Core
Charge pumps EnReg Area
PSO
Variable voltage selection VSS
Dynamic voltage control VSS

CPF Modeling goals

Connectivity checking in CLP
Consistent Power Mode
definitions
Level shifter/isolation insertion
and checking

351 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Describing Voltage Regulators

Process of defining a regulator

Library definition
x1 = REG
Macro Model description VHI VDD
Chip
Instantiate the macro model VREG
VLO
Core
EnReg Area
PSO
VSS
1. Define the regulator in the library VSS
Techlib (.lib) or in verilog
Define Power Out as inout direction
Regulator must be black boxed

352 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Describing Voltage Regulators x1 = REG
VHI VDD
VLO Chip
VREG Core
EnReg Area
2. Define a macro model PSO
VSS
set_macro_model REG
VSS
# Create a power domain for each voltage supply
create_power_domain name PD_VDDboundary_ports EnReg -default
create_power_domain name PD_VREG shutoff_condition !EnReg
external_controlled_shutoff
# Link the power domain to the power nets/input pins
update_power_domain name PD_VDD- primary_power_net VDD primary_ground_net VSS
update_power_domain name PD_VREG -primary_power_net VREG primary_ground_net
VSS
# Create nominal conditions to represent the allowed voltage levels
create_nominal_condition -name NC_OFF-voltage 0.0
create_nominal_condition -name NC_LOW-voltage 1.2
create_nominal_condition -name NC_HIGH -voltage 3.3
# Create power modes to define the allowed combinations of voltages
create_power_mode -name M1 -domain_conditions {PD_VDD@NC_HIGH PD_VREG@NC_OFF}
create_power_mode -name M2 -domain_conditions {PD_VDD@NC_HIGH PD_VREG@NC_LOW}

353
end_macro_model
January 31, 2010
Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Voltage Regulator Example x1 = REG
VHI VDD
VTOP Chip
VREG Core
EnReg Area
PSO
VSS
2. Instantiate the Regulator
VSS
# Create a top level power domain for each voltage supply
create_power_domain name TOP_VDD_boundary_ports EnReg -default
create_power_domain name TOP_VREG shutoff_condition !x1/EnReg
external_controlled_shutoff
# Link the power domain to the power nets/input pins
update_power_domain name TOP_VDD- primary_power_net VHI primary_ground_net VSS
update_power_domain name TOP_VTOP -primary_power_net VTOP primary_ground_net
VSS
# Instantiate the voltage regulator
set_instance xReg model REG domain_mapping {{PD_VDD TOP_VDD } { PD_VREG
TOP_VREG}}
# Create nominal conditions to represent the allowed voltage levels
create_nominal_condition -name NC_OFF-voltage 0.0
create_nominal_condition -name NC_LOW-voltage 1.2
create_nominal_condition -name NC_HIGH -voltage 3.3
# Create power modes to define the allowed combinations of voltages
354 January 31, 2010
Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
create_power_mode -name T1 -domain_conditions {TOP_VDD@NC_HIGH TOP_VREG@NC_OFF}
 Notes on voltage Regulator

Create macro models without knowledge of design usage

Domain Mapping depends on how power and ground will
be connected
Domain Mapping does not depend on driving or receiving
domains

355 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Simulation modeling of voltage regulator
The model described above works for a simple static relationship of
voltage and Power shutoff
The input and output voltages are always the same
This model simulates with no special additions
Regulators can also have multiple voltages as output, or select
between several voltages
CPF models multiple voltage levels in two ways
Active state conditions define a condition when a specified voltage level is
applied to domain
Create_power_domain active_state_conditions {v10@cond1 v12@cond2}
Power modes and power mode transitions
The active state conditions are most common and can easily model most voltage
regulators
Analog or complex voltage regulators may require special modeling
A wreal analog model can be used to determine the voltage
Create a wrapper that uses the output of the analog model to set the
active_state_condition used in the CPF
Contact Cadence for more details on how to implement this flow

356 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Tips and Techniques
How to model Hard macro with power intent
Macro Modeling ( details in macro modeling section)
I/O pads
Voltage_regulator
Level Shifters and Combination Isolation/level shifting cells
Roms, Flash Memory (details in RTL coding style section)

What are secondary domains (details in CPF topics)

How do avoid rush current due to power control logic
How do I design reusable Power aware IP blocks (details in IP reuse section)

Handling designs with Instantiated LP cells

Understanding Isolation on Constants and Tie Cells
Conformal LP Tips

CPF Support Matrix

Table with each CPF features, tool, support status (with tool version)

Note on Printed Copy: The details for some of the topics above are in different sections of this document and are
not copied here. In presentation mode the links provided will jump to the proper sections

357 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Enabled Level Shifter VS ISO/LS Combo Cell

A common library question is how to model enabled

level shifter and combination isolation/LS cells

What are these cells?

Combo Isolation/level shifter:
This is conceptually an isolation cell followed by a level shifter.

Enabled Level Shifter

An enabled level shifter is a level shifter that can be turned on
or off
When the shifter is turned off, its output is clamped to a
specific value

358 September 12, 2011 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Comparison of Typical Combo Cell vs Enabled LS
Combo Isolate/Level Shifter Enabled Level Shifter

Isolation:
Combo Cell isolates on its input
Enabled LS isolates on its output the logic up to the actual level
shifting is unprotected
Level Shifter
Enabled LS: LS portion is powered off when not enabled.
Combo Cell: LS portion is always enabled
Enable pins related power
Combo Cell: Enables power is from the VDD_IN (source side)
Enabled LS: Enables power is from the VDD_OUT (destination side)
359 September 12, 2011 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Modeling A Isolation-Level Shifter Combo Cell
A combo cell isolates or protects the input when the driving logic is powered down
and generates an output isolation value at the same voltage as the output supply of
the cell.
Typically the enable pin is related to the input supplies of the cell.
This type of cell is not very common. The most common combo cells are the isolation cells
with high to low shifting capabilities.
To model a combo cell you need two commands. For example:
define_level_shifter_cell -cells LVLLHCD*
-input_voltage_range 0.792:0.99:0.099 \
-output_voltage_range 0.792:0.99:0.099 \
-output_voltage_input_pin ENABLE \
-input_power_pin VDD_IN \
-output_power_pin VDD_OUT \
-direction up \
-ground GND \
-valid_location to
define_isolation_cell -cells LVLLHCD* \
-power VDD_OUT \
-ground GND \
-enable ENABLE \
-valid_location to
Note: In this case, you cannot use the -enable option in the define_level_shifter_cell
definition.
360 September 12, 2011 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Modeling an Enabled Level Shifter

Enabled Level Shifter.

This type of cell uses an enable pin to control the voltage shifting.
When the enable is active the level shifting is enabled,
When the enable is inactive, the level shifting is turned off and the output is clamped to a
specific value
Typically the enable pin is related to the output supplies of the level shifter.
If both domains are powered on, you can tie the enable to be always active and it works as a
level shifter.
Modeling an Enabled Power Level Shifter
define_level_shifter_cell -cells up_shift \
-input_voltage_range 0.8:1.0 -output_voltage_range 1.0:1.2 \
-input_power_pin VDD_IN -output_power_pin VDD_OUT -ground GND \
-direction up -valid_location from -enable ENABLE

Note: The driver of the level shifter data pin is not protected. For such a cell to be used for isolation
purposes its input power pin should be connected to the primary(unswitched) power net of the driving
domain.

361 September 12, 2011 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Tip Use the PIA GUI to simplify entry

Simple Form
Driven entry
No need to learn
all the underlying
syntax
Faster entry
Less error prone
Seeded with
information from
library (pin
names, etc)

362 September 12, 2011 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Tips and Techniques
How to model Hard macro with power intent
Macro Modeling ( details in macro modeling section)
I/O pads
Voltage_regulator
Level Shifters and Combination Isolation/level shifting cells
Roms, Flash Memory (details in RTL coding style section)

What are secondary domains (details in CPF topics)

How do avoid rush current due to power control logic
How do I design reusable Power aware IP blocks (details in IP reuse section)

Handling designs with Instantiated LP cells

Understanding Isolation on Constants and Tie Cells
Conformal LP Tips

CPF Support Matrix

Table with each CPF features, tool, support status (with tool version)

Note on Printed Copy: The details for some of the topics above are in different sections of this document and are
not copied here. In presentation mode the links provided will jump to the proper sections

365 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Using Equivalent Control Pins to Control Rush Current

It may be necessary to sequence the assertion and de-assertion of

power control signals over multiple clock cycles
To avoid unacceptable levels of instantaneous switching activity
To control the voltage ramp for power shutoff
The implementation tools cannot insert clock stages on these
controls automatically
CPF provides equivalent control pins to accomplish
In current flow only EDI and CLP provide support this style
Until complete tool support is available,
Recommend using the example on the following page

366 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 CPF coding style option 2

VDD (domain = AON)

E1

VIN VIN VIN VIN VIN VIN

E2 Ei Eo Ei Eo Ei Eo Ei Eo Ei Eo Ei Eo
VSW VSW VSW VSW VSW VSW
SR1 SR2 SR3
E3

VSO (domain = PSO)

create_power_domain name PSO shutoff_condition !E1 | !E2 | !E3

create_power_switch_rule -name sr1 -domain PSO -external_power_net VDD
update_power_switch_rule -name sr1 -stage1_enable E1
create_power_switch_rule -name sr2 -domain PSO -external_power_net VDD
update_power_switch_rule -name sr2 -stage1_enable E2
create_power_switch_rule -name sr3 -domain PSO -external_power_net VDD
update_power_switch_rule -name sr3 -stage1_enable E3

367 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Tips and Techniques
How to model Hard macro with power intent
Macro Modeling ( details in macro modeling section)
I/O pads
Voltage_regulator
Level Shifters and Combination Isolation/level shifting cells
Roms, Flash Memory (details in RTL coding style section)

What are secondary domains (details in CPF topics)

How do avoid rush current due to power control logic
How do I design reusable Power aware IP blocks (details in IP reuse section)

Handling designs with Instantiated LP cells

Understanding Isolation on Constants and Tie Cells
Conformal LP Tips

CPF Support Matrix

Table with each CPF features, tool, support status (with tool version)

Note on Printed Copy: The details for some of the topics above are in different sections of this document and are
not copied here. In presentation mode the links provided will jump to the proper sections

368 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Handling Designs with Instantiated LP cells

In some cases a user may choose to directly instantiate

the low power cells
The recommended methodology is to allow RTL-compiler to
insert all low power logic

The next few slides discuss the hand instantiated LP

cells
Isolation cells
Level shifters
State retention

369 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Handling designs with Isolation Cells
Instantiated
Hand instantiated isolation logic is automatically handling in most tools
Most tools can identify existing LP cells and no special actions are required by the user
If the existing isolation cell matches the isolation rules then no new cell is inserted
The isolation condition, isolation_ouput, and isolation_target must all match
RTL compiler, Encounter and CLP all behave the same.
IES
IES is not a synthesis too and does not have the same understanding of the LP cells or
ability to verify that an instantiated LP cell matches the CPF definition
If all the isolation cells for a design have been inserted then:
IES has the ability to turn off isolation insertion on the entire design
use the lps_iso_off flag
Define the low power cells using the define_isolation_cell always_on_pin
Define the always on portion of the isolation, this ensures the isolation cell is not corrupted
during power shutoff.
If only a portion of the design has isolation cells inserted
IES does not have the ability to turn off isolation on a domain or module basis
This is a planned improvement
Workaround
ensure that the isolation logic is described with create_isolation_rule in the CPF
Allow IES to model the isolation rules
The simulator will insert virtual isolation cells and will essentially double isolate the cells
in question
Use CLP to check consistency between the RTL instantiation and the CPF Description
If CLP check is clean, then the double isolation will have no impact on the functional
verification.

370 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Handling designs with State retention cells
Instantiated
If the instantiated state retention cell is properly defined as a state retention
cell
Then RC, Encounter, and CLP will not attempt to replace the existing logic
CLP will check to ensure that the instantiated cell matches all applicable state
retention rules

IES If all state retention cells are already inserted

use the lps_rtn_off flag
This turns off the implicit modeling of the retention cells
Without this flag, IES may attempt to model state retention inside of the behavior model
of the state retention cell
Define_state_retention_cell always_on_pin <> -always_on_inst
This defines which pins are treated as always on, and which instances inside the
verilog model of the cell remain powered on
Typically the cell is modeled with a reg for the save latch, this save latch would be
marked as always on.
IES- If only a portion of the design has isolation cells inserted
IES does not have the ability to turn off state retention modeling on a domain
or module basis
This is an improvement for CPF 2.0

371 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Handling designs with Level shifter cells
Instantiated

If the instantiated level shifter cells are properly

defined
Then RC, Encounter, and CLP will not attempt to
replace the existing logic
Use : define_level_shifter_cell to define the cells
IES
Level shifting is not currently modeled

372 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Designs with Always on Cells

IES if always on cells are instantiated in a power

shutoff domain use the following option:
"-lps_lpcell_ft"
This option has a performance impact so it is not on by default.

373 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Tips and Techniques
How to model Hard macro with power intent
Macro Modeling ( details in macro modeling section)
I/O pads
Voltage_regulator
Level Shifters and Combination Isolation/level shifting cells
Roms, Flash Memory (details in RTL coding style section)

What are secondary domains (details in CPF topics)

How do avoid rush current due to power control logic
How do I design reusable Power aware IP blocks (details in IP reuse section)

Handling designs with Instantiated LP cells

Understanding Isolation on Constants and Tie Cells
Conformal LP Tips

CPF Support Matrix

Table with each CPF features, tool, support status (with tool version)

Note on Printed Copy: The details for some of the topics above are in different sections of this document and are
not copied here. In presentation mode the links provided will jump to the proper sections

374 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Understanding Isolation with Tie-hi/Tie-low Cells
Will isolation cells be placed on signals driven by ON
tie-hi/tie-low cells?
OFF
Isolation is typically required Tie
The tie cells are part of the power shutoff domain
When power is turned off to the domain, the tie cells
also lose power Tie
Isolation is needed to protect the boundary

What about Always on tie cells

If the tie cell is a special always on type cell then
isolation may not be required: Isolation Specified
If the type of tie cell matches the type of isolation then
no isolation is required
Example OFF
A tie-hi cell in the library ON
Create_isolation_rule name ISO1 isolation_output high
If the isolation type differs from the tie cell type then Tie
isolation is required
Ex: Isolation_output low with a tie_hi cell
In this case, the tie cell will drive a 1 but the CPF
specifies a 0 should be driven. Tie
Isolation will be inserted to match the power intent
CLP will issue a warning message
375 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Understanding Isolation with Constants driving
a domain boundary
OFF
What happens to the constants in implementation
The synthesis tools will push the constants forward, so that they can 1b1 ON
be optimized with the logic they drive
The constants are now local to the domain they drive, and so do not
need isolation from a physical design perspective

For simulation the constants are required 1b0

Simulation does not optimize constants across design boundaries
Isolation is needed on the interface

If the isolation value is the same as the constant value, then the
two methods are functionally equivalent
The destination would see the same value regardless of whether the
domain was powered off
The destination does not care if the input is a 1b1 because of isolation or ON
because it is the constant itself
OFF
Recommended Methodology 1b1
Use Conformal Low power to detect any cases where the Isolation
value differ from the constant value
If any differences occur, then
Change the CPF so that the constants match the isolation value
Use the following:
RC flags: set_attr lp_isolate_domain_crossing_constants true 1b0
/designs/*
CLP flag: lowpower option -no_local_constants

376 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Tips and Techniques
How to model Hard macro with power intent
Macro Modeling ( details in macro modeling section)
I/O pads
Voltage_regulator
Level Shifters and Combination Isolation/level shifting cells
Roms, Flash Memory (details in RTL coding style section)

What are secondary domains (details in CPF topics)

How do avoid rush current due to power control logic
How do I design reusable Power aware IP blocks (details in IP reuse section)

Handling designs with Instantiated LP cells

Understanding Isolation on Constants and Tie Cells
Conformal LP Tips

CPF Support Matrix

Table with each CPF features, tool, support status (with tool version)

Note on Printed Copy: The details for some of the topics above are in different sections of this document and are
not copied here. In presentation mode the links provided will jump to the proper sections

377 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Equivalency check of power switch insertion

Equivalence check for a design having a circuit that checks signal

propagation of power switches. When running LEC on a design including
such circuit, false errors can occur.

To avoid the false errors by LEC, adopt one of following options.

Exclude external terminals that connect to open signal in golden from
equivalence check
Add a dummy (empty) module manually in golden to do away with open signals.
LEC can verify connectivity, as there is no open signals.

378 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Info on Virtual Isolation Insertion

CLP rule check on voltage is more strict in Ver. 9.1 than

before. When the following values don't match, virtual
insertion cannot be done.
nominal condition of CPF
nom_voltage in .lib
To disable voltage check, set
setenv SKIP_LIB_CELL_VOLTAGE_CHECK 1

379 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Tips and Techniques
How to model Hard macro with power intent
Macro Modeling ( details in macro modeling section)
I/O pads
Voltage_regulator
Level Shifters and Combination Isolation/level shifting cells
Roms, Flash Memory (details in RTL coding style section)

What are secondary domains (details in CPF topics)

How do avoid rush current due to power control logic
How do I design reusable Power aware IP blocks (details in IP reuse section)

Handling designs with Instantiated LP cells

Understanding Isolation on Constants and Tie Cells
Conformal LP Tips

CPF Support Matrix

Table with each CPF features, tool, support status (with tool version)

Note on Printed Copy: The details for some of the topics above are in different sections of this document and are
not copied here. In presentation mode the links provided will jump to the proper sections

380 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Appendix A: CPF Support Matrix

381 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 General CPF Command Support

Legend : Status Legend : Tools

P Planned CLP Conformal Low Power
S Supported
IUS Incisive Unified
U Unsupported Simulator
NP Not Planned PD Palladium

N/A Not Applicable RC Encounter RTL

Compiler
ET Encounter Test

EDI Encounter

382 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IUS IUS
Ver CLP PD RC ET EDI Comments
Verilog VHDL
assert_illegal_domain_configurations 1.1
-name string N/A U U U N/A N/A N/A
-domain_conditions domain_condition_list N/A U U U N/A N/A N/A
-group_modes group_modes_list N/A U U N/A N/A N/A N/A
-domain_conditions domain_condition_list N/A U U N/A N/A N/A N/A
-group_modes group_mode_list N/A U U N/A N/A N/A N/A
create_analysis_view
-name string 1.1 N/A N/A N/A N/A N/A N/A S
-mode mode 1.1 N/A N/A N/A N/A N/A N/A S
-domain_corners domain_corner_list 1.1 N/A N/A N/A N/A N/A N/A S
-group_views group_view_list 1.1 N/A N/A N/A N/A N/A N/A S
-user_attributes string_list 1.1 N/A N/A N/A N/A N/A N/A S
create_assertion_control
-name string 1.1 N/A 6.2 6.2 N/A N/A N/A N/A
-assertions assertion_list 1.1 N/A 6.2 6.2 N/A N/A N/A N/A
-domains power_domain_list 1.1 N/A 6.2 6.2 N/A N/A N/A N/A
-shutoff_condition expression 1.1 N/A 6.2 6.2 N/A N/A N/A N/A
-type {reset | suspend} 1.1 N/A 6.2 6.2 N/A N/A N/A N/A
-exclude assertion_list 1.1 N/A U U N/A N/A N/A N/A
create_bias_net 1.1
-net net S N/A N/A N/A N/A N/A S
-driver pin NP N/A N/A N/A N/A N/A N/A
EDI - query by
-user_attributes string_list NP N/A N/A N/A N/A N/A S
"getCPFUserAttributes"
-peak_ir_drop_limit float N/A N/A N/A N/A N/A N/A N/A
-average_ir_drop_limit float N/A N/A N/A N/A N/A N/A N/A

383 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IUS IUS ED
Ver CLP PD RC ET Comments
Verilog VHDL I
create_global_connection 1.1
-net net N/A N/A N/A N/A N/A N/A S
-pins pin_list N/A N/A N/A N/A N/A N/A S
-domain domain N/A N/A N/A N/A N/A N/A S
-instances instance_list N/A N/A N/A N/A N/A N/A S
create_ground_nets 1.1
-nets net_list S N/A N/A N/A N/A N/A S
-voltage {float | voltage_range} S N/A N/A N/A N/A N/A S
-external_shutoff_condition expression S N/A N/A N/A N/A N/A S
-internal S N/A N/A N/A N/A N/A S
-user_attributes string_list N/A N/A N/A N/A N/A N/A S EDI - query by "getCPFUserAttributes"
-peak_ir_drop_limit float N/A N/A N/A N/A N/A N/A S
-average_ir_drop_limit float N/A N/A N/A N/A N/A N/A S
create_isolation_rule 1.1
-name string S S S S S S S
-isolation_condition expression S S S S S S S
8.2up
-no_condition NP 8.2 S N/A U 8.1
d
-pins pin_list S S S S S S S
-from power_domain_list S S S S S S S
-to power_domain_list S S S S S S S
-exclude pin_list S S U S S S S
-isolation_target {from|to} S U U N/A S S S
-isolation_output { high | low | hold | tristate} S P P (S) S S S tristate is U yet(Tools List : RC)
-secondary_domain power_domain S 8.2s8 8.2s8 S N/A U S

384 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IUS IUS
Ver CLP PD RC ET EDI Comments
Verilog VHDL
Create_level_shifter_rule 1.1
-name string S U U N/A S S S
-pins pin_list S U U N/A S N/A S
-from power_domain_list S U U N/A S N/A S
-to power_domain_list S U U N/A S N/A S
-exclude pin_list S U U N/A S N/A S
create_mode_transition 1.1
-name string N/A 8.2s8 8.2s8 Planed N/A N/A N/A
-from power_mode N/A 8.2s8 8.2s8 Planed N/A N/A N/A
-to power_mode N/A 8.2s8 8.2s8 Planed N/A N/A N/A
-state_condition expression N/A 8.2s8 8.2s8 NP N/A N/A N/A
-end_condition expression N/A 8.2s8 8.2s8 NP N/A N/A N/A
-cycles [integer:]integer N/A U U N/A N/A N/A N/A
-clock_pin clock_pin N/A U U N/A N/A N/A N/A
-latency [float:]float N/A 8.2s8 8.2s8 N/A N/A N/A N/A
create_nominal_condition 1.1
-name string S 8.2s8 8.2s8 S S S S
-voltage float S 8.2s8 8.2s8 S S S S
-ground_voltage float S NP NP NP S N/A S
-state {on | off | standby} NP 8.2s8 8.2s8 S N/A N/A N/A
-pmos_bias_voltage float NP N/A N/A NP N/A N/A N/A
-nmos_bias_voltage float NP N/A N/A NP N/A N/A N/A
create_operating_corner 1.1
-name string N/A N/A N/A N/A N/A N/A S
-voltage float N/A N/A N/A N/A N/A N/A S
-ground_voltage float N/A N/A N/A N/A N/A N/A S
-pmos_bias_voltage float N/A N/A N/A N/A N/A N/A N/A
-nmos_bias_voltage float N/A N/A N/A N/A N/A N/A N/A
-process float N/A N/A N/A N/A N/A N/A S
-temperature float N/A N/A N/A N/A N/A N/A S
-library_set library_set N/A N/A N/A N/A N/A N/A S

385 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IUS IUS
Ver CLP PD RC ET EDI Comments
Verilog VHDL
create_power_domain
-name power_domain 1.1 S S S S S S S
-instances instance_list 1.1 S S S S S S S
-boundary_ports pin_list 1.1 S 8.2 8.2s8 S S S S
-default 1.1 S S S S S S S
-shutoff_condition expression 1.1 S S S S S S S
-external_controlled_shutoff 1.1 S 8.2 8.2s8 S S S S
-default_isolation_condition expression 1.1 NP 9.2 9.2 S S S S
-default_restore_edge expression 1.1 NP 8.1 8.1 S S U S
-default_save_edge expression 1.1 NP 8.1 8.1 S S U S
-default_restore_level expression 1.1 NP 8.1 8.1 N/A S U N/A
-default_save_level expression 1.1 NP 8.1 8.1 N/A S U N/A
-power_up_states {high|low|random} 1.1 N/A NP NP S N/A U N/A
-active_state_conditions
1.1 NP 8.2s8 8.2 s8 S N/A N/A N/A
active_state_condition_list
-base_domains domain_list 1.1 only S 8.1 8.1 S U U S
create_power_mode 1.1
-name string S 8.2s8 8.2s8 S S S S
-default S 8.2s8 8.2s8 S S S S
-domain_conditions domain_condition_list S 8.2s8 8.2s8 S S S S
-group_modes group_mode_list S 9.2 9.2 NP N/A U S
create_power_nets 1.1
-nets net_list S N/A N/A N/A N/A N/A S
-voltage {float | voltage_range} S N/A N/A N/A N/A N/A S
-external_shutoff_condition expression S N/A N/A N/A N/A N/A S
-internal S N/A N/A N/A N/A N/A S
-user_attributes string_list N/A N/A N/A N/A N/A N/A S EDI - query by "getCPFUserAttributes"
-peak_ir_drop_limit float N/A N/A N/A N/A N/A N/A S
-average_ir_drop_limit float N/A N/A N/A N/A N/A N/A S

386 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IUS IUS
Ver CLP PD RC ET EDI Comments
Verilog VHDL
create_power_switch_rule 1.1
-name string S N/A N/A N/A N/A S S
-domain power_domain S N/A N/A N/A N/A S S
-external_power_net net S N/A N/A N/A N/A N/A S
-external_ground_net net S N/A N/A N/A N/A N/A S
create_state_retention_rule
-name string 1.1 S S S S S S S
-domain power_domain 1.1 S S S S S S S
-instances instance_list 1.1 S S S S S S S
8.2s1
-exclude instance_list 1.1 S 8.2s16 S S N/A S
6
-restore_edge expression 1.1 S 8.1 8.1 S S U S
-save_edge expression 1.1 S 8.1 8.1 S S U S
-restore_precondition expression 1.1 NP 8.1 8.2 S N/A N/A N/A
-save_precondition expression 1.1 NP 8.1 8.2 S N/A N/A N/A
-target_type {flop|latch|both} 1.1 S U U S S N/A S
-secondary_domain domain 1.1 S 8.1 8.1 S N/A U S
define_library_set 1.1
-name library_set S N/A N/A N/A S N/A S
-libraries list S N/A N/A N/A S N/A S
-user_attributes string_list N/A N/A N/A N/A N/A N/A S
end_design 1.1 S S S S S S S
end_macro_model 1.1 S 8.2 8.2 U S S S
end_power_mode_control_group 1.1 NP 9.2 9.2 NP N/A U S
get_parameter 1.1 NP NP NP NP N/A U
identify_always_on_driver 1.1
-pins pin_list N/A NP NP N/A S S S
-no_propagation N/A NP NP N/A S S S
387 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IUS IUS
Ver CLP PD RC ET EDI Comments
Verilog VHDL
identify_power_logic 1.1
-type isolation N/A N/A N/A N/A S N/A S EDI - only "isolation" is allowed for -type
-instances instance_list N/A N/A N/A N/A S N/A S
-module name N/A N/A N/A N/A S N/A S
identify_secondary_domain 1.1
-secondary_domain domain N/A 8.1 8.1 N/A N/A N/A S
-instances instance_list N/A 8.1 8.1 N/A N/A N/A S
-cells cell_list N/A 8.1 8.1 N/A N/A N/A S
-domain power_domain N/A 8.1 8.1 N/A N/A N/A S
-from power_domain N/A 8.1 8.1 N/A N/A N/A S
-to power_domain N/A 8.1 8.1 N/A N/A N/A S
include 1.1 S S S U S N/A S
set_array_naming_style 1.1 S NP NP N/A S N/A S
set_cpf_version 1.1 S S S S S S S
set_design 1.1
-ports port_list S S S S S S S
-honor_boundary_port_domain N/A N/A N/A S N/A N/A S
-parameters parameter_value_list N/A N/A N/A NP N/A U S
set_equivalent_control_pins 1.1
-master pin S N/A N/A N/A N/A U S
-pins pin_list S N/A N/A N/A N/A U S
-domain domain S N/A N/A N/A N/A U S
-rules rule_list S N/A N/A N/A N/A U S
set_floating_ports 1.1 S NP NP N/A S N/A N/A
set_hierarchy_separator 1.1 S S S S S S S

388 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IUS IUS
Ver CLP PD RC ET EDI Comments
Verilog VHDL
set_input_voltage_tolerance 1.1
-ports port_list S U U N/A N/A N/A N/A
-bias [float:]float S U U N/A N/A N/A N/A CLP :Ranges is unS
set_instance
-design design 1.1 S S S NP S S S
-model macro_model 1.1 S S S NP S S S
-port_mapping port_mapping_list 1.1 S 6.2 6.2 NP S S S
-domain_mapping domain_mapping_list 1.1 S 8.2 8.2 NP S S S
-parameter_mapping parameter_mapping_list 1.1 S N/A N/A NP N/A U S
set_macro_model 1.1 S 8.2 8.2 NP S S S
set_power_mode_control_group 1.1
-name group NP 9.2 9.2 NP N/A U S
-domains domain_list NP 9.2 9.2 NP N/A U S
-groups group_list NP 9.2 9.2 NP N/A U N/A
set_power_target 1.1
-leakage float N/A N/A N/A N/A S N/A N/A
-dynamic float N/A N/A N/A N/A S N/A N/A
set_power_unit 1.1 N/A N/A N/A N/A S N/A S
set_register_naming_style 1.1 S NP NP N/A S U S
set_switching_activity 1.1 N/A
-all NP NP N/A S N/A S
-pins pin_list NP NP N/A S N/A S
-instances instance_list NP NP N/A S N/A S
-hierarchical NP NP N/A S N/A S
-probability float NP NP N/A S N/A S
-toggle_rate float NP NP N/A S N/A S
-clock_pins pin_list NP NP N/A N/A N/A N/A
-toggle_percentage float NP NP N/A N/A N/A N/A
389 -mode mode
January 31, 2010 Cadence Methodology Guide 2011 CadenceNP NP
Design Systems, N/AAll rights
Inc. N/A reserved
N/A S
 IUS IUS
Ver CLP PD RC ET EDI Comments
Verilog VHDL
set_time_unit 1.1 N/A 8.2s8 8.2s8 N/A S N/A S
set_wire_feedthrough_ports 1.1 S NP NP N/A S N/A S
upd_isolation_rules 1.1
-names rule_list S U U N/A S S S
-location {from | to} S U U N/A S S S
-within_hierarchy instance U N/A N/A N/A S N/A S
-cells cell_list S N/A N/A N/A S S S
-prefix string S N/A N/A N/A S S S
-open_source_pins_only S N/A N/A N/A N/A N/A S
upd_level_shifter_rules 1.1
-names rule_list S U U N/A S S S
-location {from | to} S U U N/A S N/A S
-within_hierarchy instance NP P P N/A S N/A S
-cells cell_list S U U N/A S S S
-prefix string S U U N/A S S S
upd_nominal_condition 1.1
-name condition N/A N/A N/A N/A S N/A S
-library_set library_set N/A N/A N/A N/A S N/A S
upd_power_domain
-name domain 1.1 S 8.2s8 8.2 s8 N/A N/A N/A S
-primary_power_net net 1.1 S N/A N/A N/A N/A N/A S
-primary_ground_net net 1.1 S N/A N/A N/A N/A N/A S
-equivalent_power_nets list_of_power_nets 1.1 S NP NP N/A N/A N/A S
-equivalent_ground_nets list_of_ground_nets 1.1 S NP NP N/A N/A N/A S
-pmos_bias_net net 1.1 S N/A N/A N/A N/A N/A N/A
-nmos_bias_net net 1.1 S N/A N/A N/A N/A N/A N/A
EDI - query by
-user_attributes string_list 1.1 N/A NP NP N/A N/A N/A S
"getCPFUserAttributes"
-transition_slope [float:]float 1.1 N/A 8.2s8 8.2 s8 N/A N/A N/A N/A
-transition_latency {from_nom latency_list} 1.1 N/A U U N/A N/A N/A N/A
-transition_cycles {from_nom cycle_list clock_pin} 1.1 N/A U U N/A N/A N/A N/A

390 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IUS IUS
Ver CLP PD RC ET EDI Comments
Verilog VHDL
upd_power_mode
-name mode 1.1 N/A N/A N/A N/A S N/A S
-activity_file file 1.1 N/A N/A N/A N/A S N/A N/A
-activity_file_weight weight 1.1 N/A N/A N/A N/A S N/A N/A
-sdc_files sdc_file_list 1.1 N/A N/A N/A N/A S N/A S
-setup_sdc_files sdc_file_list 1.1 N/A NP NP N/A N/A N/A N/A
-hold_sdc_files sdc_file_list 1.1 N/A NP NP N/A N/A N/A N/A
-peak_ir_drop_limit domain_voltage_list 1.1 N/A N/A N/A N/A N/A N/A S
-average_ir_drop_limit domain_voltage_list 1.1 N/A N/A N/A N/A n/A N/A S
-leakage_power_limit float 1.1 N/A N/A N/A N/A N/A N/A N/A
-dynamic_power_limit float 1.1 N/A N/A N/A N/A N/A N/A N/A
upd_power_switch_rule
-name string 1.1 S N/A N/A N/A N/A S S
-enable_condition_1 expression 1.1 S N/A N/A N/A N/A S S
-enable_condition_2 expression 1.1 S N/A N/A N/A N/A S S
-acknowledge_receiver expression 1.1only S N/A N/A N/A N/A N/A S
-acknowledge_receiver_1 expression 1.1 S NP NP N/A N/A N/A S
-acknowledge_receiver_2 expression 1.1 S NP NP N/A N/A N/A S
-cells cell_list 1.1 S N/A N/A N/A N/A N/A S
-gate_bias_net power_net 1.1 U N/A N/A N/A N/A N/A N/A
-prefix string 1.1 S N/A N/A N/A N/A N/A S
-peak_ir_drop_limit float 1.1 N/A N/A N/A N/A N/A N/A S
-average_ir_drop_limit float 1.1 N/A N/A N/A N/A N/A N/A S
upd_state_retention_rules 1.1
-names rule_list S N/A N/A N/A S S S RC-not complete S
-cell_type string S N/A N/A N/A S S S
RC: -cells options have some limitations
-cells cell_list S N/A N/A N/A S S S
when multiple cells are given
-set_reset_control S N/A N/A N/A N/A N/A N/A
391 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Library Related

Legend
P Planned
S Supported
U Unsupported
NP Not Planned
N/A Not Applicable

392 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IUS IUS
Ver CLP PD RC ET EDI Comments
Verilog VHDL
define_always_on_cell 1.1
-cells cell_list S S NP N/A S S S
-library_set library_set N/A N/A N/A N/A S S S
-power_switchable LEF_power_pin S N/A N/A N/A N/A N/A S
-ground_switchable LEF_ground_pin S N/A N/A N/A N/A N/A S
-power LEF_power_pin S N/A N/A N/A N/A N/A S
-ground LEF_ground_pin S N/A N/A N/A N/A N/A S
define_isolation_cell 1.1
-cells cell_list S S NP N/A S S S
-library_set library_set N/A S NP N/A S S S
-always_on_pins pin_list S S NP N/A S S S
-power_switchable LEF_power_pin S N/A N/A N/A N/A N/A S
-ground_switchable LEF_ground_pin S N/A N/A N/A N/A N/A S
-power LEF_power_pin S N/A N/A N/A N/A N/A S
-ground LEF_ground_pin S N/A N/A N/A N/A N/A S
-valid_location { from | to | on | off} S U U N/A S N/A S
-enable pin S S NP N/A S S S
-no_enable {high|low|hold} S U NP N/A N/A N/A 8.1
-non_dedicated S NP NP N/A N/A N/A S

393 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IUS IUS
Ver CLP PD RC ET EDI Comments
Verilog VHDL
define_level_shifter_cell 1.1
-cells cell_list S U U N/A S S S
-library_set library_set N/A U U N/A S S S
-always_on_pins pin_list N/A U U N/A S S S
-input_voltage_range {voltage |
S U U N/A S N/A S
voltage_range}
-output_voltage_range {voltage |
S U U N/A S N/A S
voltage_range}
-ground_input_voltage_range {voltage |
S U U N/A S N/A
voltage_range}
8.1
-ground_output_voltage_range {voltage |
S U U N/A S N/A
voltage_range}
-direction {up|down|bidir} S U U N/A S S S
-input_power_pin LEF_power_pin S N/A N/A N/A N/A N/A S
-output_power_pin LEF_power_pin S N/A N/A N/A N/A N/A S
-input_ground_pin LEF_ground_pin S N/A N/A N/A N/A N/A S
-output_ground_pin LEF_ground_pin S N/A N/A N/A N/A N/A S
-ground LEF_ground_pin S N/A N/A N/A N/A N/A S
-power LEF_power_pin S N/A N/A N/A N/A N/A S EDI - these are for ground shifting
-enable pin S U NP N/A S U S
RC - valid_location either S from
-valid_location {to | from | either} N/A U NP N/A S N/A S
9.1.200 onwards.

394 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IUS IUS
Ver CLP PD RC ET EDI Comments
Verilog VHDL
define_open_source_input_pin 1.1
-cells cell_list S NP NP N/A N/A N/A S
-pin pin S NP NP N/A N/A N/A S
-library_set library_set N/A NP NP N/A N/A N/A S
define_power_clamp_cell 1.1
-cells cell_list S N/A N/A N/A N/A N/A N/A
-data pin S N/A N/A N/A N/A N/A N/A
-power pin S N/A N/A N/A N/A N/A N/A
-ground pin S N/A N/A N/A N/A N/A N/A
-library_set library_set N/A N/A N/A N/A N/A N/A N/A
define_power_switch_cell
-cells cell_list 1.1 S N/A N/A N/A N/A N/A S
-library_set library_set 1.1 N/A N/A N/A N/A N/A N/A S
-stage_1_enable expression 1.1 S N/A N/A N/A N/A N/A S
-stage_1_output expression 1.1 S N/A N/A N/A N/A N/A S
-stage_2_enable expression 1.1 S N/A N/A N/A N/A N/A S
-stage_2_output expression 1.1 S N/A N/A N/A N/A N/A S
-type {footer|header} 1.1 S N/A N/A N/A N/A N/A S
-enable_pin_bias [float:]float 1.1 S N/A N/A N/A N/A N/A N/A
-gate_bias_pin LEF_power_pin 1.1 U N/A N/A N/A N/A N/A N/A
-power_switchable LEF_power_pin 1.1 S N/A N/A N/A N/A N/A S
-power LEF_power_pin 1.1 S N/A N/A N/A N/A N/A S
-ground_switchable LEF_ground_pin 1.1 S N/A N/A N/A N/A N/A S
-ground LEF_ground_pin 1.1 S N/A N/A N/A N/A N/A S
-on_resistance float 1.1only N/A N/A N/A N/A N/A N/A S
-stage_1_on_resistance float 1.1 N/A N/A N/A N/A N/A N/A S
-stage_2_on_resistance float 1.1 N/A N/A N/A N/A N/A N/A S
-stage_1_saturation_current float 1.1 N/A N/A N/A N/A N/A N/A S
-stage_2_saturation_current float 1.1 N/A N/A N/A N/A N/A N/A S
EDI - these are used by
-leakage_current float 1.1 N/A N/A N/A N/A N/A N/A S
addPowerSwitch
395 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 IUS IUS
Ver CLP PD RC ET EDI Comments
Verilog VHDL
define_related_power_pins 1.1
-data_pins pin_list S N/A N/A N/A N/A N/A S
-cells cell_list S N/A N/A N/A N/A N/A S
-library_set library_set N/A N/A N/A N/A N/A N/A S
-power LEF_power_pin S N/A N/A N/A N/A N/A S
-ground LEF_ground_pin S N/A N/A N/A N/A N/A S

define_state_retention_cell 1.1
-cells cell_list S S NP N/A S S S
-library_set library_set N/A N/A NP N/A S S S
-cell_type string S S NP N/A S N/A S
-always_on_pins pin_list S S NP N/A S S S
-clock_pin pin S S NP N/A S S S
-restore_function expression S S NP N/A S S S
-save_function expression S S NP N/A S S S
-restore_check expression NP U NP N/A N/A S S
-save_check expression NP U NP N/A N/A S S
-always_on_componets component_list NP S NP N/A N/A N/A N/A
-power_switchable LEF_power_pin S N/A NP N/A N/A N/A S
-ground_switchable LEF_ground_pin S N/A NP N/A N/A N/A S
-power LEF_power_pin S N/A NP N/A N/A N/A S
-ground LEF_ground_pin S N/A NP N/A N/A N/A S

396 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved
 Whats new in V1.1

Improved navigation
Moved most custom shows to normal hyperlinks
Added back button to return to main topic
Updates
Updated LP flow section and organization
New
Added Name Map flow limitations
Added verification planning section
Added voltage regulator discussion
Added level shifter vs combo isolation cell discussion
PIA usage and examples
New naming style consistency section

397 January 31, 2010 Cadence Methodology Guide 2011 Cadence Design Systems, Inc. All rights reserved