EE141

EECS141
EE141 Lecture #11 1

HW 4 due on Friday
No re-grades on MT1 after next Wednesday
Project to be launched in week 7 stay tuned

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Score Histogram
12

10
Max: 40
8
Mean: 27.9
Median: 28.1
6
Stdev: 5.97
4

0
15-17

18-20

21-23

24-26

27-29

30-32

33-35

36-38

39-41
12-14

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EE141 Lecture #11 3

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= CGCS + CGSO = CGCD + CGDO

S D

= Cdiff = Cdiff
= CGCB
B

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EE141 Lecture #11 5

Capacitance (per area) from gate across

the oxide is WLCox, where Cox=ox/tox

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Cgate vs. VGS Cgate vs. operating region

(with VDS = 0)

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EE141 Lecture #11 7

Off/Lin/Sat CGSO = CGDO = COW

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Fringing fields

n+ n+

Cross section

COV not just from metallurgic overlap get fringing

fields too

Typical value: ~0.2fFW(in m)/edge

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EE141 Lecture #11 9

NA+
Bottom
Side wall
Area cap
W Source
Cbottom = CjLSW ND
Bottom

Sidewalls xj Side wall

Perimeter cap Channel
LS Substrate
Csw = Cjsw(2LS+W)
NA

GateEdge
Cge = CjgateW
Usually automatically included in the SPICE model
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Junction caps
are nonlinear
CJ is a
function of
junction bias

SPICE model
equations:
Area CJ = area CJ0 / (1+ |VDB|/)mj
Perimeter CJ = perim CJSW / (1 + |VDB|/)mjsw
Gate edge CJ = W CJgate / (1 + |VDB|/)mjswg

How do we deal with nonlinear capacitance?

EECS141
EE141 Lecture #10 11

Replace non-linear capacitance by

large-signal equivalent linear capacitance
which displaces equal charge over voltage swing of interest

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Gate-Channel Capacitance
CGC 0 (|VGS| < |VT|)
CGC = CoxWLeff (Linear)
50% G to S, 50% G to D
CGC = (2/3)CoxWLeff (Saturation)
100% G to S

Gate Overlap Capacitance

CGSO = CGDO = COW (Always)

Junction/Diffusion Capacitance
Cdiff = CjLSW + Cjsw(2LS + W) + CjgW (Always)

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EE141 Lecture #10 15

V DD

Wp = Wn

V in V out

Wn

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EE141 Lecture #10 17

For DC VTC, IDn = IDp

Graphically, looking for intersections of NMOS and
PMOS IV characteristics
To put IV curves on the same plot, PMOS IV is
flipped since |VDSp| = VDD Vout
Also, I |VGSp| = Vdd - Vin

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1.8

1.7

1.6

1.5

1.4
V (V)

1.3
M

1.2

1.1

0.9

0.8 0 1
10 10
W p /W n

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1.8

1.7

1.6

1.5

1.4
V (V)

1.3
M

1.2

1.1

0.9

0.8
0 1
10 10
W /W
p n

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A simplified approach

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EE141 Lecture #10 23

Gain=-1

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2.5

2
Wider
PMOS
1.5
Vout(V)

Symmetrical

1
Wider
NMOS

0.5

0
0 0.5 1 1.5 2 2.5
Vin (V)

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2.5

2
Fast PMOS
Slow NMOS
1.5
Vout(V)

Nominal

1
Fast NMOS
Slow PMOS

0.5

0
0 0.5 1 1.5 2 2.5
Vin (V)

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Not all transistors are alike

Impacts parameters such as reliability and performance

Define process corners: SS, FF, SF, FS

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Discharging a capacitor

We modeled this with:

tp = ln (2) RC

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Real transistors arent exactly resistors

Look more like current sources in saturation

Two questions:
Which region of IV curve determines delay?
How can that match up with the RC model?

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With a step input:

VDD VDD/2 ID VGS = VDD

VDS
VVSAT VDD /2 VDD

Transistor is in (velocity) saturation during entire transition

from VDD to VDD/2

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In saturation, transistor basically acts like a current source:

VOUT
VOUT
VDD
IDSAT C
VDD/2

t
tp

VOUT = VDD - (IDSAT/C)t tp = C(VDD/2)/IDSAT

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Including output conductance:

VOUT

IDSAT 1/(IDSAT) C

For small :

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Transistor current not linear on VOUT how is the RC

model going to work?

Look at waveforms:

Voltage looks like a

ramp for RC too

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Match the delay of the RC model with the actual delay:

Often just:

Note that the book uses a different method and gets

0.75VDD/IDSAT instead of ~0.72VDD/IDSAT.

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