RESEARCH ON DATA MINING TECHNOLOGIES FOR PREDICTION

OF DIABETES USING AZURE WEB SERVICES

1
TANZEELA JAVID, 2ABHINAV BANSAL
1Vaagdevi College of Engg. Pune, Andra Pradesh London
2PECUniversity of Technology, Chandigarh
Email: 1 [email protected], [email protected]
Contact: 1+91-, 2+91-983738892992

Abstract:. This research is based on classification model by using cloud platform Microsoft Azure that predicts
the occurrence of Diabetes in an individual on the basis of non-pathological parameters age, gender, family
history of being diabetic, smoking and drinking habits, frequency of thirst and urination, weight height and
fatigue. Six different algorithms have been compared .

Index terms: Area-efficient, Low power, CSLA, Binary to excess one converter, Multiplexer.

I. INTRODUCTION delay. The area evaluation is done by counting the

total number of AOI gates required for each logic
Diabetes is a chronic disease that contributes to a block.
significant portion of the healthcare expenditure for a
nation as individuals with diabetes need continuous Based on this approach, the CSLA adder
medical care. In order to prevent or delay the onset of blocks of 2:1 mux, Half Adder (HA), and FA are
diabetes, it is necessary to identify high risk evaluated and listed in Table I.
populations and introduce behavior modifications as
early as possible. One of the most accurate tests of
diabetes is through the analysis of fasting blood
sugar, but it is invasive and costly. Furthermore, it is
only useful when the individual is already displaying
symptoms i.e., making a diagnosis, which is
considered too late to be an effective screening
mechanism. Therefore, a reliable non-invasive
inexpensive test to predict high risk individuals in
advance is needed.
The study of a particular disease needs careful
observation of various parameters that form the
symptoms of that disease. In our work we are going
to develop an expert system that will predict the
occurrence of diabete with a good amount of support
and confidence. The expert systems always have
benefits over manual system and can be trained to
deliver persistent and higher accuracy rates

II. DELAY AND AREA EVALUATION OF

THE BASIC ADDER BLOCKS

to excess-1 code converters (BEC) to

improve the speed of addition. This logic can be
implemented with any type of adder to further
improve the speed. Using Binary to Excess-1 Figure 1: Delay and Area evaluation of an XOR gate.
Converter (BEC) instead of RCA in the regular Table 1
Delay and Area Evaluation of the Basic Blocks of CSLA
CSLA we can achieve lower area and power
consumption. The main advantage of this BEC logic
Basic Blocks Delay Area
comes from the lesser number of logic gates than the
Full Adder (FA) structure.and area equal to 1 unit. XOR 3 5
We then add up the number of gates in the longest 2:1 MUX 3 4
path of a logic block that contributes to the maximum Half Adder 3 6

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Full Adder 6 13

III. BASIC STRUCTURE OF BEC LOGIC

conventional carry select adder performs

better in terms of speed. The delay of our proposed
design increases lightly because of logic circuit
sharing sacrifices the length of parallel path.
However, the proposed area-efficient carry
select adder retains partial parallel computation
architecture as the conventional carry select adder
area and power consumption of the regular CSLA. To
replace the n-bit RCA, an n+1-bit BEC is required. A
structure and the function table of a 4-bit BEC are
shown in Figure.2 and Table .2, respectively.

Figure 3: Regular CSLA circuit

The structure of the 16-b regular SQRT CS

conventional carry select adder performs better in
terms of speed. The delay of our proposed design
increases lightly because of logic circuit sharing
sacrifices the length of parallel path.
However, the proposed area-efficient carry
select adder retains partial parallel computation
architecture as the conventional carry select adder
{c6, sum [6:4]} = c3 [t=10] +mux (5)
{c10, sum [10:7]} = c6 [t=13] +mux (6)
{Cout, sum [15:11]}=c10 [t=16] +mux. (7)

Figure 2: 4-Bit BEC

3) The one set of 2-b RCA in group2 has 2
The Boolean expressions of the 4-bit BEC FA for Cin=1 and the other set has 1 FA and 1 HA
are for Cin=0. Based on the area count of Table I, the
X0 = ~B0 (1) total number of gate counts in group2 is determined
X1 = B0^B1 (2) as follows:
X2 = B2^ (B0 & B1) (3)
X3 = B3^ (B0 & B1 & B2) (4)
Gate Count = 57 (FA+HA+MUX) (8)
Table.2 Function table of the 4-bit BEC
FA=39(3*13) (9)
HA=6(1*6) (10)
MUX=12(3*4) (11)

4) Similarly, the estimated maximum delay

and area of the other groups in the regular SQRT
CSLA are evaluated and listed in Table 3.
Table 3

Group Delay Area

IV. BASIC STRUCTURE OF REGULAR 16- 2 11 57

BIT CSLA 3 13 87
4 16 117
5 19 147

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V. DELAY AND AREA EVALUATION OF

CSLA USING BEC CONVERTER

.
The structure of the proposed 16-b SQRT
CSLA using BEC for RCA with Cin=1 to optimize
the area and power is shown in Fig. 4. We again split
the structure into five groups. The steps leading to the
conventional carry select adder performs better in
terms of speed. The delay of our proposed design
increases lightly because of logic circuit sharing
sacrifices the length of parallel path
However, the proposed area-efficient carry Figure 4: CSLA circuit using BEC Converter
select adder retains partial parallel computation
architecture as the conventional carry select adder) VI. SIMULATIONS AND EXPERIMENTAL
are depending on s3and mux and partial c3 (input to RESULTS
mux) and mux, respectively. The sum2 depends on c1
The proposed solutions have been designed
and mux.
using Xilinx. The area-efficient carry select adder can
also achieve an outstanding performance in power
2) For the remaining groups the arrival time
consumption. Power consumption can be greatly
of mux selection input is always greater than the
saved in our proposed area-efficient carry select
arrival time of data inputs from the BECs. Thus, the
delay of the remaining groups depends on the arrival
time of mux selection input and the mux delay.

3) The area count of group2 is determined as

follows:

Gate count =43(FA+HA+MUX+BEC) (12)

FA= 13(1*13) (13)
HA=6(1*6) (14)
AND=NOT=1 (15)
XOR=10(2*5) (16)
MUX=12(3*4) (17)

4) Similarly, the estimated maximum delay

and area of the other groups of the modified SQRT adder because we only need one XOR gate and one
CSLA are evaluated and listed in Table 4. INV gate in each summation operation as well as one
Table 4 AND gate and one OR gate in each carry-out
operation after logic simplification and sharing partial
Group Delay Area circuit. Because of hardware sharing, we can also
significantly reduce the occurring chance of glitch.
Besides, the improvement of power consumption can
2 13 43 be more obvious as the input bit number increases.
3 16 61
4 19 84
5 22 107 Figure 5: Simulated Results

Comparing Tables 3and 4, it is clear that the The conventional carry select adder
proposed modified CSLA saves 113 gate areas than performs better in terms of speed. The delay of our
the regular CSLA, with only 11 increases in gate proposed design increases lightly because of logic
delays. circuit sharing sacrifices the length of parallel path.
However, the proposed area-efficient carry
select adder retains partial parallel computation
architecture as the conventional carry select adder
design; the delay increment of the proposed design is
similar to that in the conventional design as the input
bit number increases. We also simulated the delay
performance in the proposed area-efficient adder and
conventional carry select adder with 4, 8, 16, and 32-
bit respectively.

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CONCLUSION

Implemented with any type of adder to

further improve the speed. Using Binary to Excess-1
Converter (BEC) instead of RCA in the regular
CSLA we can achieve lower area and power
consumption. The main advantage of this BEC logic
comes from the lesser number of logic gates than the
Full Adder (FA) structure.is therefore, low area, low
power, simple and efficient A to excess-1 code
converters (BEC) to improve the speed of addition.
This logic can be for VLSI hardware implementation.

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