TDA7563

MULTIFUNCTION QUAD POWER AMPLIFIER

WITH BUILT-IN DIAGNOSTICS FEATURES

DMOS POWER OUTPUT MULTIPOWER BCD TECHNOLOGY

NON-SWITCHING HI-EFFICIENCY
HIGH OUTPUT POWER CAPABILITY 4x28W/ MOSFET OUTPUT POWER STAGE
4 @ 14.4V, 1KHZ, 10% THD, 4x40W EIAJ


MAX. OUTPUT POWER 4x72W/2
FULL I2C BUS DRIVING:
( s ) FLEXIWATT27

ST-BY
c t ORDERING NUMBER: TDA7563
INDEPENDENT FRONT/REAR SOFT PLAY/
MUTE
d u DESCRIPTION
SELECTABLE GAIN 30dB
r o s )
The TDA7563 is a new BCD technology Quad
16dB (FOR LOW NOISE LINE OUTPUT
FUNCTION)
e P c t (
Bridge type of car radio amplifier in Flexiwatt27
package specially intended for car radio applica-
HIGH EFFICIENCY ENABLE/DISABLE
I2C BUS DIGITAL DIAGNOSTICS
l e t d u tions. Thanks to the DMOS output stage the
TDA7563 has a very low distortion allowing a clear
FULL FAULT PROTECTION
s o r o powerful sound. Among the features, its superior
DC OFFSET DETECTION
FOUR INDEPENDENT SHORT CIRCUIT
O b e P efficiency performance coming from the internal ex-
clusive structure, makes it the most suitable device

PROTECTION
- l e t to simplify the thermal management in high power
CLIPPING DETECTOR PIN WITH

( s ) o
sets.The dissipated output power under average
listening condition is in fact reduced up to 50%

SELECTABLE THRESHOLD (2%/10%)
ST-BY/MUTE PIN
c t b s when compared to the level provided by conven-
tional class AB solutions.This device is equipped

ESD PROTECTION
d u
LINEAR THERMAL SHUTDOWN

- O with a full diagnostics array that communicates the

r o s ) status of each speaker through the I 2C bus.

BLOCK DIAGRAM

e P c t (
l e t d u
ST-BY/MUTE
CLK DATA VCC1 VCC2

o
CD_OUT

o
Thermal Clip

r
I2CBUS Protection Reference

s
Detector
Mute1 Mute2 & Dump

O b e P IN RF F OUT RF+

t
16/30dB

e
Short Circuit
OUT RF-

o l IN RR R
Protection &
Diagnostic
OUT RR+

b s 16/30dB

Short Circuit OUT RR-

O
Protection &
IN LF Diagnostic
F OUT LF+
16/30dB

Short Circuit OUT LF-

Protection &
Diagnostic
IN LR R OUT LR+
16/30dB

Short Circuit OUT LR-

Protection &
Diagnostic

SVR AC_GND RF RR LF LR TAB S_GND

PW_GND

May 2003 1/20

 TDA7563

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
Vop Operating Supply Voltage 18 V
VS DC Supply Voltage 28 V
Vpeak Peak Supply Voltage (for t = 50ms) 50 V
VCK CK pin Voltage 6 V
VDATA Data Pin Voltage 6 V
IO Output Peak Current (not repetitive t = 100ms) 8 A
IO Output Peak Current (repetitive f > 10Hz) 6 A
Ptot Power Dissipation Tcase = 70C 85 W
Tstg, Tj Storage and Junction Temperature

( s ) -55 to 150 C

c t
THERMAL DATA
d u
r o s )
(
Symbol Parameter Value Unit
Rth j-case Thermal Resistance Junction to case
e P c t Max. 1 C/W

l e t d u
PIN CONNECTION (Top view)

s o r o
O b e P 27 TAB

- l e t 26 DATA

( s ) o
25
24
PW_GND RR
OUT RR-

c t b s 23 CK

d u - O 22
21
OUT RR+
VCC2

r o s ) 20 OUT RF-

e P c t ( 19
18
PW_GND RF
OUT RF+

l e t d u 17
16
AC GND
IN RF

s o r o 15 IN RR

O b e P 14
13
S_GND
IN LR

l e t 12 IN LF

o
11 SVR

b s 10
9
OUT LF+
PW_GND LF

O 8
7
6
OUT LF-
VCC1
OUT LR+
5 CD-OUT
4 OUT LR-
3 PW_GND LR
2 STBY
1 TAB
D00AU1230

2/20
 TDA7563

Figure 1. Application Circuit

C8 C7
0.1F 3300F
Vcc1 Vcc2
V(4V .. VCC)
7 21 +
2 18
19 OUT RF
DATA 26
20
I2C BUS -
+
CLK 23 22
C1 0.22F 25 OUT RR
IN RF 16 24

)
-
+

IN RR
C2 0.22F
15
t ( s 10
9 OUT LF

C3 0.22F
u c 8
-

d
+
IN LF 12 6

C4 0.22F
r o s ) 3 OUT LR

IN LR 13

e P c t ( 4
-

S-GND

l e
14t 17

d u 11 5
1, 27
TAB

s o C5
r o C6
47K
V

O b 1F

e P 10F
CD OUT
D00AU1231A

- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b

3/20
 TDA7563

ELECTRICAL CHARACTERISTICS
(Refer to the test circuit, VS = 14.4V; RL = 4; f = 1KHz; GV = 30dB; Tamb = 25C; unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
POWER AMPLIFIER
VS Supply Voltage Range 8 18 V
Id Total Quiescent Drain Current 170 300 mA
PO Output Power EIAJ (VS = 13.7V) 35 40 W
THD = 10% 25 28 W
THD = 1% 22 W
RL = 2; EIAJ (VS = 13.7V) 55 62 W
RL = 2; THD 10% 40 46 W
RL = 2; THD 1%
RL = 2; MAX POWER
( s ) 35
72
W
W
THD Total Harmonic Distortion
c t
PO = 1W to 10W; STD MODE 0.03 0.1 %

d
HE MODE; PO = 8Wu
HE MODE; PO = 1.5W 0.02
0.15
0.1
0.5
%
%

r o
PO = 1-10W, f = 10kHz
s ) 0.2 0.5 %

e P
GV = 16dB; STD Mode

c t ( 0.02 0.05 %

CT Cross Talk
l e t
VO = 0.1 to 5VRMS

d u
f = 1KHz to 10KHz, Rg = 600 50 60 dB
RIN Input Impedance
s o r o 60 100 130 K
GV1
GV1
Voltage Gain 1
Voltage Gain Match 1
O b e P 29.5
-1
30 30.5
1
dB
dB
GV2 Voltage Gain 2
- l e t 15.5 16 16.5 dB
GV2
s
Voltage Gain Match 2

( ) o -1 1 dB
EIN1
c t
Output Noise Voltage 1
b s Rg = 600 20Hz to 22kHz 50 100 mV
EIN2

d u
Output Noise Voltage 2

- O Rg = 600; GV = 16dB
20Hz to 22kHz
15 30 mV

SVR
r o s )
Supply Voltage Rejection f = 100Hz to 10kHz; Vr = 1Vpk; 50 60 dB

BW
e P c t
Power Bandwidth ( Rg = 600
100 KHz
ASB
l e t d u
Stand-by Attenuation 90 110 dB

s o
ISB
o
Stand-by Current

r
2 20 A

P
AM Mute Attenuation 80 100 dB

O b VOS
e
Offset Voltage Mute & Play -100 0 100 mV
VAM

l e t Min. Supply Mute Threshold 7 7.5 8 V

s o
TON
TOFF
Turn ON Delay
Turn OFF Delay
D2/D1 (IB1) 0 to 1
D2/D1 (IB1) 1 to 0
5
5
20
20
ms
ms

O b VSBY
VMU
St-By/Mute pin for St-By
St-By/Mute pin for Mute
0
3.5
1.5
5
V
V
VOP St-By/Mute pin for Operating 7 VS V
IMU St-By/Mute pin Current VSTBY/MUTE = 8.5V 20 40 A
VSTBY/MUTE < 1.5V 0 10 A
CDLK Clip Det High Leakage Current CD off 0 15 A
CDSAT Clip Det Sat. Voltage CD on; ICD = 1mA 300 mV
CDTHD Clip Det THD level D0 (IB1) = 1 5 10 15 %

4/20
 TDA7563

ELECTRICAL CHARACTERISTICS (continued)

(Refer to the test circuit, VS = 14.4V; RL = 4; f = 1KHz; GV = 30dB; Tamb = 25C; unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
D0 (IB1) = 0 1 2 3 %
TURN ON DIAGNOSTICS 1 (Power Amplifier Mode)
Pgnd Short to GND det. (below this Power Amplifier in st-by 1.2 V
limit, the Output is considered in
Short Circuit to GND)
Pvs Short to Vs det. (above this limit, Vs -1.2 V
the Output isconsidered in Short
Circuit to VS)
Pnop Normal operation 1.8 Vs -1.8 V
thresholds.(Within these limits,

( s )
the Output is considered without
faults).
c t
Lsc Shorted Load det.

d u 0.5

Lop
Lnop
Open Load det.
Normal Load det.
r o s )
130
1.5 70
TURN ON DIAGNOSTICS 2 (Line Driver Mode)

e P c t (
Pgnd Short to GND det. (below this

l
limit, the Output is considered in
e t d u
Power Amplifier in st-by 1.2 V

Pvs
Short Circuit to GND)

s o
Short to Vs det. (above this limit, r o Vs -1.2 V
b
the Output isconsidered in Short

O e P
Pnop
Circuit to VS)
Normal operation
- l e t 1.8 Vs -1.8 V

) o
thresholds.(Within these limits,

( s
faults).
c b s
the Output is considered without
t
Lsc
Lop
d u
Shorted Load det.
Open Load det.
- O 400
1.5

Lnop
r o
Normal Load det.
s ) 4.5 200

P t (
PERMANENT DIAGNOSTICS 2 (Power Amplifier Mode or Line Driver Mode)

e c
Pgnd

l e tShort to GND det. (below this

u
limit, the Output is considered in
d
Power Amplifier in Mute or Play,
one or more short circuits
1.2 V

s o
Pvs o
Short Circuit to GND)

r
Short to Vs det. (above this limit,
protection activated
Vs -1.2 V

O b e P
the Output is considered in Short
Circuit to VS)
Pnop

l e tNormal operation thresholds.

(Within these limits, the Output is
1.8 Vs -1.8 V

s o considered without faults).

O b LSC Shorted Load Det. Pow. Amp. mode

Line Driver mode
0.5
1.5


VO Offset Detection Power Amplifier in play, 1.5 2 2.5 V
AC Input signals = 0
I2C BUS INTERFACE
SCL Clock Frequency 400 KHz
VIL Input Low Voltage 1.5 V
VIH Input High Voltage 2.3 V

5/20
 TDA7563

Figure 2. Quiescent Current vs. Supply Voltage Figure 5. Distortion vs. Output Power (4, STD)
Id (mA) THD (%)
250 10

230 STANDARD MODE

Vin = 0 Vs = 14.4 V
210 NO LOADS RL = 4 Ohm
190 1

170
f = 10 KHz
150

130 0.1

110 f = 1 KHz

90

( s )
70
8 10 12 14
c t 16 18
0.01
0.1 1 10
Vs (V)

d u Po (W)

Figure 3. Output Power vs. Supply Voltage (4)

r o s ) Figure 6. Distortion vs. Output Power (4, HI-EFF)

70
Po (W)

e P c t ( THD (%)

t
10
65
60
l e d u
Po-max
HI-EFF MODE
55 RL = 4 Ohm
f = 1 KHz
s o r o 1
Vs = 14.4 V
RL = 4 Ohm
50
45

O b e P THD = 10 %
f = 10 KHz
40
35
- l e t 0.1

30

( s ) o f = 1 KHz
25
20

c t b s THD = 1 % 0.01
15
10
d u - O
5
8 9
r o 10

s )
11 12 13 14 15 16 17 18
0.001
0.1 1 10

e P c t ( Vs (V) Po (W)

l e t d u
Figure 4. Output Power vs. Supply Voltage (2) Figure 7. Distortion vs. Output Power (2, STD)

s
100
o Po (W)

r o 10
THD (%)

O b90

e P Po-max HI-EFF MODE

80

70
l e t RL = 2 Ohm
f = 1 KHz 1
Vs = 14.4 V
RL = 2 Ohm

s
60
o THD = 10 % f = 10 KHz

O b50

40 0.1
f = 1 KHz
30
THD = 1 %
20

10 0.01
8 9 10 11 12 13 14 15 16 0.1 1 10
Vs (V) Po (W)

6/20
 TDA7563

Figure 8. Distortion vs. Frequency (4) Figure 11. Supply Voltage Rejection vs. Freq.
THD (%) SVR (dB)
10 90

80

STANDARD MODE
Vs = 14.4 V 70
1
RL = 4 Ohm
Po = 4 W 60

50
0.1 STD & HE MODE
40 Rg = 600 Ohm
Vripple = 1 Vpk
30

( s )
0.01
10 100 1000 10000
20
10
c t 100 1000 10000
f (Hz)

d u f (Hz)

Figure 9. Distortion vs. Frequency (2)

r o )
Figure 12. Power Dissipation & Efficiency vs.
s
e P c (
Output Power (4, STD, SINE)
t
Ptot (W) n (%)

10
THD (%)

l e t 90

80
d u STANDARD MODE n
90

80

s o r
70o Vs = 14.4 V
RL = 4 x 4 Ohm
70
STANDARD MODE
Vs = 14.4 V
RL = 2 Ohm
O b e P 60
f = 1 KHz SINE
60
1
Po = 4 W

- l e t 50 50

( s ) o 40 40

0.1
c t b s 30
Ptot
30

d u - O 20 20

r o s ) 10 10

0.01
10

e P 100

c t ( 1000 10000
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
0

t
f (Hz) Po (W)

l e d u
Figure 10. Crosstalk vs. Frequency

s o r o Figure 13. Power Dissipation & Efficiency vs.

Output Power (4W, HI-EFF, SINE)

O b P
CROSSTALK (dB)

e 90
Ptot (W) n (%)
90
90

80
l e t 80
HI-EFF MODE
Vs = 14.4 V
n
80

o
RL = 4 x 4 Ohm
70 f = 1 KHz SINE 70
70

b s 60 60

O 60

50 STANDARD MODE
RL = 4 Ohm
50

40
Ptot
50

40
Po = 4 W
40 Rg = 600 Ohm 30 30

20 20
30
10 10
20
10 100 1000 10000 0 0
f (Hz) 0.1 1 10
Po (W)

7/20
 TDA7563

Figure 14. Power Dissipation vs. Average Figure 15. Power Dissipation vs. Average
Ouput Power (Audio Program Ouput Power (Audio Program
Simulation, 4) Simulation, 2)
Ptot (W) Ptot (W)
45 90

40 80
Vs = 14 V STD MODE
35 RL = 4 x 4 Ohm 70
GAUSSIAN NOISE Vs = 14 V STD MODE
60 RL = 4 x 2 Ohm
30
GAUSSIAN NOISE
CLIP
25 START 50
CLIP
20 HI-EFF MODE 40 START

15 30

( s ) HI-EFF MODE
10

c t 20

d u 10

o
0 0
0 1 2
Po (W)
3 4

P r 5

( s )0 1 2 3 4
Po (W)
5 6 7 8 9

t e c t
DIAGNOSTICS FUNCTIONAL DESCRIPTION:
a) TURN-ON DIAGNOSTIC
l e d u
s o r o
It is activated at the turn-on (stand-by out) under I2Cbus request. Detectable output faults are:
SHORT TO GND
O b e P
SHORT TO Vs
- l e t
SHORT ACROSS THE SPEAKER

( s ) o
OPEN SPEAKER

c t b s
To verify if any of the above misconnections are in place, a subsonic (inaudible) current pulse (fig. 16) is inter-

d u O
nally generated, sent through the speaker(s) and sunk back.The Turn On diagnostic status is internally stored
-
r o
until a successive diagnostic pulse is requested (after a I2C reading).

s )
If the "stand-by out" and "diag. enable" commands are both given through a single programming step, the pulse
P t (
takes place first (power stage still in stand-by mode, low, outputs= high impedance).
e c
l e t d u
Afterwards, when the Amplifier is biased, the PERMANENT diagnostic takes place. The previous Turn On state
is kept until a short appears at the outputs.

s o r o
O b P
Figure 16. Turn - On diagnostic: working principle

e
l e t Vs~5V I (mA)

s o Isource Isource

O b CH+
Isink

CH-

Isink
~100mS t (ms)
Measure time

8/20
 TDA7563

Fig. 17 and 18 show SVR and OUTPUT waveforms at the turn-on (stand-by out) with and without TURN-ON
DIAGNOSTIC.

Figure 17. SVR and Output behaviour (CASE 1: without turn-on diagnostic)

Vsvr
Out
Permanent diagnostic
acquisition time (100mS Typ)

( s )
c t
d u
Bias (power amp turn-on)

r o s )
Diagnostic Enable
(Permanent) FAULT
t

e P c t ( event Read Data

I2CB DATA

l e t d u Permanent Diagnostics data (output)

permitted time

s o r o
b P
Figure 18. SVR and Output pin behaviour (CASE 2: with turn-on diagnostic)

O e
Vsvr
- l e t
Out
( s ) o
Turn-on diagnostic

c t s
acquisition time (100mS Typ)

b
Permanent diagnostic
acquisition time (100mS Typ)

d u - O
r o s )
e P c t (
l e t d u
s o r o t

P
FAULT
b
Diagnostic Enable Turn-on Diagnostics data (output)
Diagnostic Enable
(Turn-on) permitted time
(Permanent) event

O t e
o l e Bias (power amp turn-on)
permitted time
Read Data Permanent Diagnostics data (output)

s
permitted time

O b I2CB DATA

9/20
 TDA7563

The information related to the outputs status is read and memorized at the end of the current pulse top. The
acquisition time is 100 ms (typ.). No audible noise is generated in the process. As for SHORT TO GND / Vs the
fault-detection thresholds remain unchanged from 30 dB to 16 dB gain setting. They are as follows:

S.C. to GND x Normal Operation x S.C. to Vs

0V 1.2V 1.8V VS-1.8V VS-1.2V VS

D01AU1253

( s )
Concerning SHORT ACROSS THE SPEAKER / OPEN SPEAKER, the threshold varies from 30 dB to 16 dB
gain setting, since different loads are expected (either normal speaker's impedance or high impedance). The
values in case of 30 dB gain are as follows:
c t
d u
S.C. across Load x
r o
Normal Operation
s )
x Open Load

e P c t (
0V 0.5
l e t1.5
d u70 130 Infinite

o
D01AU1254

s o r
O b e P
If the Line-Driver mode (Gv= 16 dB and Line Driver Mode diagnostic = 1) is selected, the same thresholds will
change as follows:
- l e t
( s ) o
c t
S.C. across Load
b s x Normal Operation x Open Load

d u - O
r
0o s ) 1.5 4.5 200 400 infinite

e P c t ( D01AU1252

l e t d u
o r o
b) PERMANENT DIAGNOSTICS.
s
O b P
Detectable conventional faults are:

e
l e t
SHORT TO GND
SHORT TO Vs

s o
SHORT ACROSS THE SPEAKER

O b
The following additional features are provided:
OUTPUT OFFSET DETECTION
The TDA7563 has 2 operating statuses:
1 RESTART mode. The diagnostic is not enabled. Each audio channel operates independently from each
other. If any of the a.m. faults occurs, only the channel(s) interested is shut down. A check of the output
status is made every 1 ms (fig. 19). Restart takes place when the overload is removed.
2 DIAGNOSTIC mode. It is enabled via I2C bus and self activates if an output overload (such to cause
the intervention of the short-circuit protection) occurs to the speakers outputs . Once activated, the di-
agnostics procedure develops as follows (fig. 20):

10/20
 TDA7563

To avoid momentary re-circulation spikes from giving erroneous diagnostics, a check of the output sta-
tus is made after 1ms: if normal situation (no overloads) is detected, the diagnostic is not performed and
the channel returns back active.
Instead, if an overload is detected during the check after 1 ms, then a diagnostic cycle having a duration
of about 100 ms is started.
After a diagnostic cycle, the audio channel interested by the fault is switched to RESTART mode. The
relevant data are stored inside the device and can be read by the microprocessor. When one cycle has
terminated, the next one is activated by an I2C reading. This is to ensure continuous diagnostics
throughout the car-radio operating time.
To check the status of the device a sampling system is needed. The timing is chosen at microprocessor
level (over half a second is recommended).

( s )
Figure 19. Restart timing without Diagnostic Enable (Permanent) - Each 1mS time, a sampling of
the fault is done
c t
d u
r o 1mS
s ) Out
1-2mS 1mS 1mS

e P
1mS

c t (
l e t d u
s o r o t
Overcurrent and short
circuit protection intervention

O b e P Short circuit removed

(i.e. short circuit to GND)

- l e t
( s ) o
t s
Figure 20. Restart timing with Diagnostic Enable (Permanent)
c b
d u - O
r o s )
1-2mS 100/200mS 1mS 1mS

e P c t (
l e t d u
s o r o t

O b e P
Overcurrent and short
circuit protection intervention Short circuit removed

l e t
(i.e. short circuit to GND)

s o
O b
OUTPUT DC OFFSET DETECTION
Any DC output offset exceeding +/- 2 V are signalled out. This inconvenient might occur as a consequence of
initially defective or aged and worn-out input capacitors feeding a DC component to the inputs, so putting the
speakers at risk of overheating.
This diagnostic has to be performed with low-level output AC signal (or Vin = 0).
The test is run with selectable time duration by microprocessor (from a "start" to a "stop" command):
START = Last reading operation or setting IB1 - D5 - (OFFSET enable) to 1

11/20
 TDA7563

STOP = Actual reading operation

Excess offset is signalled out if persistent throughout the assigned testing time. This feature is disabled if any
overloads leading to activation of the short-circuit protection occurs in the process.

MULTIPLE FAULTS
When more misconnections are simultaneously in place at the audio outputs, it is guaranteed that at least one
of them is initially read out. The others are notified after successive cycles of I2C reading and faults removal,
provided that the diagnostic is enabled. This is true for both kinds of diagnostic (Turn on and Permanent).
The table below shows all the couples of double-fault possible. It should be taken into account that a short circuit
with the 4 ohm speaker unconnected is considered as double fault.

Double fault table for Turn On Diagnostic

( s )
S. GND (so) S. GND (sk)
c t
S. Vs S. Across L. Open L.
S. GND (so) S. GND S. GND

d u
S. Vs + S. GND S. GND S. GND
S. GND (sk)
S. Vs
/
/
S. GND
/
r o S. Vs

s
S. Vs)
S. GND
S. Vs
Open L. (*)
S. Vs
S. Across L. / /

e P c t (/ S. Across L. N.A.
Open L. /

l e
/
t d u / / Open L. (*)

s o r o
S. GND (so) / S. GND (sk) in the above table make a distinction according to which of the 2 outputs is shorted

O b e P
to ground (test-current source side= so, test-current sink side = sk). More precisely, in Channels LF and RR, so
= CH+, sk = CH-; in Channels LR and RF, so = CH-, sk = CH+ .

- l e t
In Permanent Diagnostic the table is the same, with only a difference concerning Open Load(*) , which is not

s ) o
among the recognisable faults. Should an Open Load be present during the device's normal working, it would
(
t s
be detected at a subsequent Turn on Diagnostic cycle (i.e. at the successive Car Radio Turn on).

c b
FAULTS AVAILABILITY
d u - O
r o )
All the results coming from I2Cbus, by read operations, are the consequence of measurements inside a defined
s
e P c t (
period of time. If the fault is stable throughout the whole period, it will be sent out.

l e t
To guarantee always resident functions, every kind of diagnostic cycles (Turn on, Permanent, Offset) will be

d u
reactivate after any I2C reading operation. So, when the micro reads the I2C, a new cycle will be able to start,
but the read data will come from the previous diag. cycle (i.e. The device is in Turn On state, with a short to Gnd,

s o r o
then the short is removed and micro reads I2C. The short to Gnd is still present in bytes, because it is the result

O b P
of the previous cycle. If another I2C reading operation occurs, the bytes do not show the short). In general to
observe a change in Diagnostic bytes, two I2C reading operations are necessary.
e
l e t
o
THERMAL PROTECTION
s
O b
Thermal protection is implemented through thermal foldback (fig. 21). Thermal foldback begins limiting the audio
input to the amplifier stage as the junction temperatures rise above the normal operating range. This effectively
limits the output power capability of the device thus reducing the temperature to acceptable levels without totally
interrupting the operation of the device. The output power will decrease to the point at which thermal equilibrium
is reached. Thermal equilibrium will be reached when the reduction in output power reduces the dissipated pow-
er such that the die temperature falls below the thermal foldback threshold. Should the device cool, the audio
level will increase until a new thermal equilibrium is reached or the amplifier reaches full power. Thermal fold-
back will reduce the audio output level in a linear manner.

12/20
 TDA7563

Figure 21. Thermal Foldback Diagram

TH. WARN.
Vout ON

TH. SH. TH. SH. Tj ( C)

Vout
START END

( s )
c t
< TSD

d u > TSD (with same input

signal)
Tj ( C)

o
CD out

P r ( s )
t e c t
l e d u
s o r o Tj ( C)

I2C PROGRAMMING/READING SEQUENCES

O b e P
- l e t
s )
A correct turn on/off sequence respectful of the diagnostic timings and producing no audible noises could be as
follows (after battery connection):
( o
c t b s
TURN-ON: PIN2 > 7V --- 10ms --- (STAND-BY OUT + DIAG ENABLE) --- 500 ms (min) --- MUTING OUT

d u - O
TURN-OFF: MUTING IN --- 20 ms --- (DIAG DISABLE + STAND-BY IN) --- 10ms --- PIN2 = 0
Car Radio Installation: PIN2 > 7V --- 10ms DIAG ENABLE (write) --- 200 ms --- I2C read (repeat until All faults
disappear).
r o s )
P t (
OFFSET TEST: Device in Play (no signal) -- OFFSET ENABLE - 30ms - I2C reading (repeat I2C reading until
e c
l e t
high-offset message disappears).

d u
s o r o
O b e P
l e t
s o
O b

13/20
 TDA7563

I2C BUS INTERFACE

Data transmission from microprocessor to the TDA7563 and viceversa takes place through the 2 wires I2C BUS inter-
face, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).
Data Validity
As shown by fig. 22, the data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Start and Stop Conditions
As shown by fig. 23 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
( s )
Acknowledge
c t
d u
The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 24).
The receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so
that the SDAline is stable LOW during this clock pulse.
r o s )
* Transmitter

e P
master (P) when it writes an address to the TDA7563
c t (
** Receiver
l e t d u
slave (TDA7563) when the P reads a data byte from TDA7563

o r o
slave (TDA7563) when the P writes an address to the TDA7563
s
b P
master (P) when it reads a data byte from TDA7563

O e
-
Figure 22. Data Validity on the I2CBUS
l e t
( s ) o
SDA

c t b s
d u
SCL

- O
r o s ) DATA LINE
STABLE, DATA
CHANGE
DATA

e P c t ( VALID ALLOWED D99AU1031

e t u
Figure 23. Timing Diagram on the I2CBUS
l d
s o r o
O b e P SCL

I2CBUS

l e t SDA

s o
b
D99AU1032
START STOP

O Figure 24. Acknowledge on the I2CBUS

SCL 1 2 3 7 8 9

SDA
MSB
ACKNOWLEDGMENT
START D99AU1033 FROM RECEIVER

14/20
 TDA7563

SOFTWARE SPECIFICATIONS
All the functions of the TDA7563 are activated by I2C interface.
The bit 0 of the "ADDRESS BYTE" defines if the next bytes are write instruction (from P to TDA7563) or read
instruction (from TDA7563 to P).
Chip Address:

D7 D0

1 1 0 1 1 0 0 X D8 Hex

X = 0 Write to device
X = 1 Read from device
If R/W = 0, the P sends 2 "Instruction Bytes": IB1 and IB2.
( s )
IB1
c t
D7 X
d u
D6 Diagnostic enable (D6 = 1)
r o s )
Diagnostic defeat (D6 = 0)

e P c t (
D5 Offset Detection enable (D5 = 1)
Offset Detection defeat (D5 = 0)
l e t d u
D4 Front Channel
s o r o
Gain = 30dB (D4 = 0)
Gain = 16dB (D4 = 1)

O b e P
D3 Rear Channel
- l e t
Gain = 30dB (D3 = 0)

( s
Gain = 16dB (D3 = 1)) o
D2
c t b
Mute front channels (D2 = 0)s
u O
Unmute front channels (D2 = 1)

d -
D1
r o )
Mute rear channels (D1 = 0)

s
Unmute rear channels (D1 = 1)

D0
e P c
CD 2% (D0 = 0)t (
l e t d u
CD 10% (D0 = 1)

s o r o
O b
IB2

e P
D7

l
D6e t X

used for testing

s o D5 used for testing

O b D4 Stand-by on - Amplifier not working - (D4 = 0)Stand-by off - Amplifier working - (D4 = 1)

D3 Power amplifier mode diagnostic (D3 = 0)Line driver mode diagnostic (D3 = 1)

D2 X

D1 Right ChannelPower amplifier working in standard mode (D1 = 0)Power amplifier working in high
efficiency mode (D1 = 1)

D0 Left ChannelPower amplifier working in standard mode (D0 = 0)Power amplifier working in high efficiency
mode (D0 = 1)

15/20
 TDA7563

If R/W = 1, the TDA7563 sends 4 "Diagnostics Bytes" to P: DB1, DB2, DB3 and DB4.
DB1
D7 Thermal warning active (D7 = 1)

D6 Diag. cycle not activated or not terminated (D6 = 0)

Diag. cycle terminated (D6 = 1)

D5 X

D4 Channel LF
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)

D3 Channel LF
Normal load (D3 = 0)
( s )
Short load (D3 = 1)

c t
D2 Channel LF
Turn-on diag.: No open load (D2 = 0)
d u
Open load detection (D2 = 1)
Offset diag.: No output offset (D2 = 0)
r o s )
P
Output offset detection (D2 = 1)

e c t (
D1 Channel LF
No short to Vcc (D1 = 0)
l e t d u
Short to Vcc (D1 = 1)
s o r o
D0
b P
Channel LFNo short to GND (D1 = 0)Short to GND (D1 = 1)

O e
- l e t
DB2

( s ) o
D7 t b s
Offset detection not activated (D7 = 0)
c
Offset detection activated (D7 = 1)

D6 X
d u - O
r o s )
D5 X

e P c t (
t
D4 Channel LR

l e d u
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)

s o D3
r o
Channel LR

O b e P
Normal load (D3 = 0)
Short load (D3 = 1)

l
D2
e tChannel LR

s o Turn-on diag.: No open load (D2 = 0)

Open load detection (D2 = 1)

O b Permanent diag.: No output offset (D2 = 0)

Output offset detection (D2 = 1)

D1 Channel LRNo short to Vcc (D1 = 0)

Short to Vcc (D1 = 1)

D0 Channel LRNo short to GND (D1 = 0)

Short to GND (D1 = 1)

16/20
 TDA7563

B3
D7 Stand-by status (= IB1 - D4)

D6 Diagnostic status (= IB1 - D6)

D5 X

D4 Channel RF
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)

D3 Channel RF
Normal load (D3 = 0)
Short load (D3 = 1)

D2 Channel RF
( s )
Turn-on diag.: No open load (D2 = 0)
Open load detection (D2 = 1)
c t
Permanent diag.: No output offset (D2 = 0)
d u
r o
Output offset detection (D2 = 1)

s )
D1 Channel RF
No short to Vcc (D1 = 0)
e P c t (
Short to Vcc (D1 = 1)

l e t d u
D0 Channel RF
No short to GND (D1 = 0)
s o r o
Short to GND (D1 = 1)

O b e P
- l e t
DB4

( s ) o
D7 X

c t b s
D6 X

d u - O
D5 X

r o s )
D4
P
Channel RR

c t (
Turn-on diagnostic (D4 = 0)
e
l e t d u
Permanent diagnostic (D4 = 1)

s o D3
o
Channel R

r
RNormal load (D3 = 0)

O b P
Short load (D3 = 1)

e
D2

l e tChannel RR
Turn-on diag.: No open load (D2 = 0)

o
Open load detection (D2 = 1)

b s Permanent diag.: No output offset (D2 = 0)

Output offset detection (D2 = 1)

O D1 Channel RR
No short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)

D0 Channel RR
No short to GND (D1 = 0)
Short to GND (D1 = 1)

17/20
 TDA7563

Examples of bytes sequence

1 - Turn-On diagnostic - Write operation
Start Address byte with D0 = 0 ACK IB1 with D6 = 1 ACK IB2 ACK STOP

2 - Turn-On diagnostic - Read operation

Start Address byte with D0 = 1 ACK DB1 ACK DB2 ACK DB3 ACK DB4 ACK STOP

The delay from 1 to 2 can be selected by software, starting from T.B.D. ms

3a - Turn-On of the power amplifier with 30dB gain, mute on, diagnostic defeat, CD = 2%.

( s )
Start Address byte with D0 = 0 ACK

c tIB1 ACK IB2 ACK STOP

d u X0000000 XXX1XX11

3b - Turn-Off of the power amplifier

r o s )
Start Address byte with D0 = 0
e P
ACK
c t (
IB1 ACK IB2 ACK STOP

l e t d u X0XXXXXX XXX0XXXX

s o r o
4 - Offset detection procedure enable
O b e P
Start
-
Address byte with D0 = 0
l e t ACK IB1 ACK IB2 ACK STOP

( s ) o XX1XX11X XXX1XXXX

c t b s
d u O
5 - Offset detection procedure stop and reading operation (the results are valid only for the offset detection bits
-
r o
(D2 of the bytes DB1, DB2, DB3, DB4).

s )
Start

e P c t (
Address byte with D0 = 1 ACK DB1 ACK DB2 ACK DB3 ACK DB4 ACK STOP

l e t
The purpose of this test is to check if a D.C. offset (2V typ.) is present on the outputs, produced by input

d u
capacitor with anomalous leackage current or humidity between pins.

s o r o
The delay from 4 to 5 can be selected by software, starting from T.B.D. ms

O b e P
l e t
s o
O b

18/20
 TDA7563

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.45 4.50 4.65 0.175 0.177 0.183 OUTLINE AND
B 1.80 1.90 2.00 0.070 0.074 0.079 MECHANICAL DATA
C 1.40 0.055
D 0.75 0.90 1.05 0.029 0.035 0.041
E 0.37 0.39 0.42 0.014 0.015 0.016
F (1) 0.57 0.022
G 0.80 1.00 1.20 0.031 0.040 0.047
G1 25.75 26.00 26.25 1.014 1.023 1.033
H (2) 28.90 29.23 29.30 1.139 1.150 1.153
H1 17.00 0.669
H2 12.80 0.503
H3 0.80 0.031
L (2) 22.07 22.47 22.87 0.869 0.884 0.904
L1
L2 (2)
18.57
15.50
18.97
15.70
19.37
15.90
0.731
0.610
0.747
0.618
0.762
0.626
( s )
L3
L4
7.70 7.85
5
7.95 0.303 0.309
0.197
0.313

c t
L5
M 3.70
3.5
4.00 4.30 0.145
0.138
0.157
d u
0.169
M1 3.60 4.00 4.40 0.142 0.157
r o0.173

s )
P (
N 2.20 0.086
O
R
2
1.70
t
0.079

e
0.067
c t
R1
R2
0.5
0.3
l e
0.02
0.12
d u
R3
R4
1.25
0.50
s o 0.049
0.019
r o
V
V1
O b
5 (Typ.)
3 (Typ.)
e P
Flexiwatt27 (vertical)
V2
-
20 (Typ.)

l e t
V3

s ) 45 (Typ.)
(1): dam-bar protusion not included

( o
t
(2): molding protusion included

c b s
d
V u - O
r o s ) C

e PB

c t (
l e t d u H
V

s o r o V3
H3
H1
H2 A

b P
O

R3

O t e R4

e
L4

o l R2
V1

s N
L2

O b R
L L1
V1
L3

V2

R2 D
R1

L5 R1 R1
Pin 1
E
G G1 F
FLEX27ME
M M1

7139011

19/20
 TDA7563

( s )
c t
d u
r o s )
e P c t (
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

O b
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

2003 STMicroelectronics - All Rights Reserved
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20/20