IDTCV125

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

PROGRAMMABLE FLEXPC IDTCV125

CLOCK FOR P4 PROCESSOR

FEATURES: DESCRIPTION:
Power management control suitable for notebook applications IDTCV125 is a 56 pin clock device, incorporating both Intel CK410M and
One high precision PLL for CPU, SSC and N programming CKSSCD requirements, for Intel advance P4 processors. The CPU output
One high precision PLL for SRC/PCI, supports 100MHz output buffer is designed to support up to 400MHz processor. This chip has four PLLs
frequency, SSC and N programming inside for CPU, SRC/PCI, LVDS, and 48MHz/DOT96 IO clocks. This device
One high precision PLL for LVDS. Supports 100/96MHz output also implements Band-gap referenced IREF to reduce the impact of VDD variation
frequency, SSC programming on differential outputs, which can provide more robust system performance.
One high precision PLL for 96MHz/48MHz Static PLL frequency divide error can be as low as 36 ppm, worse case 114
Band-gap circuit for differential outputs ppm, providing high accuracy output clock. Each CPU/SRC/LVDS has its own
Support spread spectrum modulation, 0.5 down spread and Spread Spectrum selection.
others
Support SMBus block read/write, index read/write
Selectable output strength for REF OUTPUTS:
Allows for CPU frequency to change to a slower frequency to 2*0.7V current mode differential CPU CLK pair
conserve power when an application is less execution- 6*0.7V current mode differential SRC CLK pair
intensive One CPU_ITP/SRC selectable CLK pair
Smooth transition for N programming 6*PCI, 2 free running, 33.3MHz
Available in TSSOP package 1*96MHz, 1*48MHz
1*REF
KEY SPECIFICATION: One 100/96 MHz differential LVDS
CPU/SRC CLK cycle to cycle jitter < 85ps
PCI CLK cycle to cycle jitter < 250ps
Static PLL frequency divide error < 114 ppm
Static PLL frequency divide error for 48MHz < 5 ppm

FUNCTIONAL BLOCK DIAGRAM

PLL1
CPU CLK CPU[1:0]
SSC
Output Buffer
N Programmable
Stop Logic

X1 XTAL CPU_ITP/SRC7
IREF
Osc Amp
X2 REF

LVDS CLK ITP_EN

PLL2 Output Buffer
SSC Stop Logic
SDATA LVDS
SM Bus
Controller
SCLK IREF

PLL3
SSC SRC CLK
N Programmable Output Buffer
SRC[6:1]
Stop Logic
VTT_PWRGD#/PD
SEL PCI[3:0], PCIF[1:0]
SEL100/96# 100/96MHz
IREF
FSA.B.C
Control
PCI_STOP# Logic
48MHz
CPU_STOP# 48MHz/96MHz
PLL4
Output BUffer
DOT96

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE DECEMBER 2004

1
2004 Integrated Device Technology, Inc. DSC 6552/14
 IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1)

Symbol Description Min Max Unit
VDD_PCI 1 56 PCI0
VDDA 3.3V Core Supply Voltage 4.6 V
VSS_PCI 2 55 PCI_STOP# VDDIN 3.3V Logic Input Supply Voltage GND - 0.5 4.6 V
PCI1 3 54 CPU_STOP#
TSTG Storage Temperature 65 +150 C
PCI2 4 53 FSC/TEST_SEL
TAMBIENT Ambient Operating Temperature 0 +70 C
PCI3 5 52 REF
TCASE Case Temperature +115 C
VSS_PCI 6 51 VSS_REF
ESD Prot Input ESD Protection 2000 V
VDD_PCI 7 50 XTAL_IN
Human Body Model
PCIF0/ITP_EN 8 49 XTAL_OUT
(1) NOTE:
PCIF1/SEL100/96# 9 48 VDD_REF 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
VTT_PWRGD#/PD 10 47 SDA permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
VDD48 11 46 SCL
sections of this specification is not implied. Exposure to absolute maximum rating
USB48/FSA 12 45 VSS_CPU conditions for extended periods may affect reliability.
VSS48 13 44 CPU0
DOT96 14 43 CPU0#
DOT96# 15 42 VDD_CPU
FSB/TEST_MODE 16 41 CPU1
(2)
LVDS 17 40 CPU1#
(2)
LVDS# 18 39 IREF
SRC1 19 38 VSSA
SRC1# 20 37 VDDA
VDD_SRC 21 36 CPU2_ITP/SRC7
SRC2 22 35 CPU2_ITP#/SRC7#
SRC2# 23 34 VDD_SRC
SRC3 24 33 SRC6
SRC3# 25 32 SRC6#
SRC4 26 31 SRC5
SRC4# 27 30 SRC5#
VDD_SRC 28 29 VSS_SRC

NOTES:
1. 130K internal pull-up resistor.
2. Can be configured as 100MHz or 96MHz output clock, depending on pin9 power on
pull-up (100MHz) or pull-down (96MHz) latch. If using internal pull-up resistor, power
on would be 100MHz.
TSSOP
TOP VIEW

FREQUENCY SELECTION TABLE

FSC, B, A CPU SRC[7:0] PCI USB DOT REF
101 100 100 33.3 48 96 14.318
001 133 100 33.3 48 96 14.318
011 166 100 33.3 48 96 14.318
010 200 100 33.3 48 96 14.318
000 266 100 33.3 48 96 14.318
100 333 100 33.3 48 96 14.318
110 400 100 33.3 48 96 14.318
111 Reserve 100 33.3 48 96 14.318

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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION
Pin Number Name Type Description
1 VDD_PCI PWR 3.3V
2 VSS_PCI GND GND
3 PCI1 OUT PCI clock
4 PCI2 OUT PCI clock
5 PCI3 OUT PCI clock
6 VSS_PCI GND GND
7 VDD_PCI PWR 3.3V
8 PCIF0/ITP_EN I/O PCI clock, free running. CPU2 select (sampled on VTT_PWRGD# assertion) HIGH = CPU2.
9 PCIF1/SEL100/96# I/O PCI clock, free running. SEL100/96MHz (sampled on VTT_PWRGD# assertion) HIGH, LVDS = 100MHz.
10 VTT_PWRGD#/PD IN Level-sensitive strobe used to latch the FSA, FSB, FSC/TEST_SEL, and PCIF0/ITP_EN inputs. After
VTT_PWRGD# assertion, becomes a real-time input for asserting power down. (Active HIGH). Latch PCIF1/
SEL100/96# input.
11 VDD48 PWR 3.3V
12 USB48/FSA I/O 48MHz clock/FSA for CPU frequency selection
13 VSS48 GND GND
14 DOT96 OUT 96MHz 0.7 current mode differential clock output
15 DOT96# OUT 96MHz 0.7 current mode differential clock output
16 FSB/TEST_MODE IN CPU frequency selection. Selects REF/N or Hi-Z when in test mode, Hi-Z = 1, REF/N = 0.
17 LVDS OUT Differential serial reference clock
18 LVDS# OUT Differential serial reference clock
19 SRC1 OUT Differential serial reference clock
20 SRC1# OUT Differential serial reference clock
21 VDD_SRC PWR 3.3V
22 SRC2 OUT Differential serial reference clock
23 SRC2# OUT Differential serial reference clock
24 SRC3 OUT Differential serial reference clock
25 SRC3# OUT Differential serial reference clock
26 SRC4 OUT Differential serial reference clock
27 SRC4# OUT Differential serial reference clock
28 VDD_SRC PWR 3.3V
29 VSS_SRC GND GND
30 SRC5# OUT Differential serial reference clock
31 SRC5 OUT Differential serial reference clock
32 SRC6# OUT Differential serial reference clock
33 SRC6 OUT Differential serial reference clock
34 VDD_SRC PWR 3.3V
35 CPU2_ITP#/SRC7# OUT Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7#.
36 CPU2_ITP/SRC7 OUT Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7.
37 VDDA PWR 3.3V
38 VSSA GND GND
39 IREF OUT Reference current for differential output buffer
40 CPU1# OUT Host 0.7 current mode differential clock output
41 CPU1 OUT Host 0.7 current mode differential clock output
42 VDD_CPU PWR 3.3V

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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (CONT.)

Pin Number Name Type Description
43 CPU0# OUT Host 0.7 current mode differential clock output
44 CPU0 OUT Host 0.7 current mode differential clock output
45 VSS_CPU GND GND
46 SCL IN SM bus clock
47 SDA I/O SM bus data
48 VDD_REF PWR 3.3V
49 XTAL_OUT OUT XTAL output
50 XTAL_IN IN XTAL input
51 VSS_REF GND GND
52 REF OUT 14.318 MHz reference clock output
53 FSC/TEST_SEL IN CPU frequency selection. Selects test mode if pulled above 2V when VTT_PWRGD# is asserted LOW.
54 CPU_STOP# IN Stop all stoppable CPU CLK
55 PCI_STOP# IN Stop all stoppable PCI, SRC CLK
56 PCI0 OUT PCI clock

INDEX BLOCK WRITE PROTOCOL INDEX BLOCK READ PROTOCOL

Bit # of bits From Description Master can stop reading any time by issuing the stop bit without waiting
1 1 Master Start until Nth byte (byte count bit30-37).
2-9 8 Master D2h Bit # of bits From Description
10 1 Slave Ack (Acknowledge) 1 1 Master Start
11-18 8 Master Register offset byte (starting byte) 2-9 8 Master D2h
19 1 Slave Ack (Acknowledge) 10 1 Slave Ack (Acknowledge)
20-27 8 Master Byte count, N (0 is not valid) 11-18 8 Master Register offset byte (starting byte)
28 1 Slave Ack (Acknowledge) 19 1 Slave Ack (Acknowledge)
29-36 8 Master first data byte (Offset data byte) 20 1 Master Repeated Start
37 1 Slave Ack (Acknowledge) 21-28 8 Master D3h
38-45 8 Master 2nd data byte 29 1 Slave Ack (Acknowledge)
46 1 Slave Ack (Acknowledge) 30-37 8 Slave Byte count, N (block read back of N
: bytes), power on is 8
Master Nth data byte 38 1 Master Ack (Acknowledge)
Slave Acknowledge 39-46 8 Slave first data byte (Offset data byte)
Master Stop 47 1 Master Ack (Acknowledge)
48-55 8 Slave 2nd data byte
Ack (Acknowledge)
:
Master Ack (Acknowledge)
Slave Nth data byte
Not acknowledge
Master Stop

INDEX BYTE WRITE INDEX BYTE READ

Setting bit[11:18] = starting address, bit[20:27] = 01h. Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.

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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

SSC MAGNITUDE CONTROL FOR CPU, RESOLUTION

SRC, AND SMC CPU (MHz) Resolution N=
SMC[2:0] 100 0.666667 150
000 -0.25 133 0.666667 200
001 -0.5 166 1.333333 125
010 -0.75 200 1.333333 150
011 -1 266 1.333333 200
100 0.125 333 2.666667 125
101 0.25 400 2.666667 150
110 0.375
111 0.5

SEL 100/96# CONFIGURATION SPREAD SPECTRUM CONTROL

SEL 100/96# LVDS Frequency Unit
SELECTION (SSC) FOR LVDS
0 96 MHz S[3:0] Spread
1 100 MHz 0000 -0.8%
0001 -1%
0010 -1.25%
0011 -1.5%
0100 -1.75%
S.E. CLOCK STRENGTH SELECTION 0101 -2%
(PCI, REF, USB48) 0110 -0.3%
Str[1:0] Level 0111 -0.5%
00 1 1000 0.3%
01 0.8 1001 0.4%
10 0.6 1010 0.5%
11 1.2 1011 0.6%
1100 0.8%
1101 1%
1110 1.25%
1111 1.5%

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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

CONTROL REGISTERS

N PROGRAMMING PROCEDURE

Use Index byte write.

For N programming, the user only needs to access Byte 11, Byte 12, and Byte 9.

1. Write Byte 11 for CPU PLL N, CPU f = N* Resolution (see resolution table).
2. Write Byte 12 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3.
3. Enable N Programming bit, Byte 9 bit 1. Once this bit is enabled, any N value will be changed on the fly.

BYTE 0
Bit Output(s) Affected Description/Function 0 1 Type Power On
0 Reserved
1 SRC1, SRC1# Output Enable Tristate Enable RW 1
2 SRC2, SRC2# Output Enable Tristate Enable RW 1
3 SRC3, SRC3# Output Enable Tristate Enable RW 1
4 SRC4, SRC4# Output Enable Tristate Enable RW 1
5 SRC5, SRC5# Output Enable Tristate Enable RW 1
6 SRC6, SRC6# Output Enable Tristate Enable RW 1
7 CPU2, CPU2#/ Output Enable Tristate Enable RW 1
SRC7, SRC7#

BYTE 1
Bit Output(s) Affected Description/Function 0 1 Type Power On
0 CPU[2:0], SRC[7:1], Spread Spectrum mode enable Spread off Spread on RW 0
PCI[5:0], PCIF[1:0]
1 CPU0, CPU0# Output Enable Tristate Enable RW 1
2 CPU1, CPU1# Output Enable Tristate Enable RW 1
3 Reserved RW 0
4 REF Output Enable Tristate Enable RW 1
5 USB48 Output Enable Tristate Enable RW 1
6 DOT96 Output Enable Tristate Enable RW 1
7 PCIF0 Output Enable Tristate Enable RW 1

BYTE 2
Bit Output(s) Affected Description/Function 0 1 Type Power On
0 PCIF1 Output Enable Tristate Enable RW 1
1 Reserved RW 1
2 PCI0 Output Enable Tristate Enable RW 1
3 PCI1 Output Enable Tristate Enable RW 1
4 PCI2 Output Enable Tristate Enable RW 1
5 PCI3 Output Enable Tristate Enable RW 1
6 Reserved RW 1
7 Reserved RW 1

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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

BYTE 3
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 Reserved RW 0
1 SRC1 RW 0
2 SRC2 RW 0
3 SRC3 Allow controlled by Free running, not Stopped with RW 0
4 SRC4 PCI_STOP# assertion affected by PCI_STOP# PCI_STOP# RW 0
5 SRC5 RW 0
6 SRC6 RW 0
7 SRC7 RW 0

BYTE 4
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 CPU0, CPU0# Allow control of CPU0 Not stopped Stopped with RW 1
with assertion of CPU_STOP# by CPU_STOP# CPU_STOP#
1 CPU1, CPU1# Allow control of CPU1 Not stopped Stopped with RW 1
with assertion of CPU_STOP# by CPU_STOP# CPU_STOP#
2 CPU2, CPU2# Allow control of CPU2 Not stopped Stopped with RW 1
with assertion of CPU_STOP# by CPU_STOP# CPU_STOP#
3 PCIF0 Allow controlled by Not stopped Stopped with RW 0
4 PCIF1 PCI_STOP# assertion by PCI_STOP# PCI_STOP# RW 0
5 Reserved RW 0
6 DOT96 DOT96 power down drive mode Driven in power down Tristate RW 0
7 Reserved RW 0

BYTE 5
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 CPU0, CPU0# CPU0 PD drive mode Driven in power down Tristate in power down RW 0
1 CPU1, CPU1# CPU1 PD drive mode Driven in power down Tristate in power down RW 0
2 CPU2, CPU2# CPU2 PD drive mode Driven in power down Tristate in power down RW 0
3 SRC[7:1], SRC[7:1]# SRC PD drive mode Driven in power down Tristate in power down RW 0
4 CPU0, CPU0# CPU0 CPU_STOP drive mode Driven in CPU_STOP# Tristate when stopped RW 0
5 CPU1, CPU1# CPU1 CPU_STOP drive mode Driven in CPU_STOP# Tristate when stopped RW 0
6 CPU2, CPU2# CPU2 CPU_STOP drive mode Driven in CPU_STOP# Tristate when stopped RW 0
7 SRC[7:1], SRC[7:1]# SRC PCI_STOP drive mode Driven in PCI_STOP Tristate when stopped RW 0

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 IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

BYTE 6
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 CPU[2:0] FSA latched value on power up R
1 CPU[2:0] FSB latched value on power up R
2 CPU[2:0] FSC latched value on power up R
3 PCI, SRC Software PCI_STOP control for Stop all PCI, PCIF, and Software STOP RW 1
PCI and SRC CLK SRC which can be stopped Disabled
by PCI_STOP#
4 REF REF drive strength 1x drive 2x drive RW 1
5 Reserved RW 0
6 Test clock mode entry control Normal operation Test mode, controlled RW 0
by Byte 6, Bit 7
7 CPU, SRC, PCI Only valid when Byte 6, Bit 6 Hi-Z REF/N RW 0
PCIF, REF, is HIGH
USB48, DOT96

BYTE 7
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 Vendor ID R 1
1 Vendor ID R 0
2 Vendor ID R 1
3 Vendor ID R 0
4 Revision ID R 0
5 Revision ID R 0
6 Revision ID R 0
7 Revision ID R 0

BYTE 8, LVDS CONTROL BYTE

Bit Output(s) Affected Description/Function 0 1 Type Power On
0 LVDS HW/ SMBus control HW(1) SW RW 0
1 LVDS SSC EN Spread spectrum enable Off On RW 1
2 LVDS Enable Output Enable Disable Enable RW 1
3 SEL 100/96# Select LVDS frequency 96MHz 100MHZ RW SEL 100/96#
4 S3 see SSC table RW 0
5 S2 see SSC table RW 0
6 S1 see SSC table RW 0
7 S0 see SSC table RW 0
NOTE:
1. If bit 0 is set to 0, LVDS output frequency is selected by HW SEL 100/96#. If bit 0 is set to 1, LVDS output frequency is selected by bit 3.

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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

BYTE 9
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 One cycle read disable enable RW 0
1 N Programming enable Disable enable RW 0
2 LVDS PLL power down normal Power down RW 0
3 RW 0
4 USB PLL power down normal Power down RW 0
5 SRC PLL power down normal Power down RW 0
6 CPU PLL power down normal Power down RW 0
7 SRC, PLL2, SSC enable Only valid when Byte1 bit0 is 1 disable enable RW 1

BYTE 10
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 SRC SMC0 SRC/PCI SSC control RW 1
1 SRC SMC1 see SMC table RW 0
2 SRC SMC2 RW 0
3 Reserved RW 0
4 CPU SMC0 CPU PLL SSC control RW 1
5 CPU SMC1 see SMC table RW 0
6 CPU SMC2 RW 0
7 Reserved RW 0

BYTE 11
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 CPU_N0, LSB CPU CLK = N* Resolution RW 0
1 CPU_N1 see Resolution table RW 1
2 CPU_N2 RW 1
3 CPU_N3 RW 0
4 CPU_N4 RW 1
5 CPU_N5 RW 0
6 CPU_N6 RW 0
7 CPU_N7, MSB RW 1

BYTE 12
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 SRC_N0, LSB RW 0
1 SRC_N1 RW 1
2 SRC_N2 SRC f = N*SRC Resolution RW 1
3 SRC_N3 Resolution = 0.666667 RW 0
4 SRC_N4 100MHz N= 150 RW 1
5 SRC_N5 RW 0
6 SRC_N6 RW 0
7 SRC_N7, MSB RW 1

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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

BYTE 13
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 48MHzStr0 RW 0
1 48MHStr1 USB48MHz0 strength selection RW 0
2 REFStr0 RW 0
3 REFStr1 REF strength selection RW 0
4 PCIStrC0 RW 0
5 PCIStrC1 PCI strength selection RW 0
6 PCIFStr0 RW 0
7 PCIFStr1 PCIF strength selection RW 0

ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT

PARAMETERS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIH Input HIGH Voltage 3.3V 5% 2 VDD + 0.3 V
VIL Input LOW Voltage 3.3V 5% VSS - 0.3 0.8 V
VIH_FS LOW Voltage, HIGH Threshold For FSA.B.C test_mode 0.7 VDD + 0.3 V
VIL_FS LOW Voltage, LOW Threshold For FSA.B.C test_mode VSS - 0.3 0.35 V
IIH Input HIGH Current VIN = VDD 5 5 A
IIL1 Input LOW Current VIN = 0V, inputs with no pull-up resistors 5 A
IIL2 Input LOW Current VIN = 0V, inputs with pull-up resistors 200 A
IDD3.3OP Operating Supply Current Full active, CL = full load 400 mA
IDD3.3PD Powerdown Current All differential pairs driven 70 mA
All differential pairs tri-stated 12
FI Input Frequency(1) VDD = 3.3V 14.31818 MHz
LPIN Pin Inductance(2) 7 nH
CIN Logic inputs 5
COUT Input Capacitance(2) Output pin capacitance 6 pF
CINX XTAL_IN 5
COUTX XTAL_OUT 12
TSTAB Clock Stabilization(2,3) From VDD power-up or de-assertion of PD to first clock 1.8 ms
Modulation Frequency(2) Triangular modulation 30 33 KHz
TDRIVE_SRC(2) SRC output enable after PCI_STOP# de-assertion 15 ns
TDRIVE_PD(2) CPU output enable after PD de-assertion 300 us
TFALL_PD(2) Fall time of PD 5 ns
TRISE_PD(3) Rise time of PD 5 ns
TDRIVE_CPU_STOP#(2) CPU output enable after CPU_STOP# de-assertion 10 us
TFALL_CPU_STOP#(2) Fall time of CPU_STOP# 5 ns
TRISE_CPU_STOP#(3) Rise time of CPU_STOP# 5 ns
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.

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 IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE

DIFFERENTIAL PAIR(1)
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 2pF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
ZO Current Source Output Impedance(2) VO = VX 3000
VOH3 Output HIGH Voltage IOH = -1mA 2.4 V
VOL3 Output LOW Voltage IOL = 1mA 0.4 V
VHIGH Voltage HIGH(2) Statistical measurement on single-ended signal using 660 1150 mV
VLOW Voltage LOW(2) oscilloscope math function 300 150
VOVS Max Voltage(2) Measurement on single-ended signal using absolute value 1150 mV
VUDS Min Voltage(2) 300
VCROSS(ABS) Crossing Voltage (abs)(2) 250 550 mV
d - VCROSS Crossing Voltage (var)(2) Variation of crossing over all edges 140 mV
ppm Long Accuracy(2,3) See TPERIOD Min. - Max. values 300 300 ppm
400MHz nominal / -0.5% spread 2.4993 2.5133
333.33MHz nominal / -0.5% spread 2.9991 3.016
266.66MHz nominal / -0.5% spread 3.7489 3.77
TPERIOD Average Period(3) 200MHz nominal / -0.5% spread 4.9985 5.0266 ns
166.66MHz nominal / -0.5% spread 5.9982 6.032
133.33MHz nominal / -0.5% spread 7.4978 7.54
100MHz nominal / -0.5% spread 9.997 10.0533
96MHz nominal 10.4135 10.4198
400MHz nominal / -0.5% spread 2.4143
333.33MHz nominal / -0.5% spread 2.9141
266.66MHz nominal / -0.5% spread 3.6639
200MHz nominal / -0.5% spread 4.9135
TABSMIN Absolute Min Period(2,3) 166.66MHz nominal / -0.5% spread 5.9132 ns
133.33MHz nominal / -0.5% spread 7.4128
100MHz nominal / -0.5% spread 9.912
96MHz nominal 10.1635
tR Rise Time(2) VOL = 0.175V, VOH = 0.525V 175 700 ps
tF Fall Time(2) VOL = 0.175V, VOH = 0.525V 175 700 ps
d-tR Rise Time Variation(2) 125 ps
d-tF Fall Time Variation(2) 125 ps
dT3 Duty Cycle(2) Measurement from differential waveform 45 55 %
NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.
3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.

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 IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE

DIFFERENTIAL PAIR, CONTINUED(1)
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 2pF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

Skew, CPU[1:0](2) 100
tSK3 Skew, CPU2(2) VT = 50% 250 ps
Skew, SRC(2) 250
Jitter, Cycle to Cycle, CPU[1:0](2) 85
tJCYC-CYC Jitter, Cycle to Cycle, CPU2(2) Measurement from differential waveform 100 ps
Jitter, Cycle to Cycle, SRC(2) 125
Jitter, Cycle to Cycle, DOT96(2) 250

NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.

ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F

Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 30pF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
ppm Static Error(1,2) See Tperiod Min. - Max. values 0 ppm
TPERIOD Clock Period(2) 33.33MHz output nominal 29.991 30.009 ns
33.33MHz output spread 29.991 30.1598
VOH Output HIGH Voltage IOH = -1mA 2.4 V
VOL Output LOW Voltage IOL = 1mA 0.55 V
IOH Output HIGH Current VOH at Min. = 1V -33 mA
VOH at Max. = 3.135V -33
IOL Output LOW Current VOL at Min. = 1.95V 30 mA
VOL at Max. = 0.4V 38
Edge Rate(1) Rising edge rate 1 4 V/ns
Edge Rate(1) Falling edge rate 1 4 V/ns
tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.3 1.2 ns
tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.3 1.2 ns
dT1 Duty Cycle(1) VT = 1.5V 45 55 %
tSK1 Skew(1) VT = 1.5V 500 ps
tJCYC-CYC Jitter, Cycle to Cycle(1) VT = 1.5V 500 ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.

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 IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

ELECTRICAL CHARACTERISTICS, 48MHZ, USB

Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 20pF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
ppm Static Error(1,2) See Tperiod Min. - Max. values 0 ppm
TPERIOD Clock Period(2) 48MHz output nominal 20.8257 20.834 ns
VOH Output HIGH Voltage IOH = -1mA 2.4 V
VOL Output LOW Voltage IOL = 1mA 0.55 V
IOH Output HIGH Current VOH at Min. = 1V -29 mA
VOH at Max. = 3.135V -23
IOL Output LOW Current VOL at Min. = 1.95V 29 mA
VOL at Max. = 0.4V 27
Edge Rate(1) Rising edge rate 1 2 V/ns
Edge Rate(1) Falling edge rate 1 2 V/ns
tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.5 1.2 ns
tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.5 1.2 ns
dT1 Duty Cycle(1) VT = 1.5V 45 55 %
tJCYC-CYC Jitter, Cycle to Cycle 350 ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.

ELECTRICAL CHARACTERISTICS - REF-14.318MHZ

Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 20pF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
ppm Long Accuracy(1) See Tperiod Min. - Max. values 0 ppm
TPERIOD Clock Period 14.318MHz output nominal 69.827 69.855 ns
VOH Output HIGH Voltage(1) IOH = -1mA 2.4 V
VOL Output LOW Voltage(1) IOL = 1mA 0.4 V
IOH Output HIGH Current VOH at Min. = 1V -33 mA
VOH at Max. = 3.135V -33
IOL Output LOW Current VOL at Min. = 1.95V 30 mA
VOL at Max. = 0.4V 38
Edge Rate(1) Rising edge rate 1 4 V/ns
Edge Rate(1) Falling edge rate 1 4 V/ns
tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.3 1.2 ns
tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.3 1.2 ns
dT1 Duty Cycle(1) VT = 1.5V 45 55 %
tJCYC-CYC Jitter, Cycle to Cycle(1) VT = 1.5V 1000 ps
NOTE:
1. This parameter is guaranteed by design, but not 100% production tested.

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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

PCI STOP FUNCTIONALITY

The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF[1:0] and SRC clocks can be set to be free-running through SMBus
programming, they will ignore both the PCI_STOP# pin and the PCI_STOP register bit.

PCI_STOP# CPU CPU# SRC SRC# PCIF/PCI USB DOT96 DOT96# REF
1 Normal Normal Normal Normal 33MHz 48MHz Normal Normal 14.318MHz
0 Normal Normal IREF * 6 or float Low Low 48MHz Normal Normal 14.318MHz

PCI_STOP# ASSERTION (TRANSITION FROM 1 TO 0)

The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all PCI[6:0] and stoppable PCIF[1:0]
clocks will latch low on their next high to low transition. After the PCI clocks are latched low, the SRC clock, (if set to stoppable) will latch high at IREF * 6 (or
tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and the SRC# will latch low as shown below.

tSU

PCI_STOP#

PCIF[1:0] 33MHz

PCI[3:0] 33MHz

SRC 100MHz

SRC# 100MHz

PCI_STOP# - DE-ASSERTION
The de-assertion of the PCI_STOP# signal is to be sampled on the rising edge of the PCIF free running clock domain. After detecting PCI_STOP# de-assertion,
all PCI[6:0], stoppable PCIF[1:0] and stoppable SRC clocks will resume in a glitch free manner.

tSU
tDRIVE_SRC

PCI_STOP#

PCIF[1:0] 33MHz

PCI[3:0] 33MHz

SRC 100MHz

SRC# 100MHz

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 IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

CPU STOP FUNCTIONALITY

The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously.

CPU_STOP# CPU CPU# SRC SRC# PCIF/PCI USB DOT96 DOT96# REF
1 Normal Normal Normal Normal 33MHz 48MHz Normal Normal 14.318MHz
0 IREF * 6 or float Low Normal Normal 33MHz 48MHz Normal Normal 14.318MHz

CPU_STOP# ASSERTION (TRANSITION FROM 1 TO 0)

Asserting CPU_STOP# pin stops all CPU outputs that are set to be stoppable after their next transition. When the SMBus CPU_STOP tri-state bit corresponding
to the CPU output of interest is programmed to a 0, CPU output will stop CPU_True = High and CPU_Complement = Low. When the SMBus CPU_STOP#
tri-state bit corresponding to the CPU output of interest is programmed to a 1, CPU outputs will be tri-stated.

CPU_STOP#

CPU

CPU#

CPU_STOP# - DE-ASSERTION (TRANSITION FROM 0 TO 1)

With the de-assertion of CPU_STOP# all stopped CPU outputs will resume without a glitch. The maximum latency from the de-assertion to active outputs
is two to six CPU clock periods. If the control register tristate bit corresponding to the output of interest is programmed to 1, then the stopped CPU outputs will
be driven High within 10nS of CPU_STOP# de-assertion to a voltage greater than 200mV.

CPU_STOP#

CPU

CPU#

CPU Internal

tDRIVE_CPU_Stop
10nS > 200mV

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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

PD, POWER DOWN

PD is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. When PD is asserted high all clocks will be driven low before
turning off the VCO. In PD de-assertion all clocks will start without glitches.

PD CPU CPU# SRC SRC# PCIF/PCI USB DOT96 DOT96# REF

0 Normal Normal Normal Normal 33MHz 48MHz Normal Normal 14.318MHz
1 IREF * 2 or float Float IREF * 2 or float Float Low Low IREF * 2 or float Float Low

PD ASSERTION

PD

CPU 133MHz

CPU# 133MHz

SRC 100MHz

SRC# 100MHz

USB 48MHz

PCI 33MHz

REF 14.31818

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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

PD DE-ASSERTION

tSTABLE <1.8mS

PD

CPU 133MHz

CPU# 133MHz

SRC 100MHz

SRC# 100MHz

USB 48MHz

PCI 33MHz

REF 14.31818

tDRIVE_PWRDWN
<300S, <200mV

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 IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

DIFFERENTIAL CLOCK TRISTATE

To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or tristated during PD and CPU_STOP#
mode and the SRC clock is configurable to be driven or tristated during PCI_STOP# and PD mode. Each differential clock (SRC, CPU[2:0]) output can be
disabled by setting the corresponding outputs register OE bit to 0 (disable). Disabled outputs are to be tristated regardless of CPU_STOP, SRC_STOP
and PD register bit settings.

Signal Pin PD Pin CPU_STOP# CPU_STOPTristate Bit PD Tristate Bit Non-Stoppable Outputs Stoppable Outputs
CPU 0 1 X X Running Running
CPU 0 0 0 X Running Driven at IREF x 6
CPU 0 0 1 X Running Tristate
CPU 1 X X 0 Driven at IREF x 2 Driven at IREF x 2
CPU 1 X X 1 Tristate Tristate
NOTES:
1. Each output has four corresponding control register bits; OE, PD, CPU_STOP, and Free Running.
2. IREF x 6 and IREF x 2 is the output current in the corresponding mode.
3. See CONTROL REGISTERS section for bit address.

Signal Pin PD Pin PCI_STOP# PCI_STOPTristate Bit PD Tristate Bit Non-Stoppable Outputs Stoppable Outputs
SRC 0 1 X X Running Running
SRC 0 0 0 X Running Driven at IREF x 6
SRC 0 0 1 X Running Tristate
SRC 1 X X 0 Driven at IREF x 2 Driven at IREF x 2
SRC 1 X X 1 Tristate Tristate
NOTES:
1. SRC output has four corresponding control register bits; OE, PD, SRC_STOP, and Free Running.
2. IREF x 6 and IREF x 2 is the output current in the corresponding mode.
3. See CONTROL REGISTERS section for bit address.

TRISTATE DOT96 CLOCK CONTROL

Signal Pin PD PD Tristate Bit Output
DOT96 1 X Running
DOT96 0 0 Driven at IREF x 2
DOT96 0 1 Tristate
NOTES:
1. DOT output has two corresponding control register bits; OE and PD.
2. IREF x 6 and IREF x 2 is the output current in the corresponding mode.
3. See CONTROL REGISTERS section for bit address.

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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

LVDS AC TIMING REQUIREMENTS

Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0C to +70C
Symbol Parameter Min. Typ. Max. Unit
tR1 Clock Rise Time(1,2,3) 175 700 ps
tF1 Clock Fall Time(1,2,3) 175 700 ps
tR Clock Rise Time Variation(2,3,4) 125 ps
tF Clock Fall Time Variation(2,3,4) 125 ps
Rise/Fall Matching(2,3,5) 20 %
VHIGH Voltage HIGH(2,3,6) 660 700 850 mV
VLOW Voltage LOW (2,3,7) -150 0 mV
VCROSS(ABS) Crossing Voltage (abs)(2,3,8,9,10) 250 550 mV
VCROSS(REL) Crossing Voltage (rel)(2,3,10,11) Calc. Calc.
TOTAL VCROSS Total Variation of VCROSS Over All Edges(2,3,12) 140 mV
tJCYC-CYC Cycle-to-Cycle Jitter(2,13) 350 ps
dT3 Duty Cycle(2,13) 45 55 %
VOVS Maximum Voltage Allowed at Output (overshoot)(2,3,14) VHIGH + 0.3V V
VUDS Minimum Voltage Allowed at Output (undershoot)(2,3,15) -0.3 V
VRB Ringback Margin(2,3) n/a 0.2 V
NOTES:
1. Measured from VOL = 1.75V to VOH =0.525V. Only valid for Rising LVDS and Falling LVDS#. Signal must be monotonic through the VOL to VOH region for tRISE and tFALL.
2. Test configuration is Rs = 32.2, Rp = 49.9, 2pF.
3. Measurement taken from single-ended waveform.
4. Measured with oscilloscope, averaging off, using Min. Max. statistics. Variation is the delta between Min. and Max.
5. Measured with oscilloscope, averaging off, the difference between the tRISE (average) of LVDS versus the tFALL (average) of LVDS#.
6. VHIGH is defined as the statistical average HIGH value as obtained by using the oscilloscope VHIGH math function.
7. VLOW is defined as the statistical average LOW value as obtained by using the oscilloscope VLOW math function.
8. Measured at crossing point where the instantaneous voltage value of the rising edge of LVDS equals the falling edge of LVDS#.
9. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
10. The crossing point must meet the absolute and relative crossing point specifications simultaniously.
11. VCROSS (rel) Min. and Max. are derived using the following: VCROSS (rel) Min. = 0.25V + 0.5 (VHAVG - 0.7V), VCROSS (rel) Max. = 0.55V + 0.5 (0.7V - VHAVG).
12. VCROSS is defined as the total variation of all crossing voltages of Rising LVDS and Falling LVDS#. This is the maximum allowed variance in VCROSS for any particular system.
13. Measurement is taken from differential waveform.
14. Overshoot is defined as the absolute value of the maximum voltage.
15. Undershoot is defined as the absolute value of the minimum voltage.

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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

LVDS AVERAGE PERIOD, TPERIOD(1,2,3,4)

Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0C to +70C
96MHz 100MHz
Spread Min. Max. Min. Max. Unit
0% (no spread) 10.406 10.427 9.99 10.01 ns
0.8% down-spread 10.406 10.511 9.99 10.09 ns
1% down-spread 10.406 10.531 9.99 10.11 ns
1.25% down-spread 10.406 10.557 9.99 10.135 ns
1.5% down-spread 10.406 10.583 9.99 10.16 ns
1.75% down-spread 10.406 10.61 9.99 10.185 ns
2% down-spread 10.406 10.636 9.99 10.21 ns
2.5% down-spread 10.406 10.688 9.99 10.26 ns
3% down-spread 10.406 10.74 9.99 10.31 ns
0.3% down-spread 10.375 10.458 9.96 10.04 ns
0.4% down-spread 10.365 10.469 9.95 10.05 ns
0.5% down-spread 10.354 10.479 9.94 10.06 ns
0.6% down-spread 10.344 10.49 9.93 10.07 ns
0.8% down-spread 10.323 10.511 9.91 10.09 ns
1% down-spread 10.302 10.531 9.89 10.11 ns
1.25% down-spread 10.276 10.557 9.865 10.135 ns
1.5% down-spread 10.25 10.583 9.84 10.16 ns
NOTES:
1. Test configuration is Rs = 32.2, Rp = 49.9, 2pF.
2. The average period over any 1S period of tiime must be greater than the minimum and less than the maximum specified period.
3. Measurement is taken from differential waveform.
4. Calculated using a 0.1% accuracy in spread modulation. Assumes 300ppm long term accuracy on CLKIN.

tRISE (LVDS)

VOH = 0.525V

LVDS# LVDS

VCROSS

VOL = 0.175V

tFALL (LVDS#)

Single-Ended Measurement Point for tRISE and tFALL

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 IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

MISCELLANEOUS AC TIMING REQUIREMENTS

Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0C to +70C
Symbol Parameter Min. Typ. Max. Unit
tPZL Output Enable Delay (All Outputs) (1)
0 10 s
tPZH
tPLZ Output Disable Delay (All Outputs)(1) 0 10 s
tPHZ
tSTABLE All Clock Stabilization from Power-Up(2) 3 ms
tSPREAD Setting Period for Spread Selection Change (2,3)
3 ms

NOTES:
1. These specifications apply to the LVDS and SMBus pins. These pins must be tri-stated when PWRDWN is asserted. LVDS is driven differential when PWRDWN is de-asserted unless
it is disabled.
2. The time specified is from when VDD achieves its nominal operating level (typical condition VDD = 3.3V) and PWRDWN is de-asserted until the frequency output is stable and operating
within specification.
3. The time specified is measured from the spread selection change or output frequency change until the LVDS clock is operating at the new spread modulation and frequency.
If there is another change in spread selection or output frequency during the tSPREAD settling period, then the settling period start resets to the most recent change in spread selection
and output frequency.

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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

PWRDWN (POWER DOWN) CLARIFICATION

PWRDWN

CLOCK VCO On Off

LVDS

tPHZ
LVDS#

PWRDWN Assertion

VDD

PWRDWN

CLOCK VCO Off Starting Stable

tSTABLE

LVDS

tPZH
LVDS#

PWRDWN De-Assertion

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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

LVDS SYSTEM IMPLEMENTATION

Clock Rs Rp Unit
LVDS Clock 33.2 49.9
5% 1%

33
5% Clock

CV125 LVDS
TLA

33
5% Clock#
LVDS#
TLB

475 49.9 49.9

1% 1% 1%
2pF 2pF
5% 5%

Test Load Board Configuration

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IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION
IDTCV XXX XX X
Device Type Package Grade

Blank Commercial Temperature Range

(0C to +70C)

PA Thin Small Shrink Outline Package

PAG TSSOP - Green

125 Programmable FlexPC Clock for P4 Processor

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 [email protected]
Santa Clara, CA 95054 fax: 408-492-8674 (408) 654-6459
www.idt.com

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