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Experiment 2: Inputs Output

The document describes an experiment to model a multiplexer (MUX) and demultiplexer (DEMUX) using gate-level modeling in NCSIM software. It provides the theory of operation for each, including their truth tables and logic diagrams. The result section shows the Verilog code used to model a 4-input MUX and 4-output DEMUX, along with test benches. Waveforms confirming the correct functionality of each design are also presented.

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35 views

Experiment 2: Inputs Output

The document describes an experiment to model a multiplexer (MUX) and demultiplexer (DEMUX) using gate-level modeling in NCSIM software. It provides the theory of operation for each, including their truth tables and logic diagrams. The result section shows the Verilog code used to model a 4-input MUX and 4-output DEMUX, along with test benches. Waveforms confirming the correct functionality of each design are also presented.

Uploaded by

Sdo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Experiment 2

AIM: To write the expression for Multiplexer (MUX) & De-multiplexer (DEMUX) in gate level modeling
with NCSIM software.

APPARATUS: NCSIM (candence) software.

THEORY:

MULTIPLEXER (MUX)

In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital input signals
and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which
are used to select which input line to send to the output.

Truth table

INPUTS OUTPUT
S0 S1 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

LOGIC DIAGRAM
DEMULTIPLEXER (DEMUX)

A demultiplexer (or demux) is a device that takes a single input line and routes it to one of
several digital output lines. Ademultiplexer of 2n outputs has n select lines, which are used to
select which output line to send the input. A demultiplexer is also called a data distributor.

Truth table

ENABLE INPUTS OUTPUT


E S0 S1 I0 I1 I2 I3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

LOGIC DIAGRAM
RESULT:

Program file: (MULTIPLEXER [MUX] )

module mux4(a,b,c,d,s0,s1,y);

input a,b,c,d,s0,s1;

output y;

wire w1,w2,w3,w4,w5,w6;

not x1(w1,s0);

not x2(w2,s1);

and x3(w3,w1,w2,a);

and x4(w4,w1,s1,b);

and x5(w5,s0,w2,c);

and x6(w6,s0,s1,d);

or x7(y,w3,w4,w5,w6);

endmodule

Test Bench file:

module muxtest();

reg a,b,c,d,s0,s1;

wire y;

mux4 test1(a,b,c,d,s0,s1,y);

initial

begin

s0=s1=0; a=0; b=c=d=1;

#2 s0=s1=0; a=1; b=c=d=0;

#2 s0=0; s1=1; b=0; a=c=d=1;


#2 s0=0; s1=1; b=1; a=c=d=0;

#2 s0=1; s1=0; c=0; a=b=d=1;

#2 s0=1; s1=0; c=1; a=b=d=0;

#2 s0=s1=1; d=0; a=c=d=1;

#2 s0=s1=1; d=1; a=c=d=0;

#2 $stop;

end

endmodule

Program file: (DEMULTIPLEXER [DEMUX] )

module demux4(a,b,c,d,s0,s1,e);

input e,s0,s1;

output a,b,c,d;

wire w1,w2;

not x1(w1,s0);

not x2(w2,s1);

and x3(a,w1,w2,e);

and x3(b,w1,s1,e);

and x4(c,s0,w2,e);

and x5(d,s0,s1,e);

endmodule

Test Bench file:

module demuxtest();

reg e,s0,s1;

wire a,b,c,d;

demuxtest test1(a,b,c,d,s0,s1,e);
initial

begin

e=1; s0=s1=0;

#2 e=1; s0=0; s1=1;

#2 e=1; s0=1; s1=0;

#2 e=1; s0=s1=1;

#2 $stop

end

endmodule

Waveform:

FOR MULTIPLEXER (MUX)


Learning Outcomes
I have learnt how to design multiplexer and demultiplexer using cadence NCSim software.I have seen
the output wave form in the simulation mode. I have drawn the truth table and attached the picture of
the logic diagram.

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