Scribd
Upload
67 views

Data Processing Instructions

This document contains a lecture summary on data processing and control flow instructions for the EC271 Microprocessors course taught by Arulalan Rajan at NITK Surathkal. It discusses arithmetic instructions like ADD, SUB, logical instructions like AND, ORR, register movement instructions like MOV, MVN, and compare instructions like CMP and CMN. The lecture focuses on explaining the purpose and operation of various ARM assembly instructions.

Uploaded by

vinodh krishh
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
67 views

Data Processing Instructions

This document contains a lecture summary on data processing and control flow instructions for the EC271 Microprocessors course taught by Arulalan Rajan at NITK Surathkal. It discusses arithmetic instructions like ADD, SUB, logical instructions like AND, ORR, register movement instructions like MOV, MVN, and compare instructions like CMP and CMN. The lecture focuses on explaining the purpose and operation of various ARM assembly instructions.

Uploaded by

vinodh krishh
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 56

EC271 Microprocessors

Arulalan Rajan
Dept. of E&C Engg, NITK Surathkal

Lecture - 16, 1st February 2017

Data Processing & Control Flow Instructions


Arithmetic Instructions

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Arithmetic Instructions
ADD r0, r1, r2

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Arithmetic Instructions
ADD r0, r1, r2 5KTT9GMPQYKV2NGCUG

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Arithmetic Instructions
ADD r0, r1, r2 5KTT9GMPQYKV2NGCUG

ADC r0, r1, r2

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Arithmetic Instructions
ADD r0, r1, r2 5KTT9GMPQYKV2NGCUG

ADC r0, r1, r2 r0:= r1 + r2 + C

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Arithmetic Instructions
ADD r0, r1, r2 5KTT9GMPQYKV2NGCUG

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Arithmetic Instructions
ADD r0, r1, r2 5KTT9GMPQYKV2NGCUG

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Arithmetic Instructions
ADD r0, r1, r2 5KTT9GMPQYKV2NGCUG

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

SBC r0, r1, r2

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Arithmetic Instructions
ADD r0, r1, r2 5KTT9GMPQYKV2NGCUG

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

SBC r0, r1, r2 r0:= r1 - r2 + C - 1

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Arithmetic Instructions
ADD r0, r1, r2 5KTT9GMPQYKV2NGCUG

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

SBC r0, r1, r2 r0:= r1 - r2 + C - 1

RSB r0, r1, r2

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Arithmetic Instructions
ADD r0, r1, r2 5KTT9GMPQYKV2NGCUG

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

SBC r0, r1, r2 r0:= r1 - r2 + C - 1

RSB r0, r1, r2 r0:= r2 - r1

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Arithmetic Instructions
ADD r0, r1, r2 5KTT9GMPQYKV2NGCUG

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

SBC r0, r1, r2 r0:= r1 - r2 + C - 1

RSB r0, r1, r2 r0:= r2 - r1

RSC r0, r1, r2

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Arithmetic Instructions
ADD r0, r1, r2 5KTT9GMPQYKV2NGCUG

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

SBC r0, r1, r2 r0:= r1 - r2 + C - 1

RSB r0, r1, r2 r0:= r2 - r1

RSC r0, r1, r2 r0:= r2 - r1 + C - 1

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Arithmetic Instructions
ADD r0, r1, r2 5KTT9GMPQYKV2NGCUG

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

SBC r0, r1, r2 r0:= r1 - r2 + C - 1

RSB r0, r1, r2 r0:= r2 - r1

RSC r0, r1, r2 r0:= r2 - r1 + C - 1

C : Current value of Carry bit in CPSR


#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Logical Operations

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Logical Operations
AND r0, r1, r2
ORR r0, r1, r2

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Logical Operations
AND r0, r1, r2
ORR r0, r1, r2 9J[5KTT9J[!

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Logical Operations
AND r0, r1, r2
ORR r0, r1, r2 9J[5KTT9J[!

EOR r0, r1, r2

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Logical Operations
AND r0, r1, r2
ORR r0, r1, r2 9J[5KTT9J[!

EOR r0, r1, r2 r0:= r1 xor r2

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Logical Operations
AND r0, r1, r2
ORR r0, r1, r2 9J[5KTT9J[!

EOR r0, r1, r2 r0:= r1 xor r2

BIC r0, r1, r2

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Logical Operations
AND r0, r1, r2
ORR r0, r1, r2 9J[5KTT9J[!

EOR r0, r1, r2 r0:= r1 xor r2

BIC r0, r1, r2 r0:= r1 and NOT r2

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Logical Operations
AND r0, r1, r2
ORR r0, r1, r2 9J[5KTT9J[!

EOR r0, r1, r2 r0:= r1 xor r2

BIC r0, r1, r2 r0:= r1 and NOT r2

BIC: Bit Clear

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Logical Operations
AND r0, r1, r2
ORR r0, r1, r2 9J[5KTT9J[!

EOR r0, r1, r2 r0:= r1 xor r2

BIC r0, r1, r2 r0:= r1 and NOT r2


Every 1 in R2 clears corresponding
BIC: Bit Clear
bit in R1

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Logical Operations
AND r0, r1, r2
ORR r0, r1, r2 9J[5KTT9J[!

EOR r0, r1, r2 r0:= r1 xor r2

BIC r0, r1, r2 r0:= r1 and NOT r2


Every 1 in R2 clears corresponding
BIC: Bit Clear
bit in R1

#0&$+%CTGGSWKXCNGPVKPUVTWEVKQPU

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Register Movement

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Register Movement

MOV r0, r1 r0:= r1

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Register Movement

MOV r0, r1 r0:= r1

MVN r0, r1 r0:=Not(r1)

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Register Movement

MOV r0, r1 r0:= r1

MVN r0, r1 r0:=Not(r1)

/18/80CTGGSWKXCNGPVKPUVTWEVKQPU

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Register Movement

MOV r0, r1 r0:= r1

MVN r0, r1 r0:=Not(r1)

/18/80CTGGSWKXCNGPVKPUVTWEVKQPU
--diag_warning 1645 assembler command-line option to check when
an instruction substitution occurs
#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Compare Instructions

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Compare Instructions

CMP r0, Operand 2 r1 - Operand2

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Compare Instructions

CMP r0, Operand 2 r1 - Operand2


CMN r0, Operand 2 r0 + Operand2

4GUWNVUCTGFKUECTFGF
4GIKUVGTUCTGPQVWRFCVGF
(NCIUWRFCVGF
0<%8
%/2%/0CTGGSWKXCNGPV

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Bit Test Instructions

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Bit Test Instructions
Bitwise AND on Rn and
TST{cond} Rn, Operand 2 Operand 2
(same as ANDS)

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Bit Test Instructions
Bitwise AND on Rn and
TST{cond} Rn, Operand 2 Operand 2
(same as ANDS)
Bitwise EXOR on Rn and
TEQ{cond} Rn, Operand 2 Operand 2
(same as EORS)

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Bit Test Instructions
Bitwise AND on Rn and
TST{cond} Rn, Operand 2 Operand 2
(same as ANDS)
Bitwise EXOR on Rn and
TEQ{cond} Rn, Operand 2 Operand 2
(same as EORS)

4GUWNVUCTGFKUECTFGF

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Bit Test Instructions
Bitwise AND on Rn and
TST{cond} Rn, Operand 2 Operand 2
(same as ANDS)
Bitwise EXOR on Rn and
TEQ{cond} Rn, Operand 2 Operand 2
(same as EORS)

4GUWNVUCTGFKUECTFGF
4GIKUVGTUCTGPQVWRFCVGF

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Bit Test Instructions
Bitwise AND on Rn and
TST{cond} Rn, Operand 2 Operand 2
(same as ANDS)
Bitwise EXOR on Rn and
TEQ{cond} Rn, Operand 2 Operand 2
(same as EORS)

4GUWNVUCTGFKUECTFGF
4GIKUVGTUCTGPQVWRFCVGF
(NCIUWRFCVGF
0<

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Bit Test Instructions
Bitwise AND on Rn and
TST{cond} Rn, Operand 2 Operand 2
(same as ANDS)
Bitwise EXOR on Rn and
TEQ{cond} Rn, Operand 2 Operand 2
(same as EORS)

4GUWNVUCTGFKUECTFGF
4GIKUVGTUCTGPQVWRFCVGF
(NCIUWRFCVGF
0<
%HNCIOC[DGWRFCVGFFWTKPIECNEWNCVKQPQHQRGTCPF

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Bit Test Instructions
Bitwise AND on Rn and
TST{cond} Rn, Operand 2 Operand 2
(same as ANDS)
Bitwise EXOR on Rn and
TEQ{cond} Rn, Operand 2 Operand 2
(same as EORS)

4GUWNVUCTGFKUECTFGF
4GIKUVGTUCTGPQVWRFCVGF
(NCIUWRFCVGF
0<
%HNCIOC[DGWRFCVGFFWTKPIECNEWNCVKQPQHQRGTCPF
6'30GHHGEVQP%8

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Bit Test Instructions
Bitwise AND on Rn and
TST{cond} Rn, Operand 2 Operand 2
(same as ANDS)
Bitwise EXOR on Rn and
TEQ{cond} Rn, Operand 2 Operand 2
(same as EORS)

4GUWNVUCTGFKUECTFGF
4GIKUVGTUCTGPQVWRFCVGF
(NCIUWRFCVGF
0<
%HNCIOC[DGWRFCVGFFWTKPIECNEWNCVKQPQHQRGTCPF
6'30GHHGEVQP%8
6JGPYJCVKUVJGWUGQH6'3!!
#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Control Flow Instructions

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Control Flow Instructions
Do not process data

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Control Flow Instructions
Do not process data

Nor moves the data around

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Control Flow Instructions
Do not process data

Nor moves the data around

Processor executes instructions sequentially

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Control Flow Instructions
Do not process data

Nor moves the data around

Processor executes instructions sequentially

Determines which instructions get executed next

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Control Flow Instructions
Do not process data

Nor moves the data around

Processor executes instructions sequentially

Determines which instructions get executed next

Recall: All ARM instructions can be conditionally


executed

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Control Flow Instructions

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Control Flow Instructions

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Control Flow Instructions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Control Flow Instructions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Condition 1 0 1 L 24 bit singed word Offset

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Control Flow Instructions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Condition 1 0 1 L 24 bit singed word Offset

0 = Branch

1 = Branch
with Link

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Control Flow Instructions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Condition 1 0 1 L 24 bit singed word Offset

0 = Branch

1 = Branch
with Link

Uses Link Register, whenever a subroutine is executed and


getting back to original sequence of code is required

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Control Flow Instructions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Condition 1 0 1 L 24 bit singed word Offset

0 = Branch

1 = Branch
with Link

Uses Link Register, whenever a subroutine is executed and


getting back to original sequence of code is required

B{L}{<cond>} <target_address>

#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
Control Flow Instructions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Condition 1 0 1 L 24 bit singed word Offset

0 = Branch

1 = Branch
with Link

Uses Link Register, whenever a subroutine is executed and


getting back to original sequence of code is required

B{L}{<cond>} <target_address>
Range of branch Instructions: +/- 32MBytes
#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN

You might also like