17. 12.

2014

Modern instrumentation and control

nowadays systems
Typical nowadays system:
Low cost instruments (system): microcontroller with fix firmware and fix hardware no flexibility
Reconfigurable measurement systems Quality instruments: more-less PC with signal inputs and output (signal front end: analog preprocessing

based on real time and FPGA circuit AD and DA convertors, digital/timing IO = fixed hardware)
Flexibility only in software: General purpose OS (e.g., W7) + flexible application software (measurement functions)
Large, high energy consumption, limited flexibility given by software and fixed hardware, problematic in real time
signal processing, exact and fast timing (multitask in windows), and similar applications
Jn aliga Easy maintained (software development and installation), multitask, data presentation and archiving.
Technical university of Koice, Slovakia Typical convenient applications:
Single purpose instrumentation (oscilloscope, basic spectrum analyzers, logic and network analyzers, etc.)
(based on different sources mainly from National Instruments) Typical inconvenient applications:
Distributed systems (sensor network), control systems of machines, robust and reliable systems
continuously working for a long time, fast signal processing in real time, reconfigurable measurement
system (reconfigurable signal and pattern generation, signal analyzers, etc. that cannot be processed by
software in real time)

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What is a Real-Time System? Real-Time Terms

Determinism Describes how consistently the

Real Time Response - The ability to reliably and, system responds to external events or performs
without fail, respond to an event or perform an
operations within a given time limit.
operation within a guaranteed time period.
Time Critical Code - Code that must execute on
Loop Cycle Time - Execution time of one cycle a specific schedule to function as desired
of a loop.

Jitter - Variation from the desired loop cycle Priority - Defines when a VI or loop should
time. execute relative to other VIs and loops

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Real time operational systems General Purpose Operating Systems

In general, real time systems are based on real time OS Multitasking = Processor time is shared between
(RTOS) programs
What is RTOS? Can preempt high priority programs
Any OS is responsible for managing the hardware resources
of a computer and hosting applications that run on the Many programs run in the backgroundscreen
computer savers, disk utilities, antivirus software, etc.
RTOS is specially designed to run applications with very Must service interruptskeyboard, mouse,
precise timing and a high degree of reliability Ethernet, etc.
To be considered "real-time", an operating system must have
a known maximum time for each of the critical operations
High amount of jitter
that it performs Cannot guarantee determinism
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Real-Time Operating Systems RTOS vs. general purpose OS (GPOS)

GPOS such a Windows is excellent platform for developing and running your
non-critical measurement and control applications but not the ideal
Multitasking - Ensure that high-priority tasks platform for running applications that require precise timing or extended
execute first up-time.
Priorities:
Generally do not require user input from GPOS is fair all running tasks (threads) will achieve a processor time
RTOS behavior is given by programmer decision on tasks priorities (static, dynamic)
peripherals and on environment requirements
Interrupts latency - measured as the amount of time between when a device
generates an interrupt and when that device is serviced:
LabVIEW Real-Time Module executes VIs on the following real-time operating systems: GPOS: variable amount of time
NI ETS (Embedded Tool Suite) RTOS must guarantee that all interrupts will be serviced within a certain maximum
Wind River VxWorks amount of time (interrupt latency must be bounded)
Linux Performance actual performance is given mostly by hardware
GPOS virtually decreased by multitasking
RTOS - can provide much more precise and predictable timing characteristics
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Hard and Soft RTOS RT system components

Components of RT system:
RTOS that can absolutely guarantee a maximum time for
operations are commonly referred to as hard real-time
RTOS that can only guarantee a maximum most of the time are
referred to as soft real-time When I need RT system?
If I need a precise timing:
Perform tasks within a guaranteed worst-case timeframe
Carefully prioritize different sections of my program
Run loops with nearly the same timing each iteration (typically within
microseconds)
Detect if a loop missed its timing goal
If I need a high reliability:
System should run reliably for days, months, or years without stopping
(watchdog system may be useful)

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Real-Time System Components:

LabVIEW Real-Time System
Real-Time Targets
NI RT PXI Embedded Controllers
Host Computer High speed, high channel density, I/O variety
RT Target
NI CompactRIO
Reconfigurable Embedded System

NI Compact Vision System & NI Smart

Camera Machine vision
NI Industrial Controller
Rugged, fanless, high-performance

NI Single-Board RIO
Develop Execute NI myRIO
Reconfigurable single circuit board form factor
Deploy Education
Desktop PC running RTOS
Determinism for PCI systems
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Host and Target Application

Host Application
Architecture

Runs on the host computer

Host Application Target Application working independently
Handles non-deterministic tasks Host Application
Communicates with the target application
User Network Non-deterministic Inter-task Deterministic
Interface
Communication
Loop Communication
Loop user interface parameters and data retrieval
Data logging User
Data analysis Interface

Data Storage Data Storage Data broadcast to other systems

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Target Application

Processes that requires determinism are time-critical processes

set all other processes to a lower priority
Use multithreading to set the priority of a process
FPGA in instrumentation
Higher priority processes preempt lower priority processes
Target Application

Inter-task
Non-deterministic Communication Deterministic
Loop Loop

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FPGA Top 5 Benefits of Using FPGAs

Field-programmable gate arrays (FPGAs) are FPGA chip adoption across all industries is driven by the fact that FPGAs
combine the best parts of application-specific integrated circuits (ASICs)
reprogrammable silicon chips. and processor-based systems.
In contrast to processors that you find in your PC, These benefits include the following:
Faster I/O response times and specialized functionality
programming an FPGA rewires the chip itself to Exceeding the computing power of digital signal processors
implement your functionality rather than run a Rapid prototyping and verification without the fabrication process of
software application. custom ASIC design
Implementing custom functionality with the reliability of dedicated
Ross Freeman, the cofounder of Xilinx, deterministic hardware
invented the first FPGA in 1985. Field-upgradable eliminating the expense of custom ASIC re-design and
maintenance

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FPGA Technology Configurable logic blocks (CLBs)

Basic blocks
Programmable flip-flops
Interconnects
lookup tables (LUTs)
The basic block can be combine in different FPGA into
more complex blocks:
Logic Digital signal processors (DSP) slices
Blocks Embedded block of RAM
Multipliers
Etc.

I/O Blocks
Note: Most applications do not require
detailed knowledge of these components
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FPGA Component Overview

Look Up Table (LUT) Inputs
0000
And2
0
(Xilinx Virtex 5)
0001 0
0010 0
0011 1
Inputs And3
0100 X
0000 0
A 0101 X
0001 0 CLB
Basic FPGA Building Block
0110 X
B 4 Input And2
0010
0111
0
X Memory Controller
LUT 0011
Inputs
1000
0
And4
X I/O
Common uses A
0100
0000
1001
0101
0001
0
0
X
0
0 CMT
1010 X MGT
Logic functions
0110 0
B 4 Input And3
0010
1011
0111
0
X
1
C LUT
0011
1100 0
X BUFG
1000 X
Distributed memory
0100
1101 0
X
1001
0101 X
0 BUFIO PCIe Endpoint
A 1110 X
1010
0110 X
0
Shift registers B 4 Input And4
1111
0111
1011
X
0
X
Block RAM
C LUT 1000
1100 0
X Microprocessor
D 1001
1101 0
X
1010
1110 0
X
1011 0
DSP48
1111 X
1100 0
1101 0
1110 0
1111 1

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FPGA Logic implementation True Parallelism with FPGA

E
F Implemented Logic on FPGA:
Implementing Logic on FPGA: F = {(A+B)CD} E
E
F F = {(A+B)CD} E
LabVIEW FPGA Code Z=(W X)Y

A A
B B
C C
D D
Z

W X Y
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Benefits and drawback of FPGA FPGA applications in instrumentation

Benefits:
Reprogrammable silicon also has the same flexibility of software running on a Fast real time signal processing:
processor-based system, but it is not limited by the number of processing cores
available. Fast digitizers with onboard signal processing, e.g. Agilent
Unlike processors, FPGAs are truly parallel in nature, so different processing Reconfigurable signal analyzers with demodulation and analysis in real
operations do not have to compete for the same resources. time (e.g., wireless networks with different standards)
Each independent processing task is assigned to a dedicated section of the chip, and
can function autonomously without any influence from other logic blocks. Robust components of sensor network, smart sensors
As a result, the performance of one part of the application is not affected when you Reliable data acquisition and control systems for industry
add more processing. technologies, robots, , including marine technology, space and
FPGA based applications have high execution speed, reliability, and flexibility aeronautic systems, etc.
Adding a new task does not affect the other tasks
Low costs in comparison with other HW realization (ASIC)
Reconfigurable tester for product inspection and new products
Drawback:
development,
Missing OS for easy adding tasks, connecting disk, drivers for IO, etc.
Difficult design of FPGA internal structure
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FPGA structure design Function Nodes Case Study

Traditional tools:
Hardware description languages
(HDLs) such as VHDL and Verilog Many functions correspond directly to VHDL primitives
Text oriented describing internal FPGA compiler implements logic on hardware
structure a mapping chip IO to
internal signals
To verify the design a test bench
needs to be developed simulating
input signal and acquiring outputs
Verified design is compiled into bit
form describing internal structure of
FPGA
Intellectual Properties (IP) are key
building blocks of Xilinx Targeted
Design Platforms
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VHDL to Circuit Circuit to FPGA Hardware

Function Nodes Case Study Function Nodes Case Study

Xilinx Xilinx Compiler

map and
Compiler
place & route
synthesis

Schematic

Schematic Hardware

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FPGA Hardware to Bitfile High-Level Synthesis Design Tools

Function Nodes Case Study

Simplification of design no HDL is needed

Xilinx
Verification in user friendly environment known from software
Compiler
development and debugging.
Create bitfile
Example for projects: LabVIEW FPGA

Schematic

Bitfile
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Abstraction to the Pin

LabVIEW, LabVIEW Real Time,

LabVIEW FPGA

LabVIEW FPGA
VHDL
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Graphical System Design System Design to Deployment

A Platform-Based Approach Models of Computation
Dataflow C / HDL Code Textual Math Simulation Statechart
Test Monitor Embedded Control Cyber Physical

LabVIEW LabVIEW LabVIEW LabVIEW

``

Desktop Real-Time FPGA MPU/MCU

Desktops and PXI and Modular RIO and Custom Open Connectivity
Personal Computers PXI Systems CompactRIO Single-Board RIO Custom Design
PC-Based DAQ Instruments Designs with 3rd Party I/O

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Integrating Elements

LabVIEW Real time notes

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Preparation A. Front Panel Communication

Host Computer
Real time application is always developed on PC
Displays front panel of
Real time hardware (target) must be first detected and configured by MAX RT Target VI
Project in LabVIEW must be created
Real time target must be added into the project User Interface
Under the target a new VI running in the real Communication
time environment must be created only for
developement
RT Target
Executes the block
diagram logic of
RT Target VI

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Network Communication Comparison

B. Network Communication
Common Deterministic Deterministic
Protocol Speed Advantages Caveats
Use Read/Write Data Transfer
Host Computer
Network- Latest value,
Executes Host VI which Published With RT FIFO Ease of LabVIEW
host Fast No
communicates with the Shared enabled programming only
Variable interface
RT Target VI
Network Data Built-in LabVIEW
Faster No No
Network Communication Streams streaming functions only
after deploying = High transfer
independent RT application Data rates, String
TCP Fastest No No
streaming standard data
RT Target protocol
Executes RT Target VI High transfer
String
which communicates with UDP
Broadcast
Fastest No No
rates,
data,
the Host VI latest values standard
Lossy
protocol
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Avoid Modifying Front Panel Objects

Deploying Real-Time Application and Using OS specific Technologies

Creating a stand-alone application (executable) Front panel Property Nodes and control references
of a LabVIEW Real-Time Module application using the LabVIEW Dialog functions
Application Builder VI Server front panel functions
Benefits of deploying your RT Application: Do Not Use OS-Specific Technologies
Embed executable in non-volatile memory on the target Examples:
Launch executable automatically when target boots ActiveX VIs Call Library Nodes that access an operating
.NET VIs system API other than ETS or VxWorks
Review the code for unsupported functions Windows Registry Access VIs Graphics and Sound VIs
Functions that modify front panel objects TestStand VIs (ActiveX-based) Database Connectivity Toolset
Report Generation Toolkit VIs XML DOM Parser and
Functions that use technologies specific to other operating systems G Web Server for CGI Support
Cursor VIs

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Evaluating System Requirements

Need FPGA? FPGA?

LabVIEW FPGA Select RIO Architecture FPGA for

Windows
FPGA for
Real-Time

Select a Platform PCI/PCIe PXI/PXIe CompactRIO PXI/PXIe PCI/PCIe

FPGA I/O Connectors

Other Considerations Size

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FPGA Windows Example: FlexRIO

Windows Computer (PC or PXI)
PXI/PXIe/PCIe FPGA module + adapter
Reconfigurable FPGA
Adapter: additional electronics protecting FPGA inputs and
creating additional measurement functions, e.g.: RF transceiver,
fast digitizer (oscilloscope), fast DIO,

Host VI Communication FPGA VI

LabVIEW for LabVIEW

Windows FPGA

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FPGA Real-Time Example: cRIO, sbRIOmyRIO

Windows LabVIEW Real-Time System
System (cRIO, sbRIO, R Series in RT PXI, cRIO: Chassis with FPGA + RT processor modul or embedded + slots
etc) for DAQ moduls
FPGA sbRIO: single board cRIO with integrated DAQ moduls
myRIO: educational module similar to sbRIO
Network
Windows VI Host VI Communication FPGA VI
Communication
FPGA VI
controls
FIFO

LabVIEW for LabVIEW LabVIEW
Windows Real-Time FPGA

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LabVIEW Programming & CompactRIO

or myRIO FPGA Development Flow

Evaluate Select Configure Create a

System LabVIEW
Requirements Architecture Hardware Project

Real-Time Reconfigurable
User Interface Processor FPGA

Create Simulate on Compile to Create Create

FPGA VI PC to test FPGA FPGA Host Real-Time
VI(s) Host VI(s)
LabVIEW LabVIEW FPGA
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Project with CompactRIO Controller IO access

IO are connected to processor across FPGA
IO access:
Windows LabVIEW RT System 1. The Scan Engine is a prewritten LabVIEW FPGA personality that
System automatically reads values NI CompactRIO
FPGA from I/O modules (myRIO LabVIEW Real-Time FPGA
up to 10kHz rate) no need
LabVIEW Real-Time NI Scan Engine
Windows Network Comm. FPGA to program FPGA.
Comm. Host VI I/O Variables
RIO Scan
VI VI 2. Own personality (VI I/O memory Interface
I/O Modules

table
configuring FPGA and
optionally including
digital signal preprocessing,
LabVIEW LabVIEW LabVIEW control, timing, fast complex
FPGA Host Interface LabVIEW FPGA
for Real-Time FPGA calculations, etc.). VI

Windows
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Data transfer FPGA RT application

www.ni.com/myrio
Direct writing/reading from virtual front panel of FPGA VI
Simple data transfer without memory myRIO
FIFO DMA transfer with buffered data transfer
Register
Handshake
Memory
FPGA I/O variable

See the demonstration later for more details

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What is myRIO What is inside?

Processor type ..........Xilinx Z-7010 (ARM Cortex-A9)
Processor speed........667 MHz
Processor cores .........2
Memory

National Instruments
Nonvolatile memory ...........256 MB
DDR3 memory......................512 MB
DDR3 clock frequency .........533 MHz
DDR3 data bus width............16 bits
myRIO-1900 is a portable FPGA .................Xilinx Z-7010 (28,000 programmable
logic cells)

reconfigurable I/O (RIO) Wireless Characteristics

Radio mode ..............IEEE 802.11 b,g,n
USB Ports:
device that students can host port + USB device port... USB 2.0 Hi-Speed
Analog Input

use to design control, Aggregate sample rate ........ 500 kS/s

Resolution................................. 12 bits
Overvoltage protection ............. 16 V
signal processing, Analog Output
Aggregate max. update rates .......345 kS/s

robotics, and Resolution ......................................12 bits

Overload protection ......................16 V
Digital I/O
mechatronics systems DIO 5V/3.3V........................3x8
2xUART............................. 230,400 bps
2xSPI ..................................4 MHz
2xPWM................................100 kHz
2xQuadr. encoder input .. 100 kHz Accelerometer
2xI2 C....................................400 kHz Number of axes......... 3
Range ........................ 8 g

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Xilinx Zynq 7000 family Analog inputs and ourputs

Z-7010 Z-7015 Z-7020 Z-7030 Z-7045 Z-7100
Processor
Dual ARM Cortex-A9 MPCore with CoreSight
Core

Processor
NEON & Single / Double Precision Floating Point for each processor
Extensions

32 KB Instruction, 32 KB Data per processor

L1 Cache

L2 Cache 512 KB
On-Chip
256 KB
Memory

Memory
DDR3, DDR3L, DDR2, LPDDR2, 2x Quad-SPI, NAND, NOR
Interfaces

Peripherals 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO

28K 85K
Logic Cells 74K 125K 350K 444K

BlockRAM 380 KB 560 KB 3,020 KB

240 KB 1,060 KB 2,180 KB
(Mb)

DSP Slices 80 160 220 400 900 2,020

up to
Transceiver up to 4 (12.5 up to 16 (12.5
4 (6.25 Gb/s) 16 (10.3125
Count Gb/s) Gb/s)
Gb/s)

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MXP connectors MSP connector

Identical Connectors

4 AI MXP A MXP B

6 DIO 2 AO 1 UART
1 SPI

1 Quad Encoder

1 I2C Identical to NI myDAQ

3 PW Ms

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NI myRIO Palette Links

www.ni.com/myrio
www.ni.com/labview
www.ni.com/crio
www.ni.com/flexrio
www.ni.com/...

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