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MCP6N16 Zero Drift Instrumentation Amp

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39 views58 pages

MCP6N16 Zero Drift Instrumentation Amp

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Juan Gil Roca

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MCP6N16

Zero-Drift Instrumentation Amplifier

Features: Description:
High DC Precision: Microchip Technology Inc. offers the single Zero-Drift
- VOS: 17 V (maximum, GMIN = 100) MCP6N16 instrumentation amplifier (INA) with Enable
- TC1: 60 nV/C (maximum, GMIN = 100) pin (EN) and three minimum gain options (GMIN). The
internal offset correction gives high DC precision: it has
- CMRR: 112 dB (minimum, GMIN = 100,
very low offset and offset drift, and negligible 1/f noise.
VDD = 5.5V)
- PSRR: 110 dB (minimum, GMIN = 100, Two external resistors set the gain, minimizing gain
VDD = 5.5V) error and drift over temperature. The reference voltage
(VREF) shifts the output voltage (VOUT).
- gE: 0.15% (maximum, GMIN = 10, 100)
Flexible: The MCP6N16 is designed for single-supply operation,
with rail-to-rail input (no common mode crossover
- Minimum Gain (GMIN) Options:
distortion) and output performance. The supply voltage
1, 10 and 100 V/V
range (1.8V to 5.5V) is low enough to support many
- Rail-to-Rail Input and Output portable applications. All devices are fully specified
- Gain Set by Two External Resistors from -40C to +125C. Each part has EMI filters at the
Bandwidth: 500 kHz (typical, Gain = GMIN = 1, 10) input pins, for good EMI rejection (EMIRR).
Power Supply: These parts have three minimum gain options (1, 10
- VDD: 1.8V to 5.5V and 100 V/V). This allows the user to optimize the input
- IQ: 1.1 mA (typical) offset voltage and input noise for different applications.
- Power Savings (Enable) Pin: EN
Enhanced EMI Protection:
Typical Application Circuit
- Electromagnetic Interference Rejection Ratio VDD RTD Temperature Sensor
(EMIRR): 111 dB at 2.4 GHz
Extended Temperature Range: -40C to +125C
2.49 k 10 F
Typical Applications:
EN
High-Side Current Sensor 4.99 k 4.99 k
Wheatstone Bridge Sensors MCP6N16-100
Difference Amplifier with Level Shifting VOUT
Power Control Loops 68.1 RTD 20 k
100
Design Aids: 4.99 k 100 100

SPICE Macro Model

Microchip Advanced Part Selector (MAPS)
Application Notes Package Types
MCP6N16 MCP6N16
MSOP 33 DFN *

EN 1 8 VDD EN 1 8 VDD
VIM 2 7 VOUT VIM 2 EP 7 VOUT
VIP 3 6 VFG VIP 3 9
6 VFG
VSS 4 5 VREF VSS 4 5 VREF
* Includes Exposed Thermal Pad (EP); see Table 3-1.

2014 Microchip Technology Inc. DS20005318A-page 1

MCP6N16
Minimum Gain Options
Table 1 shows key specifications that differentiate
between the different minimum gain (GMIN) options.
See Section 1.0 Electrical Characteristics,
Section 6.0 Packaging Information and Product
Identification System for further information on GMIN.

TABLE 1: KEY DIFFERENTIATING SPECIFICATIONS

TC1 CMRR Eni eni
GMIN VOS PSRR VDMH GBWP
(nV/C) (dB) (VP-P) (nV/Hz)
Part No. (V/V) (V) (dB) (V) (MHz)
Max. Min. Typ. Typ.
Nom. Max. Min. Min. Typ.
TA = -40 to +125C VDD = 5.5V f = 0.1 to 10 Hz f < 500 Hz
MCP6N16-001 1 85 1800 89 91 2.7 0.50 19 900
MCP6N16-010 10 22 180 103 104 0.27 5.0 2.2 105
MCP6N16-100 100 17 60 112 110 0.027 35 0.93 45
Note 1: GMIN is the minimum stable gain (GDM), for a given part option. In other words, GDM GMIN.
Figures 1 to 3 show input offset voltage versus
4
temperature for the three gain options (GMIN = 1, 10,
100 V/V). 3

e (V)
2

Voltage
40
1
30
V

0
Offset Voltage (V)

Input Offset

20
-1
O

10 GMIN = 100
-2 28 Samples
0 VDD = 5.5V
5 5V
-3 VCM = VDD/2
-10
0 NPBW = 3 mHz
Input O

-4
4
GMIN = 1
-20 -50 -25 0 25 50 75 100 125
28 Samples
VDD = 5.5V Ambient Temperature (C)
-30 VCM = VDD/2
NPBW = 3 mHz FIGURE 3: Input Offset Voltage vs.
-40
-50 -25 0 25 50 75 100 125 Temperature, with GMIN = 100.
Ambient Temperature (C)

FIGURE 1: Input Offset Voltage vs.

Temperature, with GMIN = 1.

3
e (V)

2
Voltage

1
V

0
Input Offset

-1
O

GMIN = 10
-2 28 Samples
VDD = 5.5V
5 5V
-3 VCM = VDD/2
NPBW = 3 mHz
-4
4
-50 -25 0 25 50 75 100 125
Ambient Temperature (C)

FIGURE 2: Input Offset Voltage vs.

Temperature, with GMIN = 10.

DS20005318A-page 2 2014 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS
2014 Microchip Technology Inc.

1.1 Absolute Maximum Ratings

VDD VSS ............................................................................................................................................................................................................................................ 6.5V
Current at Input Pins (Note 1) ........................................................................................................................................................................................................... 2 mA
Analog Inputs (VIP and VIM) (Note 1) .................................................................................................................................................................. VSS 1.0V to VDD + 1.0V
All Other Inputs and Outputs ............................................................................................................................................................................... VSS 0.3V to VDD + 0.3V
Difference Input Voltage ............................................................................................................................................................................................................. |VDD VSS|
Output Short-Circuit Current ...................................................................................................................................................................................................... Continuous
Current at Output and Supply Pins .................................................................................................................................................................................................. 30 mA
Storage Temperature ......................................................................................................................................................................................................... -65C to +150C
Maximum Junction Temperature ......................................................................................................................................................................................................+150C
ESD protection on all pins (HBM, MM)..................................................................................................................................................................................... 4 kV, 400V

Notice: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
Note 1: See Section 4.3.1.2 Input Voltage Limits and Section 4.3.1.3 Input Current Limits.

MCP6N16
DS20005318A-page 3
1.2 Specifications
DS20005318A-page 4

MCP6N16
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k
to VL, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).
Parameters Sym. Min. Typ. Max. Units GMIN Conditions
Input Offset
Input Offset Voltage VOS -85 +85 V 1 TA = +25C
-22 +22 10
-17 +17 100
Input Offset Voltage Drift TC1 -1800 +1800 nV/C 1 TA = -40C to +125C (Note 2)
Linear Temp. Co. -180 +180 10
-60 +60 100
Input Offset Voltage Drift TC2 560 pV/C2 1 TA = -40C to +125C
Quadratic Temp. Co. 63 10
69 100
Input Offset Aging VOS 1.0 V 1 408 hr Life Test at +150C,
0.8 10 measured at +25C
0.7 100
Power Supply Rejection Ratio PSRR 91 109 dB 1
104 122 10
110 128 100
Output Offset
Output Offset Voltage VOSO 0 V all
Input Current and Impedance (Note 3)
2014 Microchip Technology Inc.

Input Bias Current IB -100 2 +100 pA all

Across Temperature 20 TA = +85C
Across Temperature 0 250 2000 TA = +125C
Note 1: VCM = (VIP + VIM)/2, VDM = (VIP VIM) and GDM = 1 + RF/RG.
2: For Design Guidance only; not tested.
3: These specifications apply to the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (use VREF instead).
4: This specification applies to the VIP, VIM, VREF and VFG pins individually.
5: Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.
6: See Section 1.5 Explanation of DC Error Specifications.
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)
2014 Microchip Technology Inc.

Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k
to VL, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).
Parameters Sym. Min. Typ. Max. Units GMIN Conditions
Input Offset Current IOS -800 300 +800 pA all
Across Temperature 320 TA = +85C
Across Temperature -1500 350 +1500 TA = +125C
Common Mode Input Impedance ZCM 1013||10 ||pF
Differential Input Impedance ZDIFF 1013||4
Input Common Mode Voltage (VCM or VREF) (Note 3)
Input Voltage Range (Note 4, Note 5) VIVL VSS 0.25 VSS 0.15 V all
VIVH VDD + 0.15 VDD + 0.30
Common Mode Rejection Ratio CMRR 80 98 dB 1 VCM = VIVL to VIVH, VDD = 1.8V
94 112 10
103 121 100
89 107 1 VCM = VIVL to VIVH, VDD = 5.5V
103 121 10
112 130 100
Common Mode Rejection Ratio at VREF CMRR2 83 101 dB 1 VREF = 0.2V to VDD 0.2V,
98 116 10 VDD = 1.8V
102 120 100
94 112 1 VREF = 0.2V to VDD 0.2V,
109 127 10 VDD = 5.5V
115 133 100
Note 1: VCM = (VIP + VIM)/2, VDM = (VIP VIM) and GDM = 1 + RF/RG.
2: For Design Guidance only; not tested.
3: These specifications apply to the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (use VREF instead).

MCP6N16
4: This specification applies to the VIP, VIM, VREF and VFG pins individually.
5: Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.
DS20005318A-page 5

6: See Section 1.5 Explanation of DC Error Specifications.

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)
DS20005318A-page 6

MCP6N16
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k
to VL, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).
Parameters Sym. Min. Typ. Max. Units GMIN Conditions
Common Mode Nonlinearity (Note 6) INLCM -550 +550 ppm 1 VCM = VIVL to VIVH, VDD = 1.8V
-75 +75 10
-20 +20 100
-310 +310 1 VCM = VIVL to VIVH, VDD = 5.5V
-35 +35 10
-10 +10 100
Input Differential Voltage (VDM) (Note 3)
Differential Input Voltage Range (Note 5) VDML -3.4/GMIN -2.7/GMIN V all VDD 2.9V, VREF = VDD,
VOUT within 0.2%
VDMH +2.7/GMIN +3.4/GMIN VDD 2.9V, VREF = 0V,
VOUT within 0.2%
Differential Gain Error (Note 6) gE 0.03 % 1 VDD = 1.8V, VREF = VDD/2,
0.02 % 10, 100 VDM = (0.7V)/GMIN
0.03 1 VDD = 5.5V, VREF = VDD/2,
0.02 10, 100 VDM = (2.55V)/GMIN
-0.25 0.04 +0.25 % 1 VDD = 5.5V, VREF = 0.2V,
-0.15 0.02 +0.15 % 10, 100 VDM = 0 to (2.7V)/GMIN
-0.25 0.04 +0.25 % 1 VDD = 5.5V, VREF = 5.3V,
-0.15 0.02 +0.15 % 10, 100 VDM = 0 to (-2.7V)/GMIN
Note 1: VCM = (VIP + VIM)/2, VDM = (VIP VIM) and GDM = 1 + RF/RG.
2: For Design Guidance only; not tested.
3: These specifications apply to the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (use VREF instead).
2014 Microchip Technology Inc.

4: This specification applies to the VIP, VIM, VREF and VFG pins individually.
5: Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.
6: See Section 1.5 Explanation of DC Error Specifications.
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)
2014 Microchip Technology Inc.

Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k
to VL, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).
Parameters Sym. Min. Typ. Max. Units GMIN Conditions
Differential Gain Drift (Note 6) gE/TA 3 ppm/C all VDD = 1.8V, VREF = VDD/2,
VDM = (0.7V)/GMIN
4 VDD = 5.5V, VREF = VDD/2,
VDM = (2.55V)/GMIN
4 VDD = 5.5V, VREF = 0.2V,
VDM = 0 to (2.7V)/GMIN
3 VDD = 5.5V, VREF = 5.3V,
VDM = 0 to (-2.7V)/GMIN
Differential Nonlinearity (Note 6) INLDM 300 ppm all VDD = 1.8V, VREF = VDD/2,
VDM = (0.7V)/GMIN
150 VDD = 5.5V, VREF = VDD/2,
VDM = (2.55V)/GMIN
300 VDD = 5.5V, VREF = 0.2V,
VDM = 0 to (2.7V)/GMIN
300 VDD = 5.5V, VREF = 5.3V,
VDM = 0 to (-2.7V)/GMIN
DC Open-Loop Gain AOL 84 102 dB 1 VDD = 1.8V,
100 118 10 VOUT = 0.2V to 1.6V
108 126 100
95 113 1 VDD = 5.5V,
111 129 10 VOUT = 0.2V to 5.3V
119 137 100
Note 1: VCM = (VIP + VIM)/2, VDM = (VIP VIM) and GDM = 1 + RF/RG.
2: For Design Guidance only; not tested.
3: These specifications apply to the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (use VREF instead).

MCP6N16
4: This specification applies to the VIP, VIM, VREF and VFG pins individually.
DS20005318A-page 7

5: Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.
6: See Section 1.5 Explanation of DC Error Specifications.
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)
DS20005318A-page 8

MCP6N16
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k
to VL, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).
Parameters Sym. Min. Typ. Max. Units GMIN Conditions
Output
Minimum Output Voltage Swing VOL VSS + 3 mV all RL = 10 k, VDD = 1.8V,
VDM = -VDD/(2GMIN),
VREF = VDD/2 0.9V
VSS + 6 RL = 10 k, VDD = 5.5V,
VDM = -VDD/(2GMIN),
VREF = VDD/2 1V
VSS + 60 VSS + 250 RL = 1 k, VDD = 5.5V,
VDM = -VDD/(2GMIN),
VREF = VDD/2 1V
Maximum Output Voltage Swing VOH VDD 3 mV RL = 10 k, VDD = 1.8V,
VDM = VDD/(2GMIN),
VREF = VDD/2 + 0.9V
VDD 6 RL = 10 k, VDD = 5.5V,
VDM = VDD/(2GMIN),
VREF = VDD/2 + 1V
VDD 250 VDD 60 RL = 1 k, VDD = 5.5V,
VDM = VDD/(2GMIN),
VREF = VDD/2 + 1V
Output Short-Circuit Current ISC 10 mA VDD = 1.8V
35 VDD = 5.5V
Power Supply
Supply Voltage VDD 1.8 5.5 V all
Quiescent Current per Amplifier IQ 0.5 1.1 1.6 mA IO = 0
2014 Microchip Technology Inc.

POR Trip Voltage VPRL 0.9 1.27 V

VPRH 1.33 1.6 V
Note 1: VCM = (VIP + VIM)/2, VDM = (VIP VIM) and GDM = 1 + RF/RG.
2: For Design Guidance only; not tested.
3: These specifications apply to the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (use VREF instead).
4: This specification applies to the VIP, VIM, VREF and VFG pins individually.
5: Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.
6: See Section 1.5 Explanation of DC Error Specifications.
2014 Microchip Technology Inc.

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2,
RL = 10 k to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
Parameters Sym. Min. Typ. Max. Units GMIN Conditions
AC Response
Gain-Bandwidth Product GBWP 0.5 MHz 1
5 10
35 100
Phase Margin PM 70 all
Open-Loop Output Impedance ROL 1.6 k
Power Supply Rejection Ratio PSRR 80 dB 1 f = 1 kHz
98 10
123 100
Common Mode Rejection Ratio CMRR, CMRR2 83 dB 1 f = 10 kHz
at VCM and VREF 80 10
140 100
Step Response (see Section 4.1.4 AC Performance)
Slew Rate SR Note 1 V/s all
Start-Up Time tSTR 2 ms 1 GDM = 1000, VDD power up to 0.1% VOUT settling (Note 3, Note 4)
0.3 10
0.2 100
Overdrive Recovery, tIRC 1 s all VIP =VIM = VIVH + 0.5V to VDD 1V (or VIVL 0.5V to 1V),
Input Common Mode 90% of VOUT change (IB 2 mA) (Note 4)
Overdrive Recovery, tIRD 10 GMINVDM = GMINVDMH + 0.5V to 0V (or GMINVDML 0.5V to 0V),
Input Differential Mode VREF = 1V (or VDD 1V), 90% of VOUT change (Note 4)
Overdrive Recovery, Output tOR 180 GDMVDM = 1.5V to 0V (or -1.5V to 0V),
VREF = VDD 1V (or 1V), 90% of VOUT change (Note 4)

MCP6N16
Note 1: The slew rate is limited by the GBWP; the large signal step response is dominated by the small signal bandwidth.
2: These parameters were characterized using the circuit in Figure 1-8. In Figures 2-75 and 2-76, there is an IMD tone at DC, a residual tone at 100 Hz and
DS20005318A-page 9

other IMD tones and clock tones.

3: High gains behave differently; see Section 4.4.4 Offset at Power-Up.
4: tSTR, tSTL, tIRC, tIRD and tOR include some uncertainty due to clock edge timing.
TABLE 1-2: AC ELECTRICAL SPECIFICATIONS (CONTINUED)
DS20005318A-page 10

MCP6N16
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2,
RL = 10 k to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
Parameters Sym. Min. Typ. Max. Units GMIN Conditions
Noise
Input Noise Voltage Density eni 900 nV/Hz 1 f = 500 Hz
105 10
45 100
Input Noise Voltage Eni 19 VP-P 1 f = 0.1 Hz to 10 Hz
2.2 10
0.93 100
5.9 1 f = 0.01 Hz to 1 Hz
0.69 10
0.30 100
Input Current Noise Density ini 7 fA/Hz all f = 1 kHz
Output Noise Voltage Density eno 0 nV/Hz
Output Noise Voltage Eno 0 VP-P
Amplifier Distortion (Note 2)
Intermodulation Distortion (AC) IMD 5 VPK all VCM tone = 100 mVPK at 100 Hz
EMI Protection
EMI Rejection Ratio EMIRR 103 dB all VIN = 0.1 VPK, f = 400 MHz
106 VIN = 0.1 VPK, f = 900 MHz
106 VIN = 0.1 VPK, f = 1800 MHz
111 VIN = 0.1 VPK, f = 2400 MHz
Note 1: The slew rate is limited by the GBWP; the large signal step response is dominated by the small signal bandwidth.
2014 Microchip Technology Inc.

2: These parameters were characterized using the circuit in Figure 1-8. In Figures 2-75 and 2-76, there is an IMD tone at DC, a residual tone at 100 Hz and
other IMD tones and clock tones.
3: High gains behave differently; see Section 4.4.4 Offset at Power-Up.
4: tSTR, tSTL, tIRC, tIRD and tOR include some uncertainty due to clock edge timing.
2014 Microchip Technology Inc.

TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS

EN Low Specifications
EN Logic Threshold, Low VIL 0.2VDD V all
EN Input Current, Low IENL -10 pA EN = 0V
GND Current ISS -8 -2 A EN = 0V, VDD = 5.5V
Amplifier Output Leakage IO(LEAK) -1 nA EN = 0V
EN High Specifications
EN Logic Threshold, High VIH 0.8VDD V all
EN Input Current, High IENH 10 pA EN = VDD
EN Dynamic Specifications
EN Input Hysteresis VHYST 0.16VDD V all
EN Input Resistance RPD 1013
EN Low to Amplifier Output High Z Turn-Off Time tOFF 0.1 2 s EN = 0.2VDD to VOUT = 0.1(VDD/2), VL = 0V
EN High to Amplifier Output On Time tON 12 100 VDD = 1.8V, EN = 0.8VDD to VOUT = 0.9(VDD/2), VL = 0V
30 100 VDD = 5.5V, EN = 0.8VDD to VOUT = 0.9(VDD/2), VL = 0V
EN Low to EN High hold time tENLH 50 Minimum time before releasing EN (Note 1)
EN High to EN Low setup time tENHL 50 Minimum time before exerting EN (Note 1)
POR Dynamic Specifications
VDD to Output Off tPHL 10 s all VL = 0V, VDD = 1.8V to VPRL 0.1V step, 90% of VOUT change
VDD to Output On tPLH 100 VL = 0V, VDD = 0V to VPRH + 0.1V step, 90% of VOUT change
Note 1: For design guidance only; not tested.

MCP6N16
DS20005318A-page 11
DS20005318A-page 12

MCP6N16
TABLE 1-4: TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = 1.8V to 5.5V, VSS = GND.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Specified Temperature Range TA -40 +125 C
Operating Temperature Range TA -40 +125 Note 1
Storage Temperature Range TA -65 +150
Thermal Package Resistances
Thermal Resistance, 8L-DFN (33) JA 57 C/W
Thermal Resistance, 8L-MSOP JA 211
Note 1: Operation must not cause TJ to exceed the Absolute Maximum Junction Temperature specification (+150C).
2014 Microchip Technology Inc.
MCP6N16
1.3 Timing Diagrams

1.8V 1.8V to 5.5V

VDD 0V
tSTR 1.001 VREF
VOUT
0.999 VREF

FIGURE 1-1: Amplifier Start-Up Timing Diagram.

VDD 1V 1V
VCM VIVH + 0.5V VIVL 0.5V
tIRC
tIRC
VREF VREF
VOUT

FIGURE 1-2: Common Mode Input Overdrive Recovery Timing Diagram.

VREF 1V VDD 1V

0V 0V
GDMVDM GMINVDMH + 0.5V GMINVDML 0.5V
tIRD
tIRD
VREF VREF
VOUT VOH VOL

FIGURE 1-3: Differential Mode Input Overdrive Recovery Timing Diagram.

VREF VDD 1V 1V

0V 0V
GMINVDM 1.5V
-1.5V
tOR
tOR
VREF VREF
VOUT VOH VOL

FIGURE 1-4: Output Overdrive Recovery Timing Diagram.

VPRL 0.1V VPRH + 0.1V

VDD 1.8V
tPHL
0V tPLH

VOUT High Z High Z

FIGURE 1-5: POR Timing Diagram.

EN
tENLH tENHL
tOFF tON

VOUT High Z High Z

FIGURE 1-6: EN Timing Diagram.

2014 Microchip Technology Inc. DS20005318A-page 13

MCP6N16
1.4 DC Test Circuits 1.4.2 DIFFERENTIAL GAIN TEST CIRCUIT
Figure 1-8 is a simple circuit that can test the INAs
1.4.1 INPUT OFFSET TEST CIRCUIT differential gain error, nonlinearity and input voltage
Figure 1-7 is a simple circuit that can test the INAs range (gE, INLDM, VDML and VDMH; see Section 1.5.3
input offset errors and input voltage range (VE, VIVL and Differential Gain Error and Nonlinearity). RF and
VIVH; see Section 1.5.1 Input Offset Related RG are 0.01% for accurate gain error measurements.
Errors and Section 1.5.2 Input Offset Common The output voltages are (where VE is the sum of input
Mode Nonlinearity). U2 is part of a control loop that offset errors and gE is the gain error):
forces VOUT to equal VCNT; U1 can be set to any bias
point.
EQUATION 1-2:
G DM = 1 + RF RG
VDD VL
V OUT = VREF + G DM 1 + g E V DM + VE
100 nF
VM = V REF + G DM 1 + g E V DM + V E
2.2 F
RL

VCM 100 VOUT

U1 VDD
100 MCP6N16 VL
VREF 2.2 F
VCM + VDM/2
RG RF RL
100 100 100 nF
VOUT
2.2 nF U1
VM
U2 MCP6N16 63.4 k
RF
MCP6H01 1.0 F
31.6 k 100
31.6 k
VM VCNT VCM VDM/2 RG
10 F CCNT RCNT
VREF
2.2 nF 31.6 k

FIGURE 1-7: Simple Test Circuit for FIGURE 1-8: Simple Test Circuit for
Common Mode (Input Offset). Differential Mode.
When MCP6N16 is in its normal range of operation, the For different values of VREF, VDM sweeps over different
DC output voltages are (where VE is the sum of input ranges to keep VREF, VFG and VOUT within their ranges.
offset errors and gE is the gain error): Table 1-6 shows the recommended RF and RG; they
produce a 10 k load. VL can usually be left open.
EQUATION 1-1:
TABLE 1-6: SELECTING RF AND RG
G DM = 1 + RF RG
GMIN RF RG GDM
V OUT = V CNT (V/V) (k) (k) (V/V)
VM = V REF + G DM 1 + g E V E Nom. Nom. Nom. Nom.
1 0 Open 1.0000
Table 1-5 shows the resulting behavior for different 10 10.0 || 90.9 1.00 10.009
GMIN options.
100 10.0 || 1000 100 100.01
TABLE 1-5: RESULTS 1.4.3 DYNAMIC TESTING OF INPUT
BW BW BEHAVIOR
GMIN RF GDM GDMVOS
(kHz) (Hz)
(V/V) (k) (kV/V) (mV) The circuit in Figure 1-8 can test the inputs dynamic
Typ. Typ.
Nom. Typ. Typ. Max. behavior (i.e., IMD, tSTR, tSTL, tIRC, tIRD and tOR);
at VOUT at VM
measure the output at VOUT, instead of at VM.
1 100 1.00 85 0.50 0.50
10 402 4.02 88 1.2
100 68 8.7

DS20005318A-page 14 2014 Microchip Technology Inc.

MCP6N16
1.5 Explanation of DC Error
Specifications VE, VE_LIN (V)
VE_LIN
1.5.1 INPUT OFFSET RELATED ERRORS
V3 VE
The input offset error (VE) is extracted from input offset
V2
measurements (see Section 1.4.1 Input Offset Test
Circuit), based on Equation 1-1:

EQUATION 1-3:
V E = V M V REF G DM 1 + g E V1
VE
VCM (V)
VE has several terms, which assume a linear response VIVL VDD/2 VIVH
to changes in VDD, VSS, VCM, VOUT and TA (all of which
are in their specified ranges): FIGURE 1-9: Input Offset Error vs.
Common Mode Input Voltage.
EQUATION 1-4:
Based on the measured VE data, we obtain the
V DD V SS V CM V REF following linear fit:
V E = V OS + --------------------------------- + ----------------- + --------------------
PSRR CMRR CMRR2
V OUT EQUATION 1-5:
+ ----------------- + T A TC 1
A OL V E_LIN = V OS + VCM V DD 2 CMRR
Where: Where:
PSRR, CMRR, CMRR2 and AOL are in V OS = V2
units of V/V 1 CMRR = V3 V 1 V IVH V IVL
TA is in units of C
TC1 is in units of V/C The remaining error (VE) is described by the Common
Mode Nonlinearity spec:
VDM = 0
EQUATION 1-6:
Equation 1-2 shows how VE affects VOUT.
INL CMH = max VE V IVH VIVL
1.5.2 INPUT OFFSET COMMON MODE INL CML = min V E VIVH V IVL
NONLINEARITY INL CM = INL CMH INL CMH INL CML
The input offset error (VE) changes nonlinearly with = INL CML otherwise
VCM. Figure 1-9 shows VE vs. VCM, as well as a linear Where:
fit line (VE_LIN) based on VOS and CMRR. The INA is in V E = V E V E_LIN
standard conditions (VOUT = 0, VDM = 0, etc.). VCM is
swept from VIVL to VIVH. The test circuit is in The same common mode behavior applies to VE when
Section 1.4.1 Input Offset Test Circuit and VE is VREF is swept, instead of VCM, since both input stages
calculated using Equation 1-3. are designed the same:

EQUATION 1-7:
VE_LIN2 = VOS + V REF V DD 2 CMRR2
INL CMH2 = max V E2 V IVH V IVL
INL CML2 = min V E2 VIVH V IVL
INL CM2 = INL CMH2 INL CMH2 INL CML2
= INL CML2 otherwise
Where:
V E2 = V E VE_LIN2

2014 Microchip Technology Inc. DS20005318A-page 15

MCP6N16
1.5.3 DIFFERENTIAL GAIN ERROR AND EQUATION 1-11:
NONLINEARITY INL DMH = max VED VDMH VDML
The differential errors are extracted from differential INL DML = min VED V DMH V DML
gain measurements (see Section 1.4.2 Differential INL DM = INL DMH INL DMH INL DML
Gain Test Circuit), based on Equation 1-2. These = INL DML otherwise
errors are the differential gain error (gE) and the input
Where:
offset error (VE, which changes nonlinearly with VDM):
V ED = V ED VED_LIN
EQUATION 1-8:
G DM = 1 + RF R G
VM = G DM 1 + g E V DM + V E

These errors are adjusted for the expected output, then

referred back to the input, giving the differential input
error (VED) as a function of VDM:

EQUATION 1-9:
VED = V M GDM V DM

Figure 1-10 shows VED vs. VDM, as well as a linear fit

line (VED_LIN) based on VED and gE. The INA is in
standard conditions (VOUT = 0, etc.). VDM is swept
from VDML to VDMH.

VED, VED_LIN (V)

VED_LIN
V3 VED
V2

V1
VED
VDM (V)
VDML 0 VDMH

FIGURE 1-10: Differential Input Error vs.

Differential Input Voltage.
Based on the measured VED data, we obtain the
following linear fit:

EQUATION 1-10:
V ED_LIN = 1 + g E V E + g E VDM
Where:
g E = V 3 V1 V DMH V DML 1
VE = V2 1 + gE

Note that the VE value measured here is not as

accurate as the one obtained in Section 1.5.1 Input
Offset Related Errors.
The remaining error (VED) is described by the
Differential Nonlinearity spec:

DS20005318A-page 16 2014 Microchip Technology Inc.

MCP6N16
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.

2.1 DC Precision
30% 40%
GMIN = 1 GMIN = 1
28 Samples 35% 28 Samples
s

s
Occurrrences

Occurrrences
25% TA = +25C TA = -40 to +125C
NPBW = 3 mHz NPBW = 3 mHz
30%
20%
25%
VDD = 1.8V
age of O

age of O
VDD = 1.8V
1 8V VDD = 5.5V
5 5V
15% 20%
VDD = 5.5V
15%
%
ercenta

ercenta
10%
10%
Pe

Pe
5%
5%

0% 0%
-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 -600 -400 -200 0 200 400 600
Input Offset Voltage (V) Input Offset Voltage Drift; TC1 (nV/C)
FIGURE 2-1: Input Offset Voltage, with FIGURE 2-4: Input Offset Voltage Drift,
GMIN = 1. with GMIN = 1.

45% 40%
GMIN = 10 GMIN = 10
40% 28 Samples
35% 28 Samples
Percentage of Occurrences

s
Occurrrences

TA = +25C TA = -40 to +125C

35% NPBW = 3 mHz NPBW = 3 mHz
30%
30%
25%
25% VDD = 5.5V
age of O

20% VDD = 1.8V

1 8V
20%
VDD = 1.8V VDD = 5.5V
15%
%
ercenta

15%
10% 10%
Pe

5% 5%
0% 0%
-2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 -40 -30 -20 -10 0 10 20 30 40
Input Offset Voltage (V) Input Offset Voltage Drift; TC1 (nV/C)
FIGURE 2-2: Input Offset Voltage, with FIGURE 2-5: Input Offset Voltage Drift,
GMIN = 10. with GMIN = 10.

60% 40%
GMIN = 100 GMIN = 100
28 Samples 28 Samples
35%
Percentage of Occurrences

s
Occurrrences

50% TA = +25C TA = -40 to +125C

NPBW = 3 mHz NPBW = 3 mHz
30%
40%
25%
age of O

30% 20%
VDD = 1.8V VDD = 5.5V VDD = 1.8V VDD = 5.5V
15%
%
ercenta

20%
10%
10%
Pe

5%
0% 0%
-1.0 -0.6 -0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 -16 -12 -8 -4 0 4 8 12 16
Input Offset Voltage (V) Input Offset Voltage Drift; TC1 (nV/C)
FIGURE 2-3: Input Offset Voltage, with FIGURE 2-6: Input Offset Voltage Drift,
GMIN = 100. with GMIN = 100.

2014 Microchip Technology Inc. DS20005318A-page 17

MCP6N16
Note: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.

55% 30
GMIN = 1 Representative Part
50% 25
es

28 Samples GMIN = 1
tage off Occurrence

45% TA = -40 to +125C 20 NPBW = 2 Hz

e (V)
NPBW = 3 mHz
40% 15

Voltage
35% 10
30% VDD = 1.8V 5

Offset V
VDD = 5.5V
5 5V 0
25%
20% -5
Percent

nput O
15% -10
10% -15 VDD = 1.8V VDD = 5.5V

In
P

5% 20
-20
0% -25
-1200
1200 -800
800 -400
400 0 400 800 1200 -30
30
Quadratic Input Offset Voltage Drift; 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
2
TC2 (pV/C ) Output Voltage (V)
FIGURE 2-7: Quadratic Input Offset FIGURE 2-10: Input Offset Voltage vs.
Voltage Drift, with GMIN = 1. Output Voltage, with GMIN = 1.

30% 30
GMIN = 10 Representative Part
25
es

28 Samples GMIN = 10
tage off Occurrence

25% TA = -40 to +125C 20 NPBW = 2 Hz

e (V)
NPBW = 3 mHz
15
20%
Voltage
10
5
15% VDD = 1.8V
Offset V
VDD = 5.5V 0
-5 VDD = 1.8V VDD = 5.5V
10%
Percent

nput O

-10
5% -15
In
P

20
-20
0% -25
-160
160 -120
120 -80
80 -40 40 0 40 80 120 160 -30
30
Quadratic Input Offset Voltage Drift; 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
2
TC2 (pV/C ) Output Voltage (V)
FIGURE 2-8: Quadratic Input Offset FIGURE 2-11: Input Offset Voltage vs.
Voltage Drift, with GMIN = 10. Output Voltage, with GMIN = 10.

45% 30
GMIN = 100 Representative Part
40% p
28 Samples 25
es

GMIN = 100
tage off Occurrence

TA = -40 to +125C 20 NPBW = 2 Hz

e (V)

35% NPBW = 3 mHz

15
30%
Voltage

10
VDD = 5.5V
25% VDD = 1.8V 5
Offset V

20% 0
-5 VDD = 1.8V VDD = 5.5V
15%
Percent

nput O

-10
10% -15
In
P

5% 20
-20
0% -25
-120
120 -100
100 -80
80 -60 60 -4040 -2020 0 20 40 -30
30
Quadratic Input Offset Voltage Drift; 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
TC2 (pV/C2) Output Voltage (V)
FIGURE 2-9: Quadratic Input Offset FIGURE 2-12: Input Offset Voltage vs.
Voltage Drift, with GMIN = 100. Output Voltage, with GMIN = 100.

DS20005318A-page 18 2014 Microchip Technology Inc.

50 50
Representative Part Representative Part
40 VCM = VSS 40 VCM = VDD
GMIN = 1 GMIN = 1

e (V)
Offset Voltage (V)

30 NPBW = 2 Hz 30 NPBW = 2 Hz
20 20

Voltage
10 10

Offset V
0 0
-10 -10

Input O
Input O

-20 -20
+125C +125C
-30 -30 +85C
+85C
-40 +25C -40 +25C
-40C -40C
-50 -50
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V) Power Supply Voltage (V)
FIGURE 2-13: Input Offset Voltage vs. FIGURE 2-16: Input Offset Voltage vs.
Power Supply Voltage, with VCM = 0V and Power Supply Voltage, with VCM = VDD and
GMIN = 1. GMIN = 1.

30 30
Representative Part Representative Part
25 VCM = VSS 25 VCM = VDD
20 GMIN = 10 20 GMIN = 10
e (V)

e (V)
NPBW = 2 Hz NPBW = 2 Hz
15 15
Voltage

Voltage
10 10
5 5
Offset V

Offset V
0 0
-5 -5
Input O

Input O

10
-10 10
-10
-15 +125C -15
85 C
+85C +125C
20
-20 +25C
20
-20 +85C
-25 -40C -25 +25C
-40C
-30
30 -30
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V) Power Supply Voltage (V)
FIGURE 2-14: Input Offset Voltage vs. FIGURE 2-17: Input Offset Voltage vs.
Power Supply Voltage, with VCM = 0V and Power Supply Voltage, with VCM = VDD and
GMIN = 10. GMIN = 10.

30 30
Representative Part Representative Part
25 VCM = VSS 25 VCM = VDD
20 GMIN = 100 20 GMIN = 100
e (V)

e (V)

NPBW = 2 Hz NPBW = 2 Hz
15 15
Voltage

Voltage

10 10
5 5
Offset V

Offset V

0 0
-5 -5
Input O

Input O

10
-10 10
-10
-15 +125C -15 +125C
85 C
+85C
20
-20 +25C
20
-20 +85C
+25C
-25 -40C -25 -40C
-30
30 -30
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V) Power Supply Voltage (V)
FIGURE 2-15: Input Offset Voltage vs. FIGURE 2-18: Input Offset Voltage vs.
Power Supply Voltage, with VCM = 0V and Power Supply Voltage, with VCM = VDD and
GMIN = 100. GMIN = 100.

2014 Microchip Technology Inc. DS20005318A-page 19

50 50
Representative Part Representative Part
40 VDD = 1.8V 40 VDD = 5.5V
GMIN = 1 GMIN = 1

e (V)
Offset Voltage (V)

30 NPBW = 2 Hz 30 NPBW = 2 Hz
20 20

Voltage
10 10

Offset V
0 0
-10 -10

Input O
Input O

-20 -20
+125C +125C
-30 +85C -30 85 C
+85C
+25C +25C
-40 -40 -40C
-40C
-50 -50
50
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Common Mode Voltage (V) Input Common Mode Voltage (V)
FIGURE 2-19: Input Offset Voltage vs. FIGURE 2-22: Input Offset Voltage vs.
Common Mode Voltage, with VDD = 1.8V and Common Mode Voltage, with VDD = 5.5V and
GMIN = 1. GMIN = 1.

50 50
Representative Part Representative Part
40 VDD = 1.8V
8 40 VDD = 5.5V
GMIN = 10 GMIN = 10
e (V)

e (V)
30 NPBW = 2 Hz 30 NPBW = 2 Hz
20 20
Voltage

Voltage

10 10
Offset V

Offset V

0 0
-10 -10
Input O

Input O

-20 -20
+125C +125C
-30 +85C
+85 C -30 +85 C
+85C
+25C +25C
-40 -40C -40 -40C
-50
50 -50
50
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Common Mode Voltage (V) Input Common Mode Voltage (V)
FIGURE 2-20: Input Offset Voltage vs. FIGURE 2-23: Input Offset Voltage vs.
Common Mode Voltage, with VDD = 1.8V and Common Mode Voltage, with VDD = 5.5V and
GMIN = 10. GMIN = 10.

50 50
Representative Part Representative Part
40 VDD = 1.8V
8 40 VDD = 5.5V
GMIN = 100 GMIN = 100
e (V)

e (V)

30 NPBW = 2 Hz 30 NPBW = 2 Hz
20 20
Voltage

Voltage

10 10
Offset V

Offset V

0 0
-10 -10
Input O

Input O

-20 -20
+125C +125C
-30 +85C
+85 C -30 85 C
+85C
+25C +25C
-40 -40C -40 -40C
-50
50 -50
50
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Common Mode Voltage (V) Input Common Mode Voltage (V)
FIGURE 2-21: Input Offset Voltage vs. FIGURE 2-24: Input Offset Voltage vs.
Common Mode Voltage, with VDD = 1.8V and Common Mode Voltage, with VDD = 5.5V and
GMIN = 100. GMIN = 100.

DS20005318A-page 20 2014 Microchip Technology Inc.

30 60%
Representative Part 410 Samples
25 GMIN = 1 55% TA = +25C

Percentage of Occurrences
20 TA = +25C 50% GMIN = 1
Input Offset Voltage (V)

NPBW = 2 Hz NPBW = 2.5 Hz

15 45%
10 40%
VDD = 5.5V
5 35%
0 30%
-5 25%
-10 20%
VDD = 1.8V VDD = 5.5V
-15 15%
VDD = 1.8V
-20 10%
-25 5%
-30 0%
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -12 -8 -4 0 4 8 12
Reference Voltage (V) 1/CMRR (V/V)

FIGURE 2-25: Input Offset Voltage vs. FIGURE 2-28: CMRR, with GMIN = 1.
Reference Voltage, with GMIN = 1.

30 50%
Representative Part 310 Samples
25 GMIN = 10 45% TA = +25C

Percentage of Occurrences
20 TA = +25C GMIN = 10
Input Offset Voltage (V)

NPBW = 2 Hz
40% NPBW = 2.5 Hz
15
35%
10 VDD = 5.5V
5 30%
0 25%
-5 20%
VDD = 1.8V
-10 15%
VDD = 1.8V VDD = 5.5V
-15
10%
-20
-25 5%
-30 0%
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -5 -4 -3 -2 -1 0 1 2 3 4 5
Reference Voltage (V) 1/CMRR (V/V)

FIGURE 2-26: Input Offset Voltage vs. FIGURE 2-29: CMRR, with GMIN = 10.
Reference Voltage, with GMIN = 10.

30 70%
Representative Part 65% 410 Samples
25 GMIN = 100 TA = +25C
Percentage of Occurrences

60% GMIN = 100

20 TA = +25C
Input Offset Voltage (V)

NPBW = 2 Hz 55% NPBW = 2.5 Hz

15 50%
10 VDD = 5.5V
45%
5 40%
0 35%
-5 30%
25%
-10
VDD = 1.8V VDD = 5.5V 20%
-15 15%
VDD = 1.8V
-20 10%
-25 5%
-30 0%
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0
Reference Voltage (V) 1/CMRR (V/V)

FIGURE 2-27: Input Offset Voltage vs. FIGURE 2-30: CMRR, with GMIN = 100.
Reference Voltage, with GMIN = 100.

2014 Microchip Technology Inc. DS20005318A-page 21

55% 20%
410 Samples 410 Samples
50% TA = +25C 18% TA = +25
+25C
C
Percentage of Occurrences

Occurrrences
45% GMIN = 1 VDD = 1.8V to 5.5V
NPBW = 2.5 Hz 16% GMIN = 1
40% NPBW = 2.5 Hz
VDD = 5.5V 14%
35%
12%
30%

age of O
10%
25%
20% 8%

ercenta
15% 6%
VDD = 1.8V
10% 4%
%

Pe
5% 2%
0% 0%
-10 -8 -6 -4 -2 0 2 4 6 8 10 -5 -4 -3 -2 -1 0 1 2 3 4 5
1/CMRR2 (V/V) 1/PSRR (V/V)
FIGURE 2-31: CMRR2, with GMIN = 1. FIGURE 2-34: PSRR, with GMIN = 1.

55% 20%
310 Samples 310 Samples
50% TA = +25
+25CC 18% TA = +25
+25CC

Occurrrences
Occurrrences

45% GMIN = 10 VDD = 1.8V to 5.5V

NPBW = 2.5 Hz 16% GMIN = 10
40%
% 14% NPBW = 2.5 Hz
35%
12%
age of O
age of O

30%
VDD = 5.5V 10%
25%
8%
20%
ercenta
ercenta

6%
15%
10% 4%
%
Pe
Pe

VDD = 1.8V
5% 2%
0% 0%
-1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
1/CMRR2 (V/V) 1/PSRR (V/V)
FIGURE 2-32: CMRR2, with GMIN = 10. FIGURE 2-35: PSRR, with GMIN = 10.

90% 22%
410 Samples 410 Samples
80% TA = +25
+25C
C 20% TA = +25
+25C
C
Occurrrences
Occurrrences

GMIN = 100 18% VDD = 1.8V to 5.5V

70% NPBW = 2.5 Hz GMIN = 100
16% NPBW = 2.5 Hz
60% 14%
50%
age of O

12%
age of O

VDD = 5.5V
40% 10%
8%
ercenta
ercenta

30%
6%
20%
4%
Pe
Pe

VDD = 1.8V
1 8V
10% 2%
0% 0%
-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
1/CMRR2 (V/V) 1/PSRR (V/V)
FIGURE 2-33: CMRR2, with GMIN = 100. FIGURE 2-36: PSRR, with GMIN = 100.

DS20005318A-page 22 2014 Microchip Technology Inc.

55% 150
410 Samples GMIN = 100, VDD = 5.5V
50% TA = +25C 145 VDD = 1.8V
8
Percentage of Occurrences

45% GMIN = 1 140

NPBW = 2.5 Hz
40% 135
VDD = 5.5V
35% 130

(dB)
125
30%
120

CMRR
25%
115
20%

C
110
15% 105
VDD = 1.8V
10% 100
GMIN = 10, VDD = 5.5V GMIN = 1, VDD = 5.5V
5% 95 VDD = 1.8V VDD = 1.8V
0% 90
-10 -8 -6 -4 -2 0 2 4 6 8 10 -50 -25 0 25 50 75 100 125
1/AOL (V/V) Ambient Temperature (C)
FIGURE 2-37: DC Open-Loop Gain, with FIGURE 2-40: CMRR vs. Ambient
GMIN = 1. Temperature.

55% 150
310 Samples
50% TA = +25C
+25 C
145
Occurrrences

45% GMIN = 10 140

NPBW = 2.5 Hz
40%
% 135
130

2 (dB)
35%
125
age of O

30%
CMRR2
VDD = 5.5V 120
25%
115
20%
C
ercenta

110
15% GMIN = 100, VDD = 5.5V
105 VDD = 1.8V
10% 100
Pe

VDD = 1.8V GMIN = 10, VDD = 5.5V GMIN = 1, VDD = 5.5V

5% 95 VDD = 1.8V VDD = 1.8V
0% 90
-1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 -50 -25 0 25 50 75 100 125
1/AOL (V/V) Ambient Temperature (C)
FIGURE 2-38: DC Open-Loop Gain, with FIGURE 2-41: CMRR2 vs. Ambient
GMIN = 10. Temperature.

90% 150
410 Samples
80% TA = +25C
+25 C
145 GMIN = 100
Occurrrences

GMIN = 100 140

70% NPBW = 2.5 Hz
135
60% 130 GMIN = 10
PSRR (dB)

125
50%
age of O

VDD = 5.5V 120

40% 115 GMIN = 1
ercenta

30% 110
105
20%
100
Pe

VDD = 1.8V
1 8V
10% 95 VDD = 1.8V to 5.5V
0% 90
-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 -50 -25 0 25 50 75 100 125
1/AOL (V/V) Ambient Temperature (C)
FIGURE 2-39: DC Open-Loop Gain, with FIGURE 2-42: PSRR vs. Ambient
GMIN = 100. Temperature.

2014 Microchip Technology Inc. DS20005318A-page 23

150 1000

A)
145

ents (pA
DC Open-Loop Gain; AOL (dB)

140
| IOS |
135

Input Bias, Offsett Curre

130 100
125
120
115
110 10
GMIN = 100, VDD = 5.5V IB
105 VDD = 1.8V
100
GMIN = 10, VDD = 5.5V GMIN = 1, VDD = 5.5V
95 VDD = 1.8V VDD = 1.8V
90 1
-50 -25 0 25 50 75 100 125 25 45 65 85 105 125
Ambient Temperature (C) Ambient Temperature (C)
FIGURE 2-43: DC Open-Loop Gain vs. FIGURE 2-46: Input Bias and Offset
Ambient Temperature. Currents vs. Ambient Temperature, with
VDD = 5.5V.

600 1m
1.E-3

Input Bias Current Magnitude (A)

Representative Part
500
A)
ents (pA

TA = +85C
85 C 100
1.E-4
400 VDD = 5.5V
300 10
1.E-5
Input Bias, Offsett Curre

200 1.E-6
1
100
0 1.E-7
100n
IB
-100 1.E-8
10n
-200
-300 1.E-9
1n -40C
-400
400 +25C
IOS
1.E-10
100p +85C
-500 +125C
-600
600 1.E-11
10p
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Common Mode Input Voltage (V) Input Voltage (V)

FIGURE 2-44: Input Bias and Offset FIGURE 2-47: Input Bias Current
Currents vs. Common Mode Input Voltage, with Magnitude vs. Input Voltage (below VSS).
TA = +85C.

1,000 0.10
Representative Part Representative Parts GMIN = 100;
A)

800 0.08
ents (pA

TA = +125C
125 C VDD = 1.8V
VDD = 5.5V VDD = 5.5V
600 0.06
400 0 04
0.04
Input Bias, Offsett Curre

ain Errror (%)

IB
200 0.02
0 0.00
-200 -0.02
Ga

-400 -0.04
IOS
-600
600 -0.06
0.06
GMIN = 1; GMIN = 10;
-800 -0.08 VDD = 1.8V VDD = 1.8V
VDD = 5.5V VDD = 5.5V
-1,000
1 000 -0.10
0 10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100 125
Common Mode Input Voltage (V) Ambient Temperature (C)
FIGURE 2-45: Input Bias and Offset FIGURE 2-48: Gain Error vs. Ambient
Currents vs. Common Mode Input Voltage, with Temperature.
TA = +125C.

DS20005318A-page 24 2014 Microchip Technology Inc.

16%
405 Samples
es

14% GMIN = 1
Percenttage off Occurrence

VDD = 1.8V VDD = 5.5V

12%
10%
8%
6%
4%
2%
P

0%
-0.14

-0.04
4
-0.12
-0.10
-0.08
-0.06
4
-0.02
0.00
2
0.02
0.04
4
0.06
0.08
0.10
2
0.12
0.14
4
Gain Error (%)
FIGURE 2-49: Gain Error, with GMIN = 1.

18%
306 Samples
16%
es

GMIN = 10
Percenttage off Occurrence

14%
12%
10%
8%
6%
VDD = 1.8V VDD = 5.5V
4%
2%
P

0%
-0.14

-0.04
4
-0.12
-0.10
-0.08
-0.06
4
-0.02
0.00
0.02
0.04
4
0.06
0.08
0.10
0.12
0.14
4

Gain Error (%)

FIGURE 2-50: Gain Error, with GMIN = 10.

18%
386 Samples
16%
es

GMIN = 100
Percenttage off Occurrence

14%
12%
10%
8%
6%
VDD = 1.8V VDD = 5.5V
4%
2%
P

0%
-0.14

-0.04
4
-0.12
-0.10
-0.08
-0.06
4
-0.02
0.00
2
0.02
0.04
4
0.06
0.08
0.10
2
0.12
0.14
4

Gain Error (%)

FIGURE 2-51: Gain Error, with GMIN = 100.

2014 Microchip Technology Inc. DS20005318A-page 25

2.2 Other DC Voltages and Currents

0.4 100
1st Wafer Lot VDD = 5.5V

V)
om

om (mV
03
0.3 RL = 1 k
eadroo

VIVH VDD 80
0.2 VDD VOH

Headroo
70
nge He

0.1 60
age Ran

put Volltage H
(V))

0.0 50
VOL VSS
-0.1 40
ut Volta

VIVL VSS 30
-0.2
20

Outp
Inpu

-0.3 10
-0.4
04 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Ambient Temperature (C) Ambient Temperature (C)
FIGURE 2-52: Input Voltage Range FIGURE 2-55: Output Voltage Headroom
Headroom vs. Ambient Temperature. vs. Ambient Temperature.

4.2 1.2
1st Wafer Lot
4.0 GMINVDMH = -G
GMINVDML 1.1
ut
Range;; GMINVDMH (V))
al Inpu

RTO 1.0
3.8
mA) 0.9
36
3.6
ed Diffferentia

Supply Currrent (m
+125C
0.8 +85C
3.4 0.7 +25C
GMIN = 1,, 10,, 100 -40
40C
C
3.2 0.6
3.0 0.5
Normalize
oltage R

2.8 0.4
0.3
2.6
Vo

02
0.2
2.4 0.1
22
2.2 0.0
00
-50 -25 0 25 50 75 100 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Ambient Temperature (C) Power Supply Voltage (V)
FIGURE 2-53: Normalized Differential Input FIGURE 2-56: Supply Current vs. Power
Voltage Range vs. Ambient Temperature. Supply Voltage.

1.2
1.1
V)
om (mV

100 VDD = 5.5V

VDD = 1.8V 1.0
VDD = 1.8V
mA)

0.9
Headroo

ply Current (m

0.8
VDD VOH VDD = 5.5V 0.7
put Volltage H

0.6
10 0.5
Supp

04
0.4
VOL VSS 0.3
Outp

02
0.2
0.1
1 0.0
00
0.1 1 10 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Output Current Magnitude (mA) Common Mode Input Voltage (V)
FIGURE 2-54: Output Voltage Headroom FIGURE 2-57: Supply Current vs. Common
vs. Output Current Magnitude. Mode Input Voltage.

DS20005318A-page 26 2014 Microchip Technology Inc.

50
mA)

40
uit Currrent (m

30
20
10 +125C
ut Shorrt-Circu

+85C
+85 C
0 +25C
-10 -40C

-20
-30
30
Outpu

-40
-50
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
FIGURE 2-58: Output Short-Circuit Current
vs. Power Supply Voltage.

50%
103 Samples
45% 1 Wafer Lot
Percenttage of Occurrences

TA = +25C
40%
35%
30%
VPRL VPRH
25%
20%
15%
10%
5%
0%
1.20

1.22

1.24

1.26

1.28

1.30

1.32

1.34

1.36

1.38

1.40

Power-On Reset Trip Voltages (V)

FIGURE 2-59: Power-On Reset Trip
Voltages.

1.60
1 Wafer Lot
Trip Voltages (V)

1.55
1 50
1.50
1.45
1.40 VPRH
1.35
1.30
Reset T

1.25
VPRL
1.20
1 15
1.15
er-On R

1.10
1.05
Powe

1.00
0.95
0.90
0 90
-50 -25 0 25 50 75 100 125
Ambient Temperature (C)
FIGURE 2-60: Power-On Reset Trip
Voltages vs. Temperature.

2014 Microchip Technology Inc. DS20005318A-page 27

2.3 Frequency Response

130 500
VDD = 5.5V
120

dwidth
h
WP/GMINN (kHz)
110 450
100

zed Gaiin Band

90 400
(dB)

Prroductt; GBW
70 350
CMRR

60
C

ormaliz
0
50 300
40
250

No
30 GMIN = 100 GMIN = 1
GMIN = 10 GMIN = 10
20 GMIN = 1 GMIN = 100 VDD = 1.8V
10 200
1.E+04
10k 1.E+05
100k 1.E+06
1M -50 -25 0 25 50 75 100 125
Frequency (Hz) Ambient Temperature (C)
FIGURE 2-61: CMRR vs. Frequency. FIGURE 2-64: Normalized Gain-Bandwidth
Product vs. Ambient Temperature.

120 85
VDD = 5.5V
110
100 80
90
argin ()

80 75
PSRR (dB)

70
ase Ma

60 70
50
Pha

40 65
30
20 GMIN = 100 60 GMIN = 1
GMIN = 10 GMIN = 10
10 GMIN = 1 VDD = 1.8V GMIN = 100
0 55
1.E+03
1k 1.E+04
10k 1.E+05
100k 1.E+06
1M -50 -25 0 25 50 75 100 125
Frequency (Hz) Ambient Temperature (C)
FIGURE 2-62: PSRR vs. Frequency. FIGURE 2-65: Phase Margin vs. Ambient
Temperature.

120 -60 1.E+4

10k
GMIN = 1, 10, 100
p Gain Phase; AOL ()

100 -90
op Gain Magnitude;

80 -120
ed-Loop Output
mpedance ()

60 -150 1.E+3
1k
|AOL| (dB)

40 -180
20 AOL; -210
GMIN = 100
Open-Loo

Close
Open-Loop

0 GMIN = 10 240
-240 1.E+2
100
GMIN = 1
-20 |AOL|; -270 GDM/GMIN = 1
GMIN = 100
-40 GMIN = 10 -300 GDM/GMIN = 10
GMIN = 1 GDM/GMIN = 100
-60 -330 10
1.E+1
1k
1.E+3 10k
1.E+4 100k
1.E+5 1M
1.E+6 10M
1.E+7 1k
1.E+3 10k
1.E+4 100k
1.E+5 1M
1.E+6
Frequency (Hz) Frequency (Hz)
FIGURE 2-63: Open-Loop Gain vs. FIGURE 2-66: Closed-Loop Output
Frequency. Impedance vs. Frequency.

DS20005318A-page 28 2014 Microchip Technology Inc.

10 140
f = 900 MHz
9 130 VDD = 5.5V

8 120
B)

at VIP
n Peaking (dB

7 GMIN = 1
GDM = 1 110

R (dB)
6
100
GMIN = 10

EMIRR
5
GDM = 10 90
4 GMIN = 100 = 20

E
Gain

GDM = 100 = 50 80
3 = 200 GMIN = 1 at VREF
= 500 70 GMIN = 10
2 GMIN = 100
1 60
0 50
10 100 1,000 0.01 0.1 1 2
Normalized Capacitive Load; CL GMIN/GDM (pF) Input Voltage (VPK)
FIGURE 2-67: Gain Peaking vs. FIGURE 2-70: EMIRR vs. Input Voltage,
Normalized Capacitive Load. with f = 900 MHz.

140 140
VIN = 100 mVPK, at VIP or VREF f = 1800 MHz
130 VDD = 55.5V
5 130 VDD = 5.5V

120 120
at VREF
110 110
R (dB)

R (dB)
100 100
EMIRR

90 EMIRR 90
GMIN = 1
E

80 GMIN = 10 80
GMIN = 100 GMIN = 1 at VIP
70 70 GMIN = 10
GMIN = 100
60 60
50 50
10M
1.E+07 100M
1.E+08 1G
1.E+09 10G
1.E+10 0.01 0.1 1 2
Frequency (Hz) Input Voltage (VPK)
FIGURE 2-68: EMIRR vs. Frequency, with FIGURE 2-71: EMIRR vs. Input Voltage,
VIN = 100 mVPK. with f = 1800 MHz.

140 140
f = 400 MHz f = 2400 MHz
130 VDD = 5.5V 130 VDD = 5.5V

120 120 at VREF

at VREF
110 110
R (dB)

R (dB)

100 100
EMIRR

EMIRR

90 90
E

80 80 att VIP
GMIN = 1 at VIP
70 GMIN = 10 70 GMIN = 1
GMIN = 100 GMIN = 10
60 60 GMIN = 100

50 50
0.01 0.1 1 2 0.01 0.1 1 2
Input Voltage (VPK) Input Voltage (VPK)
FIGURE 2-69: EMIRR vs. Input Voltage, FIGURE 2-72: EMIRR vs. Input Voltage,
with f = 400 MHz. with f = 2400 MHz.

2014 Microchip Technology Inc. DS20005318A-page 29

2.4 Noise

20 20m 100
Eni(0 Hz to f); VDD tone = 100 mVPK, f = 100 Hz
1.E+4
10 10m
1.E+6

d Input Noise Voltage

GMIN = 1
Input Noise Voltage Density

eni; GMIN = 10 IMD Residual

R id l

m, RTI ((VPK)
GMIN = 1 GMIN = 100 Tone 100 Hz
GMIN = 10 at DC Tone GMIN = 1
GMIN = 100 10
1.E+3
1 1m
1.E+5
(V/Hz)

(VP-P)

ectrum
GMIN = 10

MD Spe
Integrated
100n
1.E+2 100
1.E+4 1

IM
GMIN = 100
10n
1.E+1 10
1.E+3 0.1
01
0.1 1.E+0
1.E-1 1 1.E+1
10 1.E+2
100 1.E+3
1k 1.E+4
10k 1.E+5
100k 1.E+0
1 1.E+1
10 1.E+2
100 1.E+3
1k 1.E+4
10k 1.E+5
100k
Frequency (Hz) Frequency (Hz)
FIGURE 2-73: Input Noise Voltage Density FIGURE 2-76: Intermodulation Distortion
and Integrated Input Noise Voltage vs. vs. Frequency with VDD Disturbance
Frequency. (see Figure 1-8).

1E+3
1
GMIN = 1
y
Density

oise Voltage; eni(t)

f = 100 Hz
put Noise Volltage D

GMIN = 1
GMIN = 10
(5 V/div)

GMIN = 100
Hz)
(V/H

1E+2
100n

NPBW = 10 Hz
Input No
Inp

NPBW = 1 Hz
1E+1
10n
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 20 40 60 80 100 120 140 160 180 200
Common Mode Input Voltage (V) Time (s)

FIGURE 2-74: Input Noise Voltage Density FIGURE 2-77: Input Noise Voltage vs.
vs. Input Common Mode Voltage. Time, with 1 Hz and 10 Hz Filters and GMIN = 1.

100 GMIN = 10
VCM tone = 100 mVPK, f = 100 Hz
Voltage;; eni(t)

IMD Residual 60 Hz
ectrum, RTI (VPK)

Tone 100 Hz Harmonics

at DC Tone GMIN = 1
10
V/div)
nput Noise Vo
(0.5 V

GMIN = 10 NPBW = 10 Hz
IMD Spe

1
In

GMIN = 100 NPBW = 1 Hz

0.1
1.E+0
1 1.E+1
10 1.E+2
100 1.E+3
1k 1.E+4
10k 1.E+5
100k 0 20 40 60 80 100 120 140 160 180 200
Frequency (Hz) Time (s)

FIGURE 2-75: Intermodulation Distortion FIGURE 2-78: Input Noise Voltage vs.
vs. Frequency with VCM Disturbance (see Time, with 1 Hz and 10 Hz Filters and GMIN = 10.
Figure 1-8).

DS20005318A-page 30 2014 Microchip Technology Inc.

GMIN = 100
put Noise Volltage; eni(t)
div)
0.2 V/d
(0

NPBW = 10 Hz
Inp

NPBW = 1 Hz

0 20 40 60 80 100 120 140 160 180 200

Time (s)

FIGURE 2-79: Input Noise Voltage vs.

Time, with 1 Hz and 10 Hz Filters and
GMIN = 100.

2014 Microchip Technology Inc. DS20005318A-page 31

2.5 Time Response

100 125 5 7
NPBW = 1.3 Hz VDD = 5.5V
90 100

al Modee
4 6
80 75

oltage; GDMVDDM (V)

e (C)
VDM
e (V)

70 50 3 5

V)
put Volltage (V
erature

erentia
Voltage

60 GMIN = 1 TSEN 25
GMIN = 10 2 4
50 0
GMIN = 100

ed Diffe
Sensorr Tempe
Offset V

40 -25 1 3
30 -50
0 2

Outp
nput Vo
Norrmalize
nput O

20 -75
10 VOS -100 -1 VOUT; 1
In

GMIN = 1

In
S
0 125
-125
-2 GMIN = 10 0
-10 -150 GMIN = 100
-20
20 -175
175 -3
3 -1
1
0 20 40 60 80 100 120 140 160 180 0 1 2 3 4 5 6 7 8 9 10
Time (s) Time (ms)
FIGURE 2-80: Input Offset Voltage vs. FIGURE 2-83: The MCP6N16 Shows No
Time with Temperature Change. Phase Reversal vs. Differential Input Overdrive,
with VDD = 5.5V.

30 200 0.2 2.2

GDM = 1000
0.0 2.0
25 150
ge (V)

oltage; GDMVDDM (V)

e (V)

GMIN = 1 -0.2 GDMVDM 1.8

ntial

GMIN = 10

V)
20 100 -0.4 1.6

put Volltage (V
Differen
y Voltag

Voltage

GMIN = 100 VOUT;

-0.6 GMIN = 1 1.4
15 50 GMIN = 10
0.8
-0 8 12
1.2
alized D
Offset V
Supply

VOS GMIN = 100

10 0 -1.0 1.0
Power S

-1 2
-1.2 08
0.8

Outp
nput Vo
Input O

Norma

5 -50 -1.4 0.6

N
In

-1.6
16 0.4
04
P

0 -100
VDD -1.8 0.2
-5
5 -150
150 -2.0
20 00
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 1 2 3 4 5 6 7 8 9 10
Time (ms) Time (ms)
FIGURE 2-81: Input Offset Voltage vs. FIGURE 2-84: The MCP6N16 Shows No
Time at Power-Up. Phase Reversal vs. Output Overdrive to VSS.

7 3.2 2.0 5.5

VDD = 5.5V
Mode Input Voltage (V)

1.8 5.3
6 3.1
oltage;; GDMVDDM (V)

VCM 1.6 5.1

Differential

5 3.0
V)
put Voltage (V)

1.4 4.9
put Voltage (V

4 2.9 1.2 4.7

1.0 4.5
alized D

3 2.8 VOUT;
0.8 GMIN = 1 4.3
2 2.7 GMIN = 10
06
0.6 41
4.1
Outp
Outp

nput Vo
Norma
Common M

GMIN = 100
1 2.6 0.4 3.9
VOUT;
02
0.2 37
3.7
In

GMIN = 1 GDMVDM
0 GMIN = 10 2.5
GMIN = 100
0.0 3.5
-1 2.4 -0.2
02 33
3.3
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
Time (ms) Time (ms)
FIGURE 2-82: The MCP6N16 Shows No FIGURE 2-85: The MCP6N16 Shows No
Phase Reversal vs. Common Mode Input Phase Reversal vs. Output Overdrive to VDD.
Overdrive, with VDD = 5.5V.

DS20005318A-page 32 2014 Microchip Technology Inc.

1000
VDD = 5.5V

Differential Input Overdrive

e (10 mV/div)

GMIN = 1

Recovery Time (s)

GMIN = 10
100 GMIN = 100
GMIN = 1
GMIN = 10
utput Voltage

GMIN = 100
V

10
Ou

1
0 5 10 15 20 25 30 35 40 45 50 1 10
Time (s) Normalized Gain; GDM/GMIN

FIGURE 2-86: Small Signal Step FIGURE 2-89: Differential Input Overdrive
Response. Recovery Time vs. Normalized Gain.

5.5 5.5
5.0 5.0
4.5 4.5
V)

V)
4.0 4.0
put Volltage (V

put Volltage (V
3.5 GMIN = 1 3.5
3.0 GMIN = 10 3.0 GMIN = 1
GMIN = 100 GMIN = 10
2.5 2.5 GMIN = 100
20
2.0 20
2.0
Outp

Outp

1.5 1.5
10
1.0 10
1.0
0.5 0.5
0.0
00 0.0
00
0 5 10 15 20 25 30 35 40 45 50 0 50 100 150 200 250 300 350 400 450 500 550 600
Time (s) Time (s)
FIGURE 2-87: Large Signal Step FIGURE 2-90: Output Overdrive Recovery
Response. vs. Time.

5.5 1000
VDD = 5.5V
5.0 VDD = 5.5V Recovery from VSS and VDD
Output Overdrive Recovery

4.5
put Voltage (V)

4.0
GMIN = 1
3.5 GMIN = 10
Time (s)

GMIN = 1
GMIN = 100
3.0 GMIN = 10
GMIN = 100
2.5
20
2.0
Outp

1.5
1.0
0.5
0.0 100
0 50 100 150 200 250 1 10
Time (s) Normalized Gain; GDM/GMIN

FIGURE 2-88: Differential Input Overdrive FIGURE 2-91: Output Overdrive Recovery
Recovery vs. Time. Time vs. Normalized Gain.

2014 Microchip Technology Inc. DS20005318A-page 33

2.0
oltage (V)

VL = 0V
1.8
1.6
1.4
utput Vo

GMIN = 1
1.2 GMIN = 10
GMIN = 100
1.0
ply, Ou

0.8
On
06
0.6 VDD
er Supp

0.4 VOUT
02
0.2
Powe

0.0
Off Off
-0.2
02
0 20 40 60 80 100 120 140 160 180 200
Time (ms)
FIGURE 2-92: Power Supply On and Off
and Output Voltage vs. Time.

DS20005318A-page 34 2014 Microchip Technology Inc.

2.6 Enable Response

2.0 50
VDD = 1.8V
1.8 VL = 0V 45 VDD = 1.8V GMIN = 1
ges (V))

Enable Turn-On Time (s)

1.6 GMIN = 10
40 GMIN = 100
INA INA
1.4 turns on turns off 35
t Voltag

1.2
30
1.0 EN VOUT
nable, Output

25
0.8 VDD = 5.5V
20
GMIN = 100
O

0.6
GMIN = 10 15
0.4 GMIN = 1 GMIN = 1
02
0.2 10 GMIN = 10
En

5 GMIN = 100
0.0
-0.2
02 0
0 20 40 60 80 100 120 140 160 180 200 -50 -25 0 25 50 75 100 125
Time (s) Ambient Temperature (C)

FIGURE 2-93: Enable and Output Voltages FIGURE 2-96: Enable Turn-On Time vs.
vs. Time, with VDD = 1.8V. Ambient Temperature.

6.0 2.5
VDD = 5.5V EN = 0V
5.5 VL = 0V 2.0
ges (V))

5.0
1.5
ply Current
4.5
INA INA

A)
t Voltag

10
1.0
own (A
40
4.0 turns on turns off IDD
3.5 0.5 -40C
3.0 +25 C
+25C
nable, Output

Powerr Supp
In Shutdo

0.0
2.5 EN +85C
VOUT -0.5 +125C
2.0
O

ISS
S

1.5 -1.0
1.0 GMIN = 1
GMIN = 10 -1.5
En

0.5 GMIN = 100

0.0 -2.0
-0.5
05 -2.5
25
0 20 40 60 80 100 120 140 160 180 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Time (s) Power Supply Voltage (V)
FIGURE 2-94: Enable and Output Voltages FIGURE 2-97: Power Supply Current in
vs. Time, with VDD = 5.5V. Shutdown vs. Power Supply Voltage.

0.7 1.E-7
100n
V/V)

VIH_TRIP/VDD VDD = 1.8V EN = 0V

VDD = 5.5V
ages (V

06
0.6
ent (A))
Normallized Enable Input

1.E-8
10n
+125C
05
0.5
steresiis Volta

e Curre

VIL_TRIP/VDD
0.4 1.E-9
1n
+85C
utput Leakage

0.3
VHYST/VDD 1.E-10
100p
and Hys

0.2
1.E-11
10p
p
N

Ou
Trip a

0.1 +25C
VDD = 5.5V
00
0.0 1.E-12
1 E 12
1p
-50 -25 0 25 50 75 100 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Ambient Temperature (C) Output Voltage (V)
FIGURE 2-95: Normalized Enable Input FIGURE 2-98: Output Leakage Current in
Trip and Hysteresis Voltages vs. Ambient Shutdown vs. Output Voltage.
Temperature.

2014 Microchip Technology Inc. DS20005318A-page 35

MCP6N16
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP6N16
Symbol Description
MSOP DFN
1 1 EN Enable Input
2 2 VIM Inverting Input
3 3 VIP Non-inverting Input
4 4 VSS Negative Power Supply
5 5 VREF Reference Input
6 6 VFG Feedback Input
7 7 VOUT Output
8 8 VDD Positive Power Supply
9 EP Exposed Thermal Pad (EP); must be connected to VSS.

3.1 Digital Enable Input (EN) 3.5 Analog Feedback Input (VFG)
This input (EN) is a CMOS, Schmitt-triggered input. The analog feedback input (VFG) is the inverting input
When it is low, it puts the part in a low-power state. of the second input stage. The external feedback
When high, the part operates normally. The EN pin components (RF and RG) are connected to this pin. It is
must not be left floating. a high-impedance CMOS input with low bias current.

3.2 Analog Signal Inputs (VIP, VIM) 3.6 Analog Output (VOUT)
The non-inverting and inverting inputs (VIP and VIM) are The analog output (VOUT) is a low impedance voltage
high-impedance CMOS inputs with low bias currents. output. It represents the differential input voltage
(VDM = VIP VIM), with gain GDM and is shifted by
3.3 Power Supply Pins (VSS, VDD) VREF. The external feedback resistor (RF) is connected
to this pin.
The positive power supply (VDD) is 1.8V to 5.5V higher
than the negative power supply (VSS). For normal 3.7 Exposed Thermal Pad (EP)
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive) There is an internal connection between the exposed
supply configuration. In this case, VSS is connected to thermal pad (EP) and the VSS pin; they must be
ground and VDD is connected to the supply; VDD will connected to the same potential on the printed circuit
need bypass capacitors. board (PCB).
This pad can be connected to a PCB ground (VSS)
3.4 Analog Reference Input (VREF) plane region to provide a larger heat sink. This
improves the package thermal resistance (JA).
The analog reference input (VREF) is the non-inverting
input of the second input stage; it shifts VOUT to its
desired range. The external gain resistor (RG) is
connected to this pin. It is a high-impedance CMOS
input with low bias current.

DS20005318A-page 36 2014 Microchip Technology Inc.

MCP6N16
4.0 APPLICATIONS EQUATION 4-2:
The MCP6N16 instrumentation amplifier (INA) is VIP = V CM + VDM 2
manufactured using Microchips state of the art CMOS V IM = V CM V DM 2
process. Its low cost, low power and high speed make V CM = VIP + VIM 2
it ideal for battery-powered applications.
VDM = V IP V IM
4.1 Basic Performance
The negative feedback loop includes GM2, RM4, RF and
4.1.1 STANDARD CIRCUIT RG. These blocks set the DC open-loop gain (AOL) and
the nominal differential gain (GDM):
Figure 4-1 shows the standard circuit configuration for
these INAs. When the inputs and output are in their
specified ranges, the output voltage is approximately: EQUATION 4-3:
A OL = G M2 RM4
EQUATION 4-1: G DM = 1 + RF R G
VOUT VREF + GDMVDM
Where: AOL is very high, so I4 is very small and I1 + I2 0. This
makes the differential inputs to GM1 and GM2 equal in
GDM = 1 + RF / RG
magnitude and opposite in polarity. Ideally, this gives:

EQUATION 4-4:
VDD U1
V FG VREF = VDM
VIP MCP6N16 V OUT = V DM GDM + V REF
VOUT
VIM RF For an ideal part, changing VCM, VSS or VDD produces
VFG
no change in VOUT. VREF shifts VOUT as needed.
The different GMIN options change GM1, GM2 and the
RG
internal compensation capacitor. This results in the
VREF performance trade-offs shown in Table 1.
FIGURE 4-1: Standard Circuit. 4.1.3 DC ERRORS
For normal operation, keep: Section 1.5 Explanation of DC Error
VIP, VIM, VREF and VFG between VIVL and VIVH Specifications defines some of the DC error
VIP VIM (i.e., VDM) between VDML and VDMH specifications. These errors are internal to the INA, and
can be summarized as follows:
VOUT between VOL and VOH

4.1.2 ANALOG ARCHITECTURE EQUATION 4-5:

Figure 4-2 shows the block diagram for these INAs, V OUT = V REF + G DM 1 + g E V DM + V ED
without details on chopper-stabilized operation. + G DM 1 + g E V E + VE
Where:
V DD VSS V CM VREF
VDD VSS EN RM4
VE = V OS + --------------------------------- + ----------------- + --------------------
VOUT PSRR CMRR CMRR2
VOUT
I4 V OUT
+ ----------------- + T A TC 1
VIP RF A OL
VIP GM1 GM2 V
FG
VED INLDM V DMH V DML

VIM I1 I2 RG VE INLCM V IVH VIVL
VIM
VREF Where:
MCP6N16 RR VREF
PSRR, CMRR, CMRR2 and AOL are in
FIGURE 4-2: MCP6N16 Block Diagram. units of V/V

The input signal is applied to GM1. Equation 4-2 shows TA is in units of C

the relationships between the input voltages (VIP and TC1 is in units of V/C
VIM) and the common mode and differential voltages VDM = 0
(VCM and VDM).

2014 Microchip Technology Inc. DS20005318A-page 37

MCP6N16
The nonlinearity specifications (INLCM and INLDM) EQUATION 4-8:
describe errors that are nonlinear functions of VCM and
V REF = I BR R R = I B2 + I OS2 2 R R
VDM, respectively. They give the maximum excursion
from linear response over the entire common mode V FG VREF due to high AOL
and differential ranges. V OUT I B2 RF G DM R R + IOS2 R F + GDM R R 2
The input bias current and offset current specifications Where:
(IB and IOS), together with a circuits external input IB2 meets the IB specification
resistances, give an additional DC error. Figure 4-3 IOS2 meets the IOS specification
shows the resistors that set the DC bias point. IB2 IB, in general
IOS2 IOS, in general

IBP VDD U1
RIP The change in VREF (VREF) can affect the input range,
VIP MCP6N16 for large RR or RF. The best design results when
GDMRR and RF are equal (i.e., RR = RF||RG) and small:
VOUT
VIM IBF RF EQUATION 4-9:
IBM RIM
VFG V OUT 2I B2 RTOL + IOS2 RF
RR Where:
IBR RG
GDMRR = RF
VREF
RTOL = tolerance of RR, RF and RG
FIGURE 4-3: DC Bias Resistors.
The resistors at the main input (RIP and RIM) and its 4.1.4 AC PERFORMANCE
input bias currents (IBP and IBM) give the following
The bandwidth of these amplifiers depends on GDM
changes in the INAs bias voltages:
and GMIN:

EQUATION 4-6:
EQUATION 4-10:
VIP = I BP R IP = I B + I OS 2 R IP
f BW fGBWP G DM
VIM = IBM R IM = I B IOS 2 R IM
0.50 MHz G MIN G DM , GMIN = 1, 10
VCM = V IP + V IM 2
0.35 MHz G MIN G DM , GMIN = 100
= I B RIP + R IM 2 I OS R IP R IM 4
Where:
VDM = V IP V IM
fBW = -3 dB bandwidth
= IB RIP RIM I OS R IP + R IM 2
VOUT = G DM V DM + V CM CMRR fGBWP = Gain-Bandwidth product
Where:
The bandwidth at the maximum output swing is called
CMRR is in units of V/V the Full Power Bandwidth (fFPBW). It is limited by the
Slew Rate (SR) for many amplifiers, but is close to fBW
The change in VCM (VCM) can affect the input range, for these parts:
for large RIP or RIM. The best design results when RIP
and RIM are equal and small:
EQUATION 4-11:
EQUATION 4-7: f FPBW SR V O
fBW , for these parts
V OUT G DM V DM
Where:
G DM 2I B RTOL I OS R IP
VO = Maximum output voltage swing
Where:
VOH VOL
RIP = RIM
RTOL = tolerance of RIP and RIM

The resistors at the feedback input (RR, RF and RG)

and its input bias currents (IBR and IBF) give the
following changes in the INAs bias voltages:

DS20005318A-page 38 2014 Microchip Technology Inc.

MCP6N16
4.1.5 NOISE PERFORMANCE 4.2 Overview of Zero-Drift Operation
As shown in Figure 2-73, the noise density is white at Figure 4-4 shows a simplified diagram of the MCP6N16
low frequencies; the 1/f noise is negligible for almost all zero-drift INAs. This diagram will be used to explain
applications. As a result, the time domain data in how low voltage errors are reduced in this architecture
Figures 2-77, 2-78 and 2-79 is well behaved. (much better VOS, TC1 (VOS/TA), CMRR, CMRR2,
PSRR, AOL and 1/f noise).

VIP

VIM GM1

Chopper Chopper
GA1 Low-Pass
Input Output
Filter
Switches Switches

RM4 VOUT

Chopper POR Digital Control

Input GA2
Switches
Oscillator
VREF
GM2
VFG

FIGURE 4-4: Simplified Zero-Drift INA Functional Diagram.

4.2.1 BUILDING BLOCKS 4.2.2 CHOPPING ACTION

The Main Amplifiers (GM1 and GM2) are designed for Figure 4-5 shows the amplifier connections for the first
high gain and bandwidth, with a differential topology. phase of the Chopping Clock and Figure 4-6 shows
The main input pairs (+ and - pins at the top left) are for them for the second phase. The slow voltage errors
the higher frequency portion of the input signal. The alternate in polarity, making the average error small.
auxiliary input pair (+ and - pins at the bottom left of
GM1) is for the low frequency portion of the input signal VIP
and corrects the INAs input offset voltage. Both inputs
are added together internally.
VIM
The Auxiliary Amplifiers (GA1 and GA2), the Chopper
Input Switches and the Chopper Output Switches
provide a high DC gain to the input signal. DC errors GA1
are modulated to higher frequencies and white noise to
low frequencies. Low-Pass
Filter
The Low-Pass Filter reduces high-frequency content,
including harmonics of the Chopping Clock.
The Output Buffer (RM4) converts current to voltage
and drives external loads at the VOUT pin. GA2
The Oscillator runs at fCLK = 200 kHz. Its output is
divided by 8, to produce the Chopping Clock rate of VREF
fCHOP = 25 kHz.
The internal POR part starts the part in a known good
VFG
state, protecting against power supply brown-outs. The
Digital Control block outputs clocks and POR events. FIGURE 4-5: First Chopping Clock Phase;
Simplified Diagram.

2014 Microchip Technology Inc. DS20005318A-page 39

MCP6N16
4.3 Other Functional Blocks
VIP
4.3.1 RAIL-TO-RAIL INPUTS
VIM Each input stage uses one PMOS differential pair at the
input. The output of each differential pair is processed
using current mode circuitry. The inputs show no
GA1 crossover distortion vs. common mode voltage.
Low-Pass With this topology, the inputs (VIP and VIM) operate
Filter normally down to VSS 0.15V and up to VDD + 0.15V
at room temperature (see Figure 2-52). The input offset
voltage (VOS) is measured at VCM = VSS 0.15V and
VDD + 0.15V (at +25C) to ensure proper operation.
GA2
4.3.1.1 Phase Reversal
VREF The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-82 shows an input voltage
VFG exceeding both supplies with no phase inversion.
FIGURE 4-6: Second Chopping Clock The input devices also do not exhibit phase inversion
Phase; Simplified Diagram. when the differential input voltage exceeds its limits;
see Figure 2-83.
4.2.3 INTERMODULATION DISTORTION
(IMD) 4.3.1.2 Input Voltage Limits
These INAs will show intermodulation distortion (IMD) In order to prevent damage and/or improper operation
products when an AC signal is present. of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1 Absolute Maximum
The signal and clock can be decomposed into sine Ratings ). This requirement is independent of the
wave tones (Fourier series components). These tones current limits discussed later on.
interact with the zero-drift circuitrys nonlinear response
to produce IMD tones at sum and difference The ESD protection on the inputs can be depicted as
frequencies. Each of the square wave clocks shown in Figure 4-7. This structure was chosen to
harmonics has a series of IMD tones centered on it. protect the input transistors against many (but not all)
See Figures 2-75 and 2-76. overvoltage conditions, and to minimize input bias
current (IB).

Bond
VDD
Pad

VIP Bond Input Bond V

IM
Pad Stage Pad
of
INA Input

VSS Bond
Pad

FIGURE 4-7: Simplified Analog Input ESD

Structures.
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages that go too far above VDD; their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
over-voltage (beyond VDD) events. Very fast ESD
events (that meet the specification) are limited so that
damage does not occur.

DS20005318A-page 40 2014 Microchip Technology Inc.

MCP6N16
In some applications, it may be necessary to prevent 4.3.1.4 Input Voltage Ranges
excessive voltages from reaching the INA inputs.
Figure 4-10 shows possible input voltage values
Figure 4-8 shows one approach to protecting these
(VSS = 0V). Lines with a slope of +1 have constant VDM
inputs. D1 and D2 may be small signal silicon diodes,
(e.g., the VDM = 0 line). Lines with a slope of -1 have
Schottky diodes for lower clamping voltages or
constant VCM (e.g., the VCM = VDD/2 line).
diode-connected FETs for low leakage.
For normal operation, VIP and VIM must be kept within
the region surrounded by the thick blue lines. The
VDD horizontal and vertical blue lines show the limits on the
individual inputs. The blue lines with a slope of +1 show
U1 the limits on VDM; the larger GMIN is, the closer they are
D1
V1
MCP6N16 to the VDM = 0 line.
The input voltage range specifications (VIVL and VIVH)
D2 change with the supply voltages (VSS and VDD,
V2 respectively). The differential input range specifications
(VDML and VDMH) change with minimum gain (GMIN).
FIGURE 4-8: Protecting the Analog Inputs Temperature also affects these specifications.
Against High Voltages.
VIP
4.3.1.3 Input Current Limits
VIVH
In order to prevent damage and/or improper operation VDD
of these amplifiers, the circuit must limit the currents

H
M
into the input pins (see Section 1.1 Absolute

D
V
=
Maximum Ratings ). This requirement is

DM
independent of the voltage limits previously discussed.

VC
M
Figure 4-9 shows one approach to protecting these

=
VD
inputs. The resistors R1 and R2 limit the possible

D
/2
current in or out of the input pins (and into D1 and D2).

0
=
The diode currents will dump onto VDD.

L
D

M
V

D
V
=
VIM

DM
VDD

V
0
VIVL
D1 U1
VIVL
0

VDD
VIVH
V1 MCP6N16
R1 D2 FIGURE 4-10: Input Voltage Ranges.
V2 To take full advantage of VDML and VDMH, set VREF
R2 (see Figures 1-7 and 1-8) so that the output (VOUT) is
centered between the supplies (VSS and VDD). Also set
VSS min(V1, V2) the gain (GDM) to keep VOUT within its range.
min(R1, R2) >
2 mA
max(V1, V2) VDD
min(R1, R2) >
2 mA
FIGURE 4-9: Protecting the Analog Inputs
Against High Currents.
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIP and VIM)
should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-47.

2014 Microchip Technology Inc. DS20005318A-page 41

MCP6N16
4.3.2 ENABLE 4.4.3 DC GAIN PLOTS
This input (EN) is a CMOS, Schmitt-triggered input. Figures 2-28 to 2-39 are histograms of the reciprocals
When it is low, it puts the part in a low-power state and (in units of V/V) of CMRR, PSRR and AOL,
the output is put into a high-impedance state. When respectively. They represent the change in input offset
high, the part operates normally. voltage (VOS) with a change in common mode input
If the EN pin is left floating, the amplifier will not operate voltage (VCM), power supply voltage (VDD) and output
properly. voltage (VOUT).
The 1/AOL histogram is centered near 0 V/V because
4.3.3 RAIL-TO-RAIL OUTPUT the measurements are dominated by the INAs input
The Minimum Output Voltage (VOL) and Maximum noise. The negative values shown represent noise and
Output Voltage (VOH) specifications describe the tester limitations, not unstable behavior. Production
widest output swing that can be achieved under the tests make multiple VOS measurements, which
specified load conditions. validates an INA's stability; an unstable part would
show greater VOS variability, or the output would stick
The output can also be limited when VIP or VIM exceeds at one of the supply rails.
VIVL or VIVH or when VDM exceeds VDML or VDMH.
4.4.4 OFFSET AT POWER-UP
4.4 Applications Tips When these parts power up, the input offset (VOS)
starts at its uncorrected value (usually less than
4.4.1 INPUT OFFSET VOLTAGE OVER
10 mV). Circuits with high DC gain can cause the
TEMPERATURE output to reach one of the two rails. In this case, the
Table 1 gives both the linear and quadratic temperature time to a valid output is delayed by an output overdrive
coefficients (TC1 and TC2) of input offset voltage. The time (like tODR), in addition to a start-up time (like tSTR).
input offset voltage can be estimated as follows: It can be simple to avoid this extra start-up time.
Reducing the gain is one method. Adding a capacitor
EQUATION 4-12: across the feedback resistor (RF) is another method.
2
V OS T A = VOS + TC 1 T + TC2 T 4.4.5 SOURCE RESISTANCES
Where:
The input bias currents have two significant
TA = -40C to +125C components: switching glitches that dominate at room
T = TA 25C temperature and below, and input ESD diode leakage
currents that dominate at +85C and above.
VOS(TA) = Input offset voltage at TA
Make the resistances seen by the inputs small and
VOS = Input offset voltage at +25C
equal. This minimizes the output offset caused by the
TC1 = Linear temperature coefficient input bias currents.
TC2 = Quadratic temperature coefficient The inputs should see a resistance on the order of 10
to 1 k at high frequencies (i.e., above 1 MHz). This
These specifications show these INAs intrinsic helps minimize the impact of switching glitches, which
performance. The plots of input offset voltage versus are very fast, on overall performance. In some cases, it
temperature on the second page (Figures 1 to 3) show may be necessary to add resistors in series with the
the typical behavior for a few parts from the first wafer inputs to achieve this improvement in performance.
lot. Small input resistances at the inputs may be needed for
In most designs, other effects will dominate the circuit high gains. Without them, parasitic capacitances might
temperature performance; see Section 4.4.13 PCB cause positive feedback and instability.
Design for DC Precision for more details.
4.4.6 SOURCE CAPACITANCE
4.4.2 NOISE EFFECT ON OFFSET The capacitances seen by the inputs should be small.
VOLTAGE Large input capacitances and source resistances,
The input noise (eni) makes measured offset values together with high gain, can lead to positive feedback
(VOS) vary in a random manner. Lower noise requires and instability.
a lower noise power bandwidth (NPBW; see AN1228,
mentioned in 5.3 Application Notes), which
increases measurement time. In the offset-related
specifications (AOL, CMRR, CMRR2 and PSRR) and
plots, the various values of NPBW were chosen to
trade off time versus accuracy of results.

DS20005318A-page 42 2014 Microchip Technology Inc.

MCP6N16
4.4.7 MINIMUM STABLE GAIN
2k
There are three options for different Minimum Stable
Gains (1, 10 and 100 V/V; see Table 1). The differential

O ()
1k
1,000
gain (GDM) needs to be greater than or equal to GMIN

ded RISO
in order to maintain stability.
Picking a part with higher GMIN has the advantages of

mmend
lower input noise voltage density (eni), lower input

Recom
offset voltage (VOS) and increased gain-bandwidth
product (GBWP). The differential input voltage range
(VDML and VDMH) is lower for higher GMIN, but supports
a reasonable output voltage range. 100
10p
10p
10 100p
100 1n
1,000 10n
10,000
4.4.8 CAPACITIVE LOADS Normalized Load Capacitance; CL GMIN/GDM (F)

Driving large capacitive loads can cause stability FIGURE 4-12: Recommended RISO Values
problems for voltage amplifiers. As the load for Capacitive Loads.
capacitance increases, the feedback loops phase After selecting RISO for the circuit, double check the
margin decreases and the closed-loop bandwidth resulting frequency response peaking and step
reduces. This produces gain peaking in the frequency response overshoot on the bench. Modify RISOs value
response, with overshoot and ringing in the step until the response is reasonable.
response. Lower gains (GDM) exhibit greater sensitivity
to capacitive loads. 4.4.9 GAIN RESISTORS
When driving large capacitive loads with these Figure 4-13 shows a simple gain circuit with the INAs
instrumentation amps (e.g., > 80 pF), a small series input capacitances at the feedback inputs (VREF and
resistor at the output (RISO in Figure 4-11) improves the VFG). These capacitances interact with RG and RF to
feedback loops phase margin (stability) by making the modify the gain at high frequencies. The equivalent
output load resistive at higher frequencies. The capacitance acting in parallel to RG is CG = CDM + CCM
bandwidth will be generally lower than the bandwidth plus any board capacitance in parallel to RG. CG will
with no capacitive load. cause an increase in GDM at high frequencies, which
reduces the phase margin of the feedback loop (i.e.,
reduce the feedback loops stability).
VDD
U1
V1 MCP6N16 RISO VDD
VOUT U1

RF CL
V1 MCP6N16
V2
VFG VOUT
V2 RF
RG VFG
VREF CCM
CCM CDM RG
FIGURE 4-11: Output Resistor, RISO VREF
Stabilizes Large Capacitive Loads.
FIGURE 4-13: Simple Gain Circuit with
Figure 4-12 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the Parasitic Capacitances.
normalized load capacitance (CL GMIN/GDM), where
GDM is the circuits differential gain (1 + RF/RG) and
GMIN is the minimum stable gain.

2014 Microchip Technology Inc. DS20005318A-page 43

MCP6N16
In this data sheet, RF + RG = 10 k for most gains (0 4.4.12 SUPPLY BYPASS
for GDM = 1); see Table 1-6. This choice gives good
With these INAs, the Power Supply pin (VDD for single
phase margin. In general, RF (Figure 4-13) needs to
supply) should have a local bypass capacitor (i.e.,
meet the following limits to maintain stability:
0.01 F to 0.1 F) within 2 mm for good high-frequency
performance. Surface mount, multilayer ceramic
EQUATION 4-13: capacitors, or their equivalent, should be used.
For GDM = 1: These INAs require a bulk capacitor (i.e., 1.0 F or
RF = 0 larger) within 100 mm to provide large, slow currents.
For GDM > 1: This bulk capacitor can be shared with other nearby
G DM
2 analog parts as long as crosstalk through the supplies
R F ------------------------------ does not prove to be a problem.
2 f GBWP C G
Where: 4.4.13 PCB DESIGN FOR DC PRECISION
0.25 In order to achieve DC precision on the order of 1 V,
GDM GMIN many physical errors need to be minimized. The design
of the printed circuit board (PCB), the wiring, and the
fGBWP = Gain-Bandwidth Product
thermal environment have a strong impact on the
CG = CDM + CCM + (PCB stray capacitance) precision achieved. A poor PCB design can easily be
more than 100 times worse than the MCP6N16 op
4.4.10 EMI REJECTION RATIO (EMIRR) amps minimum and maximum specifications.

Electromagnetic interference (EMI) can be coupled to 4.4.13.1 PCB Layout

an INA through electromagnetic induction or radiation,
Any time two dissimilar metals are joined together, a
or by conduction. INAs are most sensitive to EMI at
temperature dependent voltage appears across the
their input pins.
junction (the Seebeck or thermojunction effect). This
EMIRR describes an INAs EMI robustness. Internal effect is used in thermocouples to measure
passive filters in these parts improve the EMIRR, when temperature. The following are examples of
good PCB layout techniques are used. EMIRR is thermojunctions on a PCB:
defined to be:
Components (resistors, INAs, ) soldered to a
copper pad
EQUATION 4-14:
Wires mechanically attached to the PCB
VRF Jumpers
EMIRR dB = 20 log -------------
V OS Solder joints
Where: PCB vias
VRF = Peak Input Voltage of EMI (VPK) Typical thermojunctions have temperature to voltage
VOS = Input Offset Voltage Shift (V) conversion coefficients of 1 to 100 V/C (sometimes
higher).
Microchips AN1258 (Op Amp Precision Design: PCB
4.4.11 REDUCING UNDESIRED NOISE Layout Techniques DS01258) contains in-depth
AND SIGNALS information on PCB layout techniques that minimize
Reduce undesired noise and signals with: thermojunction effects. It also discusses other effects,
such as crosstalk, impedances, mechanical stresses
Low bandwidth signal filters:
and humidity.
- Minimizes random analog noise
- Reduces interfering signals 4.4.13.2 Crosstalk
Good PCB layout techniques: DC crosstalk causes offsets that appear as a larger
- Minimizes crosstalk input offset voltage. Common causes include:
- Minimizes parasitic capacitances and Common mode noise (remote sensors)
inductances that interact with fast switching Ground loops (current return paths)
edges
Power supply coupling
Good power supply design:
Interference from the mains (usually 50 Hz or 60 Hz),
- Isolation from other parts
and other AC sources, can also affect the DC
- Filtering of interference on supply line(s) performance. Nonlinear distortion can convert these
signals to multiple tones, including a DC shift in voltage.

DS20005318A-page 44 2014 Microchip Technology Inc.

MCP6N16
When the signal is sampled by an ADC, these AC 4.5.2 DIFFERENCE AMPLIFIER FOR
signals can also be aliased to DC, causing an apparent VERY LARGE COMMON MODE
shift in offset. SIGNALS
To reduce interference: Figure 4-15 uses the MCP6N16 INA as a difference
- Keep traces and wires as short as possible amplifier for signals with a very large common mode
- Use shielding component. The input resistor dividers (R1 and R2)
ensure that the INAs inputs are within their normal
- Use ground plane (at least a star ground)
range of operation. The capacitors (C1 and C2) set the
- Place the input signal source near to the DUT same voltage division ratio for high-frequency signals
- Use good PCB layout techniques (e.g., a voltage step). C2 includes the INAs CCM. R1
- Use a separate power supply filter (bypass and R2s tolerances affect CMRR.
capacitors) for these zero-drift INAs

4.4.13.3 Miscellaneous Effects V1

R1 R2
Keep the resistances seen by the input pins as small
and as near to equal as possible, to minimize bias VDD U
C1 C2 1
current-related offsets.
MCP6N16
Make the (trace) capacitances seen by the input pins
small and equal. This is helpful in minimizing switching VOUT
glitch-induced offset voltages. RF
C1 C2 VFG
Bending a coax cable with a radius that is too small
causes a small voltage drop to appear on the center
conductor (the triboelectric effect). Make sure the RG
R1 R2
bending radius is large enough to keep the conductors
V2 VREF
and insulation in full contact.
Mechanical stresses can make some capacitor types FIGURE 4-15: Difference Amplifier with
(such as some ceramics) output small voltages. Use Very Large Common Mode Component.
more appropriate capacitor types in the signal path and
minimize mechanical stresses and vibration. 4.5.3 RTD TEMPERATURE SENSOR
Humidity can cause electrochemical potential voltages Figure 4-16 shows an RTD temperature sensor circuit,
to appear in a circuit. Proper PCB cleaning helps, as which measures over the -55C to +155C range. The
does the use of encapsulants. sensor chosen changes from 78 to 159 over this
range. The 2.49 k and 4.99 k resistors set the
4.5 Typical Applications current through the RTD and 68.1 resistor. The INA
provides a high-differential gain. The 10 F capacitor
4.5.1 HIGH INPUT IMPEDANCE filters common mode interference on the bridge.
DIFFERENCE AMPLIFIER
Figure 4-14 shows the MCP6N16 used as a difference VDD
amplifier. The inputs are high-impedance and give
good CMRR performance.
2.49 k 10 F

VDD U1 EN
MCP6N16 4.99 k 4.99 k
VIP MCP6N16-100
VOUT
VOUT
VIM RF 68.1 20 k
VFG RTD
100
4.99 k 100 100
RG
VREF
FIGURE 4-16: RTD Temperature Sensor.
FIGURE 4-14: Difference Amplifier.

2014 Microchip Technology Inc. DS20005318A-page 45

MCP6N16
4.5.4 WHEATSTONE BRIDGE
Figure 4-17 shows the MCP6N16 INA used to
condition the signal from a Wheatstone bridge (e.g.,
strain gage). The overall INA gain is set at 1001 V/V.
The best GMIN option to pick, for this gain, is 100 V/V
(MCP6N16-100).

VDD

RW1 RW2
U1
10 F MCP6N16-100
VOUT
RW2 RW1 RF
VFG 100 k

RN RG
100 100
VREF

FIGURE 4-17: Wheatstone Bridge

Amplifier.

4.5.5 HIGH SIDE CURRENT DETECTOR

Figure 4-18 shows the MCP6N16 INA used to detect
and amplify the high side current in a power supply
design. U1s low offset voltage makes it possible to
reduce RSH, which saves power and minimizes
temperature effects. U1s supply current is included in
the measurement. The INAs gain is set at 101 V/V, so
VOUT changes 1.01V for every 1A change in IDD.

VPS
IDD
IPS
U1
MCP6N16-100
RSH VOUT
10 m RF
VFG 10.0 k
IL
RG
VL 100
VREF

VPS = +1.8V to 5.5V

IPS = IL + IDD
IPS = (VPS VL)/(10 m)
= (VOUT VREF)/((10 m) (101 V/V))

FIGURE 4-18: High Side Current Detector.

DS20005318A-page 46 2014 Microchip Technology Inc.

MCP6N16
5.0 DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP6N16 instrumentation amplifiers.

5.1 Microchip Advanced Part Selector

(MAPS)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design
requirement. Available at no cost from the Microchip
website at www.microchip.com/maps, the MAPS is an
overall selection tool for Microchips product portfolio
that includes Analog, Memory, MCUs and DSCs. Using
this tool, a customer can define a filter to sort features
for a parametric search of devices and export
side-by-side technical comparison reports. Helpful links
are also provided for Data sheets, Purchase and
Sampling of Microchip parts.

5.2 Analog Demonstration Board

Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help customers achieve faster time
to market. For a complete listing of these boards
and their corresponding users guides and technical
information, visit the Microchip web site at
www.microchip.com/analog tools.

5.3 Application Notes

The following Microchip Application Notes are
available on the Microchip web site at
www.microchip.com/appnotes and are recommended
as supplemental reference resources.
AN884: Driving Capacitive Loads With Op
Amps, DS00884
AN990: Analog Sensor Conditioning Circuits
An Overview, DS00990
AN1177: Op Amp Precision Design: DC
Errors, DS01177
AN1228: Op Amp Precision Design: Random
Noise, DS01228
AN1258: Op Amp Precision Design: PCB Layout
Techniques, DS01258
Some of these application notes, and others, are listed
in the design guide:
Signal Chain Design Guide, DS21825

2014 Microchip Technology Inc. DS20005318A-page 47

MCP6N16
6.0 PACKAGING INFORMATION

6.1 Package Marking Information

8-Lead DFN (3x3 mm) Example

Product Number Code

MCP6N16-001E/MF DADV DADV
MCP6N16T-001E/MF DADV 1423
MCP6N16-010E/MF DADW 256
MCP6N16T-010E/MF DADW
MCP6N16-100E/MF DADX
MCP6N16T-100E/MF DADX

8-Lead MSOP (3x3 mm) Example

N16010
423256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week 01)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.