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PERFORMANCE ANALYSIS OF A LOW-POWER HIGH-SPEED HYBRID 1-

BIT FULL ADDER CIRCUIT USING CMOS TECHNOLOGIES USING
CADANCE

Megha R1, Vishwanath B R2

1
Mtech, Department of ECE, Rajeev Institute of Technology, Hassan-573201
2
Assistant Professor, Department of ECE, Rajeev Institute of Technology, Hassan-573201
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ABSTRACT: The general objective of our work is to in the form of 0s and 1s. Addition is the core of many
investigate the power and delay performances of low- other operations like subtraction, multiplication, division
voltage full adder cells in different CMOS logic styles for the and address calculation. In VLSI field, an architecture
predominating tree structured arithmetic circuits. A new called Adder is used to add two or more binary digits.
hybrid style full adder circuit is also presented. The sum and Adder can be either a FA or a HA. This project
carry generation circuits of the proposed full adder are concentrates on FA. Thus the main objective of this project
designed with hybrid logic styles. To operate at ultra-low is enhancing the performance of the available one-bit FA
supply voltage, the pass logic circuit that cogenerates the cell.
intermediate XOR and XNOR outputs has been improved to
over- come the switching delay problem. As full adders The requirement for low-power VLSI systems is constantly
are frequently employed in a tree structured configuration increasing because of the endless applications emerging
for high - performance arithmetic circuits, a cascaded in mobile communication and compact devices. Todays
simulation structure is introduced to evaluate the full adders compact devices are usually battery operated for example,
in a realistic application environment. A systematic and mobile phones, PDAs, which demands VLSI with less
elegant procedure to scale the transistor for minimal power consumption. So designers and developers are
power-delay product is proposed. The circuits being facing more problems regarding high performance,
studied are optimized for energy efficiency at 180nm, rapid speed, low-power consumption and narrow silicon
90nm and 45nm CMOS process technology. With the space. Thus constructing a high performance low-power
proposed simulation environment, it is shown that some adder cells are having enormous importance. Therefore in
survival cells in standalone operation at low voltage may this project, a well-organized approach for understanding
fail when cascaded in a larger circuit, either due to the lack the adder construction and working is given. It is focused
of drivability or unsatisfactory speed of operation. The on splitting the entire FA into several smaller modules.
proposed hybrid full adder exhibits not only the full swing Every single module is constructed, optimized, and
logic and balanced out- puts but also strong output tested individually. Multiple FA cells are formed by joining
drivability. The increase in the transistor count of its these smaller modules.
complementary CMOS output stage is compensated by its
area efficient layout. Therefore, it remains one of the be st FAs, being the most basic building block of all the
contenders for designing large tree structured arithmetic processors, thus remains a key concentration area for the
circuits with reduced energy consumption while keeping the scientists over the years. Distinctive logic styles with their
increase in area to a minimum. In this report the 1-bit own pros and cons were examined to execute 1-bit FA
proposed full adder circuit is designed and also it is also cells.
extended to 4-bits and the results of power and delay were
also tabulated. The outlines, detailed up until this point, might be
comprehensively classied into two classifications:
KeyWords:FA=Full Adder, HA=Half Adder
Static style: Power leakage is measured during the
1. INTRODUCTION Continuous flow of Voltage.

There are four basic arithmetic operations. Addition Dynamic style: Power leakage is measured during the
is one of them. Addition of two or more numbers is switching ON and OFF of a Circuit.
broadly utilized in numerous applications of VLSI, for
example in application-specific DSP architectures and Static FAs are usually more stable, less
microprocessors. The numbers that are added in VLSI complicated with low power demand even though the on-
applications are usually in the form of binary digits that is

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chip area requirement is more in comparison to its

dynamic counterpart. Lengthy interconnections will possibly bring down the
execution in ultra deep submicron process. Thus a
FAs can be constructed using different logics, methodology has been presented in C.H Chang et al.[3],
namely: Standard static complementary metaloxide this paper is used to considerably improve the efficiency in
semiconductor logic (CMOS), dynamic CMOS logic, using silicon area by making the FAs to avoid the cross-
complementary pass-transistor logic (CPL), and stage interconnections as much as possible, without
transmission gate full adder (TGA). disturbing the connectivity in individual stages. In these
designs three outputs from the upper adder stage acts as
Whereas some adders can be constructed by the inputs to the lower adder stage in order to provide
implementing more than one logic style. Such flexibility for redistributing the cells. Due to this feature,
architectures are called hybrid-logic designs. These hybrid the outputs namely sum and carry-out of the FAs are
logic designs makes use of advantageous features of obtained synchronously thus reducing the glitches in the
above mentioned logic styles to enhance the general lower stages.
execution of the FA. Even though this hybrid logic style
offers promising execution, a large portion of these
designs encounter a poor driving capacity which results N. H. E. Westeet.al[4] described that CMOS logic. The
in the definite reduction in their execution in cascaded standard complementary (CMOS) style-based adder
mode of functioning if the reasonably designed buffers are usually consists of 28 transistors. This design shows
excluded. more robustness against transistor sizing voltage scaling
but the design needs high input capacitance and buffers
Hybrid Full Adders are used in the battery-operated thus it prove to be its major disadvantage.
compact gadgets such as Mobile phones, PDAs, and
notebooks which require VLSI, and ULSI designs with a J. M. Rabacyet,al[5] describes the complementary design
better power delay aspects. It is used in the Processor chip to the CMOS FA is the mirror adder, which
like Snap dragon, Intel Pentium for CPU part, which consumes almost same power and consists of same
consists of ALU. This block is used to carry out the number of transistors as of CMOS style but the delay in
operations like addition, subtraction, multiplication etc. the path through which carry propagates within the adder
is generally less in comparison to that of the standard
1.1 Literature Survey CMOS FA.

In computer arithmetic the FAs can be categorized into D. Radhakrishnan[6] and C.H Chang et al.[3] were
two fundamental classes. The first class includes described the CPL Full Adder. CPL consists of 32
Ripple Carry Adders (RCA) and Array Multipliers. These transistors with a better voltage swing. Even though it has
architectures are constructed by arranging the full adders a better voltage swing its not a suitable choice for
in chain where the output of first adder is the input to the applications which requires low power. The major
next adder. Thus in these designs the critical path travels limitations of CPL are regular ON and OFF of
from carry-in of the first FA to the carry-out of the last FA. intermediate nodes, overloading of its inputs, requirement
Here the generation of the carry-out signal should be of more number of transistors and static inverters.
quick otherwise; the late carry-out signal not only
increases the delay but also create more disturbance and
R. Zimmermann et al.[7] and A. M. Shams Et
glitches in the succeeding stages subsequently ending up
consuming more power. al.[8]describes the major limitation of CPL is the voltage
degradation that has been effectively over come in TGA,
The second class includes Wallace Dadda tree multipliers which requires only about 20 transistors for designing
and multiplier-less digital filters were described in P. J. the FA. But the other limitations of CPL like, slow-speed
and more power consumption are always been the major
Song et al.[1] , A. P. Chandrakasan et al.[2] and C. H.
issues to be concentrated. Thus, the researchers came
Chang et al.[3], which forms a tree like architecture. FAs with a more effective approach which includes the
in these architectures forms a tree of few layers to pack the advantageous features of various logic styles in order to
partial products to a carry saved number before a last improve the overall performance of the design called as
carry propagation adder changes over it to a typical binary the Hybrid logic approach.
number. These multiplier designs are proved to be quicker
than its chain structured architectures. However, these
Vesterbacka et al.[9] presented an approach for
tree structured architectures are more complicated
implementing a FA using more than one logic style which
because of their irregular structure and lengthy
employs 14-Transistors.
interconnections. Thus, this unpredictable structure makes
the layout bit complicate and takes wide silicon area.
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Zhang et al.[10]has proposed hybrid pass logic with static

CMOS output drive FA (HPSC). This HPSC circuit uses a
pass transistor logic employing only six transistors where
the XNOR and XOR functions are synchronously
obtained and it is made used in CMOS module so as to get
full swing outputs of the FA but demands more number of
transistors and also decreases the speed. In spite of
the reality that the hybrid logic styles provides good .
performance, but most of these hybrid logic adders
encounter poor driving capability issue and thus their
performance gets corrupted drastically when functioning Fig-1: Schematic structure of proposed full adder
in a cascaded mode without a well designed buffers.
2.1 Altered XNOR-Module
This paper concentrates on the tree structured
architectures for examining the FAs being optimized and In the suggested FA circuit, XNOR-module is in charge of
simulated in the presented tree structure simulation the majority of the power utilization of the whole adder
environment. Another objective is to prolong the life span circuit. Subsequently, this module is intended to limit the
of battery operated compact electronics in order to limit power to the most desirable extend with by passing the
the energy usage per arithmetic operation. Here low voltage degeneration probability.
power consumption does not mean low energy. To
complete any arithmetic operation, a circuit can utilize
very low power by clocking at exceptionally low frequency
but it needs more time to complete the entire operation.
One of the objectives of this project is to study the energy
efficiency of the FAs designed using various logic styles
with a decreasing input voltage in an 180nm technology.
The main aim of this project is to enhance various
specifications such as delay, power and transistor count of
the FA in comparison to the already existing logic styles.

1.2 PROBLEM DEFNITION

The problem being faced is designing of a Hybrid

FA using Cadence virtuoso 180-nm, 90-nm and 45-nm
technology is to reduce delay, area and power of a circuit.
In the literature survey it is evident that the CCMOS logic
utilizes28-Transistors, similarly in the CPL and TGA Logic
uses 32T and 20T. These structures are not suitable for a
suitable choice for low-power applications because of Fig-2: XNOR module.
various limitations as discussed in the literature survey.
The main drawbacks of these structures are voltage The Modified XNOR circuit as demonstrated in a Fig-2 has
degradation in the output voltage levels and slow a power utilization is decreasing remarkably by careful
response, high power utilization and high area occupied. utilization of a weak inverter framed by Mp1 and Mn1
Therefore with the concern on power, area and speed, transistors. Moving faster into the levels of a output signals
design and develop a hybrid full adder structure and is ensured by level restoring of Mp3 and Mn3transistors.
validation of these structure in different technologies that Different topology of XOR/XNOR is already being
is 180nm, 90nm and 45nm using cadence tool. described. The XOR/XNOR utilizes 4Ts at the price of a
low logic swing. Contrarily, the XOR/XNOR described in
2.PROPOSED METHODOLOGY utilizes a 6Ts to obtain preferred logic swing equated to
a 4T XOR/XNOR circuit. Here the XNOR module houses
The suggested FA circuits were prescribed by 3 blocks is 6T, but having distinctive transistor organization than
represented in Fig-1. Module-1 and module-2 were XNOR that of 6T XOR/XNOR. The XNOR circuit introduced in
modules, that will produce a sum signal (SUM) and this work is having a low power and high speed when
module-3 creates the (output carry signal). Each compared with the 6T XOR/XNOR circuit.
module is composed separately with the end goal that the
whole adder circuit is upgraded in terms of power, area
and delay

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by the 2-XNORmodules. The transistors Mp1 and Mn1 of

2.2 Carry Generation Module the inverter will generate B, it is successfully utilized to
plan the controlled inverter utilizing a transistor pair Mp2
The transistors Mp7, Mp8, Mn7, and Mn8 are depicted and Mn2. However, it is having some voltage degeneration
in Fig-3 represents a output carry signal. Through a TGs issue, which is being removed by utilizing a 2 pass
(Mn7 and Mp7), the input carry signal () is being transistors Mp3 and Mn3. pMOS transistors(Mp4, Mp5, and
propagated. This will causes a reduction in a overall carry Mp6) and nMOS transistors (Mn4, Mn5,and Mn6)
propagation path. The intentional utilization of strong TGs comprehend to a second stage XNOR module to form a total
ensured further decrease in propagation delay of a carry Sum operation. Looking at a truth table of a FA, the action
signal. for is being generated and abstracted as follows:

If, A = B, then= B; else=.

The unity between inputs A and B is analyzed by AB

operation. In the event that they are same, at that
point is equal to B, it is achieved by utilizing the TG
acknowledged by transistors Mp8 and Mn8. Contrarily, the
input carry signalis emulated as which is achieved
by other TG comprising of transistors Mp7 and Mn7.

3. PRINCIPLE OF IMPLEMENTING A PROPOSED

FULL ADDER

First design and develop 1-bit proposed full adder

using Cadence virtuoso and check the result in ADEL
. waveform window. 1 bit hybrid Full adder is designed by
Hybridizing (that is combining) XNOR Module and Carry
generation Module using Cadence virtuoso and check the
Fig-3:Carry generation module. result in ADEL waveform window. Validation and the
results were also analyzed for 1 bit hybrid FA of
The CMOS and TGA logic developed a new concept of 180nm, 90nm and 45nm technology using the Cadence
Hybrid Adder in different CMOS technologies using virtuoso tool. The 1 bit hybrid FA circuit is extended to 4-
Cadence and compare the different technology results and bit FA circuit. By using the four 1 bit FAs which is
analyze the Adder performance of the area, power and connected in series. After applying the inputs Validation
delay and the results were also analyzed for 4 bit hybrid FA
of 180nm, 90nm and 45nm technology using Cadence
2.1.1 Operation of the proposed FA. virtuoso tool.

3.1 SPECIFICATIONS ANALYSIS

1) Power Analysis: Power measurement is being one of

a key factor for designing a current VLSI circuits. Overall
power loss includes static and dynamic losses.

=+ (1)

Conflict to early days, as a dynamic power losses

conquered any additional form of power losses, with a
latest move to UDSM level designing; currently static
power losses too have become a major worry.
There are two types of Power losses they are

Static Power loss: Power leakage is calculated

Fig-4: The circuit representation of proposed FA. during the continuous flow of Voltage.

The Fig-4 demonstrates the detail outline of the Dynamic Power loss: Power leakage is calculated
proposed FA. The sum is being a output of a FA is formed during the turning on and off of a circuit.

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2) Delay or Lag Analysis: As a raise in count of inversion 3.4 CIRCUIT IMPLEMENTATION OF 1-BIT PROPOSED
levels in series will lead to a enhancement in lag of a FA OF 90nm TECHNOLOGY
circuit. Interconnect capacitance, junction capacitance,
Inter wire capacitance, intra wire capacitance; each of The Circuit implementation of 1-bit proposed FA of 90nm
these capacitances will matters for the improved delays. technology is as shown in the Schematic Fig-6, which
consist of 16 transistors of 90nm as the minimum possible
= (/) (2) length in 90nm technology. The schematic consist of A, B,
, vdd and gnd as inputs and and Sum as outputs. In
Logical effort(C/I) details for all these factors this circuit module1 and module2 is implemented with
quantitatively. Dynamic circuits were built with the XNOR module to get Sum as the output, but module3 is
purpose to utilize the internal capacitances to grip implemented by carry generation module to get as
some important information which in case of static the output. The nMOS and pMOS will be set to L=100nm
circuits is merely because of delays. These circuits and W=120nm respectively as a default value.
sustained to be very beneficial when fast operation
speeds are essential.

3.2 SIMULATION ANALYSIS

Each circuit is simulated using BSIM 3V3 180nm, 90nm

and 45nm technology on Tanner EDA tool. Every circuits
are being simulated on explicitly similar input patterns
which valid for impartial testing environment. Each
simulation is being operated on a bound of voltages
1.8v,1.2v and 1v for 180nm, 90nm and 45nm
technologies respectively. Schematics of 1 bit FA and 4
bit FA for 180nm, 90nm and 45nm technology were
designed and simulated for the results. Fig-6: Schematic representation of 1-bit proposed full
adder of 90nm technology
3.3 CIRCUIT IMPLEMENTATION OF 1-BIT PROPOSED
FA 3.5 CIRCUIT IMPLEMENTATION OF 1-BIT
PROPOSED FA OF 45nm TECHNOLOGY
The Circuit realization of 1-bit proposed FA of 180nm
technology is as shown in the Schematic Fig-5. The Circuit implementation of 1-bit proposed FA of
45nm technology is as shown in the Schematic Fig-7, which
consist of 16 transistors of 90nm as the minimum possible
length in 45nm technology. The schematic consist of A, B,
, vdd and gnd as inputs and and Sum as outputs. In
this circuit module1 and module2 is implemented with
XNOR module to get Sum as the output, but module3 is
implemented by carry generation module to get as
the output. The nMOS and pMOS will be set to L=45nm and
W=120nm respectively as a default value.

Fig- 5: Schematic representation of 1-bitproposed full

adder of 180nm technology

It includes 16 transistors of 180nm as the minimum

possible length in 180nm technology. The schematic
consist of A, B,, vdd and gnd as inputs and and
Sum as outputs. In this circuit module1 and module2 is
implemented with XNOR module to get Sum as the output,
but module3 is implemented by carry generation module
to get as the output. The nMOS and pMOS will be set
to L=180nm and W=2m respectively as a default value. Fig-7: Schematic representation of 1-bit proposed
full adder of 45nm technology

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3.6 CIRCUIT IMPLEMENTATION OF 4-BIT

PROPOSED FULL ADDER

Till now we have discussed about the 1-bit proposed FA

circuit. By using 1-bit proposed FA circuit we can extend our
design by connecting the full adder circuit in series. The 4-bit
proposed FA circuit is interpreted as shown in the Fig-8 and is
being implemented in 180nm, 90nm and 45nm technologies.
To implement 4-bit proposed full adder circuit, four 1-bit FA
symbols are connected in series with 03(0, 1, 2 , 3),
03(0 , 1 , 2 , 3), , vdd and gnd as input pins, and
03(0, 1, 2 , 3) and 03(0 , 1 , 2, 3) as output pins.
The carry generated in the first 1-bit adder is fed as and the
process repeats till the last adder.

Fig -10: Test Schematic representation of 1-bit proposed

FA circuit of 90nm technology

Fig -8: Schematic representation of 4-bit proposed full

adder of 180nm technology.

4 RESULTS
The Test Schematic representation and output
waveform of 1-bit proposed FA and 4-bit proposed FA is Fig -11: Test Schematic representation of 1-bit proposed
obtained and is shown for different technologies like 180nm, FA circuit of 45nm technology
90nm and 45nm as shown in the figures below

Fig-9: Test Schematic representation of 1-bit proposed FA Fig-12: Transient response of 1-bit proposed FA.
circuit of 180nm technology

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Table -1: Results comparison of power between various

technologies for 1-bit proposed full adder.

Sl.no. Parameters 180nm 90nm 45nm

1 Static Power 43.15 2.342 0.3115

(w)
2 Dynamic 0.6447 892.1 0.09397

Power(nw)
3 Power 43.1506 3.2341 0.31159

dissipation

(w)

Table -2: Results comparison between various technologies

for 1-bit proposed full adder.

Sl.no. Parameters 180nm 90nm 45nm

1 Operating 1.8v 1.2v 1v Fig -13: Test Schematic representation of 4-bit proposed
voltage FA of 180nm technology

2 Power(w) 15.115 0.18315 0.10937

3 Current(A) 8.3975 0.14965 0.10937

4 Transmission 86.39 81.62 25.99

Delay(pS)

5 DC Power (w) 37.39 7.767 5.275

6 Power 12.190 0.8490 0.0709

dissipation
(W)

8 Storage 1-bit 1-bit 1-bit

capacity Fig-14:Transient response of 4-bit proposed FA

9 Hybrid full 16T 16T 16T

adder Table -3: Results comparison of power between various
implementatio technologies for 4-bit proposed full adder.
n
10 Operating 27 C 27 C 27 C
Temperature Sl. Parameters 180nm 90nm 45nm
no
1 Static Power (W) 12.19 0.6259 0.07091

2 Dynamic Power 0.1553 223.1 0.02425

(nW)

3 Power Dissipation 12.190 0.8490 0.0709

(W)

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Table -4: Results comparison between various Finally this method improved scheme is proposed.
technologies for 4-bit proposed full adder. This method compared with different technologies
saves more hardware resources. For the further reduction
of hardware we can perform the ASIC design flow by
Sl.no Parameters 180nm 90nm 45nm doing this we can greatly reduce the number of logics
hence we can reduce the hardware utilization and also we
1 Operating 1.8v 1.2v 1v can reduce the area gate and power.
voltage
4.1 FUTURE WORK
2 Power(w) 27.56623 2.817567 0.07831
2 6827 As a future scope, enhancing the execution of 1 bit
5 FAs can be executed by changing the value of W/L
3 Transmission 112 103.3 92.93 proportions. Utilizing the design of 1 bit proposed FA
Delay(pS) blocks, we can implement a 2 bit, 4 bit, 8 bit, 16 bit, 32 bit,
64 bit Subtractor/Adder circuits. These adders can also be
4 Power 43.1506 3.2341 0.31159
design and differentiate using different possible nm
dissipation
technologies like 180nm, 90nm, 65nm, 32nm, 22nm, and
(w)
so on.

4. CONCLUSIONS REFERENCES

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