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Mustareadafterawritetothesameaddressreturnthenewlywrittendata? Search
Scenario
WhenthereisanAHBwritefollowedbyareadfromthesameaddress,shouldthereadreturntheoldorthe Popular Tags BlogArchives
newdatawhenthereadaddressphaseisinsamecycleofthewritedataphase?
Answer
Theanswertothisquestionisdependentonthedesignoftheslave.
Asimpleslavewillnotbebufferinganydata,sothereturnedreaddatawillbethelatest.Amorecomplex
slavecouldimplementbufferingforwritedata(ifallowedbyHPROT[2])andsoitcould"snoop"thewrite
buffercontentsbeforereturningreaddata,oritmightjustreturnthepreviouslystoreddataregardlessof
whatmightbebuffered.
Inconclusion,alltheAHBspecificationrequiresisthatdataisreturned.

Whatsystemsupportisrequiredifaslavecanbepowereddownorhaveitsclockstopped?
Answer
Ifaslaveaccessisattemptedwhilethatslaveisinapowerdownstateorhashaditsclockstopped,youmust
ensurethatanaccesswillcausethepower/clocktoberestored,orelseconfiguretheAHBdecoderupto
redirectanysuchaccessestothedummyslavesothatthesystemdoesnothangforeverwhenanaccessto
thedeviceismadewhenitisdisabled.
Redirectingtheaccessinthiswaywillensurethatrandom"IDLE"addressesaretreatedwiththeHREADYhigh
andHRESP=OKAYdefaultresponse,butrealaccesses(NONSEQorSEQ)willbedetectedwithanERROR
response.

WhencanEarlyBurstTerminationoccur?
Answer
BurstscanbeearlyterminatedeitherasaresultoftheArbiterremovingtheHGRANTtoamasterpartway
throughaburst,orafteraslavereturnsanonOKAYresponsetoanybeatofaburst.Notehoweverthata
mastercannotdecidetoterminateadefinedlengthburstunlesspromptedtodosobytheArbiterorSlave
responses.
AllAHBMasters,SlavesandArbitersmustbedesignedtosupportEarlyBurstTermination.
CanHTRANSchangewhilstHREADYislow?
Answer
chipguru2011.PoweredbyBlogger.
Ingeneral,anAHBmastershouldnotchangecontrolsignalswhilstHREADYislow.Howeveritisallowableto
changeHTRANSinthefollowingconditions:
HTRANS=IDLE
TheAHBmasterisperforminginternaloperationsandhasnotyetcommittedtoabustransfer.
HoweverduringtheAHBwaitstates(HREADYlow)themastermaydeterminethatabustransferis
requiredandchangeHTRANSonthenextcycletoNONSEQ.
HTRANS=BUSY
HTRANSisbeingusedtogivethemastertimetocompleteinternaloperations,whichmaybe
entirelyindependentofHREADY(i.e.waitstatesontheAHB).ThereforeHTRANScanchangeonthe
nextcycletoanylegalvalue,i.e.SEQiftheburstistocontinue,IDLEifthebursthascompleted,
NONSEQifaseparateburstistobegin.
HRESP=SPLIT/RETRY
AsstatedintheAHBspecification,amastermustassertIDLEonHTRANSduringthesecondcycle
ofthetwocycleSPLITorRETRYslaveresponsesoHTRANSwillchangevaluefromthefirstcycleto
thesecondcycleoftheresponse.
HRESP=ERROR
ThemasterispermittedtochangeHTRANSinreactiontoanERRORresponseinthesamewayasin
 reactiontoaSPLIT/RETRYresponseandcancelanyfurtherbeatsinthecurrentburst(evenif
HBURSTisindicatingadefinedlengthburst).InthiscaseHTRANSchangestoIDLEonthesecond
cycleoftheresponse.Alternatively,themasterispermittedtocontinuewiththecurrenttransfers

CanaBUSYtransferoccurattheendofaburst?
Answer
ABUSYtransfercanonlyoccurattheendofanundefinedlengthburst(INCR).ABUSYtransfercannotoccur
attheendofafixedlengthburst(SINGLE,INCR4,WRAP4,INCR8,WRAP8,INCR16,WRAP16).

Canamasterchangetheaddress/controlsignalsduringawaitedtransfer?
Answer
Yes.Iftheaddress/controlsignalsareindicatinganIDLEtransferthenthemastercanchangetoareal
transfer(NONSEQ)whenHREADYislow.
However,ifamasterisindicatingarealtransfer(NONSEQorSEQ)thenitcannotcancelthisduringawaited
transferunlessitreceivesaSPLIT,RETRYorERRORresponse.

CananAHBmasterbeconnecteddirectlytoanAHBslave?
Answer
AnyslavewhichdoesnotuseSPLITresponsescanbeconnecteddirectlytoanAHBmaster.Iftheslavedoes
useSPLITresponsesthenasimplifiedversionofthearbiterisalsorequired.
IfanAHBmasterisconnecteddirectlytoanAHBslaveitisimportanttoensurethattheslavedrivesHREADY
highduringresetandthattheselectsignalHSELfortheslaveistiedpermanentlyhigh.

DoallslaveshavetosupporttheBUSYtransfertype?
Answer
Yes.AllslavesmustsupporttheBUSYtransfertypetoensuretheyarecompatiblewithanybusmaster.

Doestheaddresshavetobealigned,evenforIDLEtransfers?
Answer
Yes.Theaddressshouldbealignedaccordingtothetransfersize(HSIZE)evenforIDLEtransfers.Thiswill
preventspuriouswarningsfrombusmonitorsusedduringsimulation.

HowmanymasterscantherebeinanAHBsystem?
Answer
TheAHBspecificationcatersforupto16masters.However,allowingforadummybusmastermeansthe
maximumnumberofrealbusmastersisactually15.Byconventionbusmasternumber0isallocatedtothe
dummybusmaster.

IsHREADYaninputoranoutputfromslaves?
Answer
AnAHBslavemusthavetheHREADYsignalasbothaninputandanoutput.
HREADYisrequiredasanoutputfromaslavesothattheslavecanextendthedataphaseofatransfer.
HREADYisalsorequiredasaninputsothattheslavecandeterminewhenthepreviouslyselectedslavehas
completeditsfinaltransferandthefirstdataphasetransferforthisslaveisabouttocommence.
EachAHBSlaveshouldhaveanHREADYoutputsignal(conventionallynamedHREADYOUT)whichisconnected
totheSlavetoMasterMultiplexer.TheoutputofthismultiplexeristheglobalHREADYsignalwhichisrouted
toallmastersontheAHBandisalsofedbacktoallslavesastheHREADYinput.

Isadefaultslavereallynecessary?
Answer
Iftheentire4gigabyteaddressspaceisdefinedthenadefaultslaveisnotrequired.If,however,thereare
undefinedareasinthememorymapthenitisimportanttoensurethataspuriousaccesstoanonexistent
addresslocationwillnotlockupthesystem.Thefunctionalityofthedefaultslaveisextremelysimpleandit
willoftenmakesensetoimplementthiswithinthedecoder.

Isadummymasterreallynecessary?
Answer
AdummymasterisnecessaryinanysystemwhichhasaslavethatcangiveSPLITtransferresponses.The
dummymasterisrequiredsothatsomethingcanbegrantedthebusifalltheothermastershavereceiveda
SPLITresponse.
Nologicisrequiredforthedummymasteranditcanbeimplementedbysimplytyingofftheinputstothe
masteraddress/controlmultiplexerforthedummymasterposition.Therequirementsforadummymasterare
thatHTRANSisdriventoIDLE,HLOCKisdrivenlow,andallothermasteroutputsaredriventolegalvalues.

IsitlegalforamastertochangeHADDRwhenatransferisextended?
Answer
IfamasterisindicatingthatitwantstodoaNONSEQ,SEQorBUSYtransferthenitcannotchangethe
addressduringanextendedtransfer(whenHREADYislow)unlessitreceivesanERROR,RETRYorSPLIT
response.IfthemasterisindicatingthatitwantstodoanIDLEtransferthenitmaychangetheaddress.

IsitspecifiedthatHPROT,HSIZEandHWRITEremainconstantthroughoutaburst?
Answer
Yes,thecontrolsignalsmustremainconstantthroughoutthedurationofaburst.

Thespecificationrecommendsthatonly16waitstatesareused.Whatshouldyoudoifmorethan
16cyclesareneeded?
Answer
Forsomeslavesitisacceptabletoinsertmorethan16waitstates.Forexample,aserialbootROMwhichis
onlyeveraccessedatinitialpowerupcouldinsertalargernumberofwaitstatesanditwouldnotaffectthe
calculationofthesystemperformanceandlatencyoncesystempoweruphasbeencompleted.
Forotherslavesanumberofoptionsexist.ASPLITorRETRYresponsecouldbeusedtoindicatethattheslave
isnotyetabletoperformtherequesteddatatransfer,ortheslavecouldbeaccessedeitherinresponseto
interruptsorafterpollingastatusregister,ineithercaseindicatingthattheslaveisnowabletorespondinan
acceptablenumberofcycles.

Whatarethedifferentburstsusedfor?
Answer
Typicallyamasterwouldusewrappingburstsforcachelinefillswherethemasterwantstoaccessthedatait
requiresfirstandthenitcompletesthebursttofetchtheremainingdataitrequiresforthecachelinefill.
Incrementingburstsareusedbymasters,suchasDMAcontrollers,thatarefillingabufferinmemorywhich
maynotbealignedtoaparticularaddressboundary.

WhatdefaultstateshouldbeusedfortheHREADYandHRESPoutputsfromaslave?
Answer
ItisrecommendedthatthedefaultvalueforHREADYishighandthedefaultvalueforHRESPisOKAY.This
combinationensuresthattheslavewillrespondcorrectlytoIDLEtransferstotheslave,eveniftheslaveisin
someformofpowersavingmode.

Whatisthedifferencebetweenadummybusmasterandadefaultbusmaster?

Answer
Thetermdefaultbusmasterisusedtodescribethemasterthatisgrantedwhennoneofthemastersinthe
systemarerequestingaccesstothebus.Usuallythebusmasterwhichismostlikelytorequestthebusis
madethedefaultmaster.
ThedummybusmasterisamasterwhichonlyperformsIDLEtransfers.Itisrequiredinasystemsothe
arbitercangrantamasterwhichisguaranteednottoperformanyrealtransfers.Thetwocaseswhenthe
arbiterwouldneedtodothisarewhenaSPLITresponseisgiventoalockedtransferandwhenaSPLIT
responseisgivenandallothermastershavealreadybeenSPLIT.

WhatistherecommendeddefaultvalueforHPROT?
Answer
Manybusmasterswillnotbeabletogenerateaccurateprotectioninformationandforthesebusmastersitis
recommendedthattheHPROTencodingshows,Noncacheable,Nonbufferable,Privileged,DataAccesses
whichcorrespondstoHPROT[3:0]=4'b0011.

WhatisthestateoftheAHBsignalsduringreset?
Answer
Thespecificationstatesthatduringresetthebussignalsshouldbeatvalidlevels.Thissimplymeansthatthe
signalsshouldbelogic'0'or'1',butnotHiZ.Theactuallogiclevelsdrivenareleftuptothedesigner.
HTRANSistheonlysignalspecifiedduringreset,withamandatoryvalueofIDLE.
ItisimportantthatHREADYishighduringreset.IfallslavesinthesystemdriveHREADYhighduringreset
thenthiswillensurethatthisisthecase.However,ifslavesareusedwhichdonotdriveHREADYhighduring
resetitshouldbeensuredthataslavewhichdoesdriveHREADYhighisselectedatreset.

Whatsequencesoftransferstypes(HTRANS)canoccuronthebus?
Answer
ThefollowingexamplesshowsomeofthesequencesofHTRANSthatcanoccuronthebus:
AlargeburstoffourtransfersfollowedbyanIDLE.
NSSSI
AlargeburstoffourtransferswhichincludesBUSYtransfers.
NSBSBSI
Aburstoffourtransfersfollowedbyanotherburst.
NSSSNSSSI
Asingletransferfollowedbyaburstoffourtransfers.
NNSSSI
AsingletransferfollowedbyanIDLE
NI
AnundefinedlengthburstwhichconcludeswithaBUSYtransfer.
NBSBSBI
AnundefinedlengthburstwhichconcludeswithaBUSYtransferandisfollowedimmediatelybyanother
burst.
NBSBSBNS

Whenamasterrebuildsaburstwhichhasbeenterminatedearlyarethereanylimitationsonhow
itrebuildstheburst?
Answer
Theonlylimitationisthatthemasteruseslegalburstcombinationstorebuildtheburst.Forexample,ifa
masterwasperformingan8beatburst,buthadonlycompleted3transfersbeforelosingcontrolofthebus,
thentheremaining5transferscouldbeperformedeitherbyusinga1beatSINGLEburstfollowedbya4beat
INCR4burst,oritcouldbeperformedusinga5beatundefinedlengthINCRburst.
ForsimplicityitisrecommendedthatmastersuseINCRburststorebuildtheremainingtransfers.

HowdoestheAHBhandleLOCKedSPLITs?
Answer
WhenatransferisSPLITthearbiterdegrantsandremovestheSPLITmasteroutofthearbitrationuntilthe
slaveindicatesthatthetransfercancomplete.WhenanaccessisLOCKedtheaccesscannotbeinterruptedby
anaccessfromanothermaster.
TheonlypossiblewaythatanAHBsystemcanhandlethesetworequirementssimultaneouslyistogranta
"dummymaster"whentheLOCKedaccessisSPLIT.ThedummymasterwillonlyperformIDLEtransactions,
whichareallowableduringalockedtransfer.TograntanyothermasterwouldviolatetheLOCKprotocol,for
thearbitertoignoretheSPLITwouldviolatetheSPLITprotocolthedummymasteristheonlyoption.
ThedummymasterisalsousedwhenallmastersarehavereceivedaSPLITresponse(thedummymaster
cannotreceiveaSPLITresponse).
Itisrecommendedthatthedesignerofthesplitcapableslave(s)makessurethattheslavemonitorsits
HMASTLOCKinputsothatitdoesn'treturnaSPLITonaLOCKedtransfer,asthisservesnopurpose.

HowmanyclockcyclesshouldtheresetsignalinanAMBAsystembeassertedfor?
Answer
Itisrecommendedthatmasterandslavecomponentsshouldclearlystateiftheyhavearesetrequirement
greaterthan1or2cycles.Itisalsorecommendedthatthesystemdesignshouldholdresetassertedforat
least16cycles,unlessitisknownthatamasterorslavecomponenthasalongerresetrequirement.

IsitlegalforanAHBwrappingbursttobealignedwithrespecttothetotalnumberbytesinthe
burst,suchthatitdoesnotwrap?
Answer
Yes,thisbehavioriscompliantwiththeAHBprotocol.
Considerafourbeatwrappingburstofword(4byte)transfers(whichwillwrapat16byteboundaries).
Ifthestartaddressofthetransferis0x30,thentheburstconsistsoffourtransferstoaddresses0x30,0x34,
0x38,and0x3C.
Again,althoughHBURSTissettoWRAP4,theburstwillnotactuallywrap,whichisallowed.

WhenshouldamasterassertanddeasserttheHLOCKsignalforalockedtransfer?
Answer
TheHLOCKsignalmustbeassertedatleastonecyclebeforethestartoftheaddressphaseofalocked
transfer.ThisisrequiredsothatthearbitercansampletheHLOCKsignalashighatthestartoftheaddress
phase.
ThemastershoulddeasserttheHLOCKsignalwhentheaddressphaseofthelasttransferinthelocked
sequencehasstarted.
WhenshouldamasterdeassertitsHBUSREQsignal?
Answer
Foranundefinedlengthburst(INCR)amastermustkeepitsHBUSREQsignalasserteduntilithasstartedthe
addressphaseofthelasttransferintheburst.Thiswillmeanthatifthepenultimatetransferintheburstis
zerowaitstatethenthemastermaybegrantedthebusforanadditionaltransferattheendofanundefined
lengthburst.
ForadefinedlengthburstthemastercandeasserttheHBUSREQsignaloncethemasterhasbeengrantedthe
busforthefirsttransfer.Thiscanbedonebecausethearbiterisabletocountthetransfersintheburstand
keepthemastergranteduntiltheburstcompletes.
HoweveritisnotamandatoryrequirementforanArbitertoallowabursttocomplete,sothemasterwillhave
toreassertHBUSREQiftheArbiterremovesHGRANTbeforethebursthasbeencompleted.

Whenwillthearbitergrantanothermasterafteralockedtransfer?
Answer
Thearbiterwillalwaysgrantthemasteranextratransferattheendofalockedsequence,sothemasteris
guaranteedtoperformonetransferwiththeHMASTLOCKsignallowattheendofthelockedsequence.This
coincideswiththedataphaseofthelasttransferinthelockedsequence.
DuringthistimethearbitercanchangetheHGRANTsignalstoanewbusmaster,butifthedataphaseofthe
lastlockedtransferreceiveseitheraSPLITorRETRYresponsethenthearbiterwilldrivetheHGRANTsignals
toensurethateitherthemasterperformingthelockedsequenceremainsgrantedonthebusforaRETRY
response,ortheDummymasterisgrantedthebusfortheSPLITresponse.

CanamasterdeassertHLOCKduringaburst?
Answer
TheAHBspecificationrequiresthatalladdressphasetimedcontrolsignals(otherthanHADDRandHTRANS)
remainconstantforthedurationofaburst.
AlthoughHLOCKisnotanaddressphasetimedsignal,itdoesdirectlycontroltheHMASTLOCKsignalwhichis
addressphasetimed.
ThereforeHLOCKmustremainhighforthedurationofaburst,andcanonlybedeassertedsuchthatthe
followingHMASTLOCKsignalchangesafterthefinaladdressphaseoftheburst.

CanamasterperformtransfersotherthanIDLEwhenthebuswasgrantedtoit,butnotrequested
bythemaster?
Answer
Yes.AmastercanperformtransfersotherthanIDLEwhenithadnotrequestedthebus.Pleasenotethatin
thiscaseitisstillrecommendedthatthemasterassertsitsrequestsignalsothatthearbiterdoesnotchange
ownershipofthebustoalowerprioritymasterwhilethetransfersareinprogress.

Ifamasteriscurrentlygrantedthebusbydefault,howmanycyclesbeforestartingannonIDLE
transferdoesithavetoassertHBUSREQ?
Answer
None.ItcanstartanonIDLEtransferimmediately.

WhatistherelationshipbetweentheHLOCKsignalandtheHMASTLOCKsignal?
Answer
AtthestartoftheaddressphaseofeverytransferthearbiterwillsampletheHLOCKsignalofthemasterthat
isabouttostartdrivingtheaddressbusandifHLOCKisassertedatthispointthenHMASTLOCKwillbe
assertedbythearbiterforthedurationoftheaddressphaseofthetransfer.

WhencantheHGRANTsignalchange?
Answer
TheHGRANTsignalcanchangeinanycycleandthefollowingcasesarepossible:
ItispossiblethattheHGRANTsignalmaybeassertedandthenremovedbeforethecurrent
transfercompletes.ThisisacceptablebecausetheHGRANTsignalisonlysampledbymasterswhen
HREADYishigh.
Amastercanbegrantedthebuswithoutrequestingit.
Theabovepointalsomeansthatitispossibletobegrantedthebusinthesamecyclethatitis
requested.Thiscanoccurifthemasteriscoincidentallygrantedthebusinthesamecyclethatit
requestsit.

WhyisHADDRsometimesshownasaninputtothearbiter?
Answer
Theaddressbus,HADDR,isnotrequiredasaninputtothearbiterbutinsomesystemdesignsitmaybe
usefultousetheaddressbustodetermineagoodpointtochangeoverbetweenbusmasters.Forexample,
thearbitercouldbedesignedtochangebusownershipwhenaburstoftransfersreachesaquadword
boundary.

Cananarbiterbedesignedtoalwaysallowburststocomplete?
Answer
ASPLIT,RETRYorERRORresponsefromaslavecanalwayscauseabursttobeearlyterminated.Thisis
outwiththecontroloftheArbiterandsomustbesupported.
UndefinedlengthINCRburstscannothavetheirendpointpredicted,sothereisnoefficientwaythatan
Arbiterdesigncanallowthebursttocompletebeforegrantinganothermaster.INCRburstsmustbearbitrated
onacyclebycyclebasis.
DefinedlengthINCRxandWRAPxburstscanhavetheirbeatscounted,andsoallowedtocompletebythe
Arbiter.HoweverbecauseoftheAHBarbitrationsynchronoustiming,thereisnowaytoavoidpossibly
terminatingaburstimmediatelyafterthefirsttransferofthebursthasbeenindicated.
TheArbiteronlyknowsthatadefinedlengthburstisinprogressbysamplingtheHBURSTbus.Howeverthe
firstpointatwhichHBURSTcanbesampledisafterthefirstclockcycleofthefirstburstbeat,bywhichtime
theArbitermayalreadyhavedecidedtograntanothermasterandwillhavechangedtheHGRANToutputs
accordingly.OnlyacombinatorialpathfromHBURSTtoHGRANTwouldallowthebursttobedetectedintimeto
avoidearlyterminationinthisscenario,butcombinatorialpathsintheAHBbusarenotallowed.
Whyistherea1KBrestrictioninAHB?
Answer
The1KBrestrictionyourefertoisnotarestrictiononmaximumslavesizebutaconstraintwithinAHBthat
saysthataburstmustnotcrossa1KBboundary.Thelimitisdesignedtopreventburstscrossingfromone
devicetoanotherandtogiveareasonabletradeoffbetweenburstsizeandefficiency.Inpractise,thismeans
thatamastermustALWAYSbreakaburstthatwouldotherwisecrossthe1KBboundaryandrestartitwitha
nonsequentialtransfer,thus:

Address:0x3F00x3F40x3F80x3FC0x4000x4040x408
Transfer:NSEQSEQSEQSEQNSEQSEQSEQ

What'sthedifferencebetweenretryandsplitinAHB?
Answer

TheSPLITandRETRYresponsesprovideamechanismforslavestoreleasethebuswhentheyareunableto
supplydataforatransferimmediately.Bothmechanismsallowthetransfertofinishonthebusandtherefore
allowahigherprioritymastertogetaccesstothebus.

WhenamasterinitiatesatransactionontheAMBAbus,ifthetargetdetectsthatthetransferwilltakealarge
numberofcyclestoperform,itcanissueaSPLITsignal.Whathappensnowisthatthearbitercangrantthe
bustoothermastersevenbeforetheSPLITtransactioniscomplete.ThemastertowhichtheSPLIThasbeen
issuedhastothenwaitandcompletetheentiretransaction.

Duringtheaddressphaseofatransferthearbitergeneratesatag,orbusmasternumber,onHMASTER[3:0]
whichidentifiesthemasterthatisperformingthetransfer.AnyslaveissuingaSPLITresponsemustbe
capableofindicatingthatitcancompletethetransfer,anditdoesthisbymakinganoteofthemasternumber
ontheHMASTER[3:0]signals.

Later,whentheslavecancompletethetransfer,itassertstheappropriatebit,accordingtothemaster
number,ontheHSPLITx[15:0]signalsfromtheslavetothearbiter.Thearbiterthenusesthisinformationto
unmasktherequestsignalfromthemasterandinduecoursethemasterwillbegrantedaccesstothebusto
retrythetransfer.ThearbitersamplestheHSPLITxbuseverycycleandthereforetheslaveonlyneedsto
asserttheappropriatebitforasinglecycleinorderforthearbitertorecognizeit.

ThebasicstagesofaSPLITtransactionare:
1.Themasterstartsthetransferinanidenticalwaytoanyothertransferand
issuesaddressandcontrolinformation
2.Iftheslaveisabletoprovidedataimmediatelyitmaydoso.Iftheslave
decidesthatitmaytakeanumberofcyclestoobtainthedataitgivesaSPLIT
transferresponse.Duringeverytransferthearbiterbroadcastsanumber,or
tag,showingwhichmasterisusingthebus.Theslavemustrecordthisnumber,
touseittorestartthetransferatalatertime.
3.ThearbitergrantsothermastersuseofthebusandtheactionoftheSPLIT
responseallowsbusmasterhandovertooccur.Ifallothermastershavealso
receivedaSPLITresponsethenthedefaultmasterisgranted.
4.Whentheslaveisreadytocompletethetransferitassertstheappropriatebitof
theHSPLITxbustothearbitertoindicatewhichmastershouldberegranted
accesstothebus.
5.ThearbiterobservestheHSPLITxsignalsoneverycycle,andwhenanybitof
HSPLITxisassertedthearbiterrestoresthepriorityoftheappropriatemaster.
6.Eventuallythearbiterwillgrantthemastersoitcanreattemptthetransfer.This
maynotoccurimmediatelyifahigherprioritymasterisusingthebus.
7.WhenthetransfereventuallytakesplacetheslavefinisheswithanOKAY
transferresponse.

ForaSPLITtransferthearbiterwilladjustthepriorityschemesothatanyother
masterrequestingthebuswillgetaccess,evenifitisalowerpriority.Inorder
foraSPLITtransfertocompletethearbitermustbeinformedwhentheslavehas
thedataavailable.

ForRETRYthearbiterwillcontinuetousethenormalpriorityschemeand
thereforeonlymastershavingahigherprioritywillgainaccesstothebus.
WhatvalueshouldbeusedforHTRANSwhenanAHBmastergetsaRETRY
responsefromaslaveinthemiddleofburst?

WheneveratransferisrestarteditmustuseHTRANSsettoNONSEQandit
mayalsobenecessarytoadjusttheHBURSTinformation(usuallyjustto
indicateINCR).

WhataddressshouldbeonthebusduringtheIDLEcycleafteraSPLITor
RETRY?

Itdoesnotmatterwhataddressisdrivenontothebusduringthiscycle.
Theslaveselectedbythedrivenaddressshouldnottakeanyactionand
mustrespondwithazerowaitstateOKAYresponse.

Inmanycasesitwillbesimplerforthemastertoleavetheaddress
unalteredduringthiscycle,sothatitremainsattheaddressofthenext
transferthatthemasterwishestoperformandonlyinthefollowingcycle
doesthemasterreturntheaddresstothatofthetransferthatmustbe
repeatedbecauseoftheSPLITorRETRYresponse.

Insomedesignsitmaybepossibleforthemastertoreturntheaddressto
thatrequiredtorepeattheprevioustransferduringtheIDLEcycleand
thisbehaviourisalsoperfectlyacceptable.

DoallmastershavetosupportSPLITandRETRY?

Yes.AllmastersmustsupportSPLITandRETRYresponsestoensuretheyare
compatiblewithanybusslave.AmasterwillhandlebothSPLITandRETRY
responsesinanidenticalmanner.

CanaSPLITorRETRYresponsebegivenatanypointduringaburst?

Yes.ASPLIT,RETRYorERRORresponsecanbegivenbyaslavetoany
transferduringaburst.Theslaveisnotrestrictedtoonlygivingthese
responsestothefirsttransfer.

WillamasteralwayslosethebusafteraSPLITresponse?

Yes.AslavemustnotasserttherelevantbitoftheHSPLITbusinthesame
cyclethatitgivestheSPLITresponseandthereforethemasterwillalways
losethebus.
CanaslaveassertHSPLITxinthesamecyclethatitgivesaSPLIT
response?

No.ThespecificationrequiresthatHSPLITxcanonlybeassertedafterthe
slavehasgivenaSPLITresponse.

DoallslaveshavetosupporttheSPLITandRETRYresponses?

No.Aslaveisonlyrequiredtosupporttheresponsetypesthatitneedsto
use.Forexample,asimpleonchipmemoryblockwhichcanrespondtoall
transfersinjustafewwaitstatesdoesnotneedtouseeithertheSPLIT
orRETRYresponses.

CanaslaveusebothSPLITandRETRYresponses?

NormallyaslavewillnotuseboththeSPLITandRETRYresponses.TheSPLIT
responseshouldbeusedbyanyslavethatmaybeaccessedbymanydifferent
mastersatthesametime.TheRETRYresponseisintendedtobeusedby
peripheralsthatareonlyaccessedbyonebusmaster.

ExplainLockTransferinAHB?

Answer
LOCKtellsthearbitertokeepthecurrentmastergranted,SPLITtellsthearbitertograntanothermaster,so
theonlypossibleactionthearbitercantakeforthesecontradictoryrequestsistograntthedummymaster
thatmustexistinanysystemwithSPLITcapableslaves.

ThedummymasterwillonlyperformIDLEtransfers(i.e.nodatatransfers),socannotcorrupttheLOCKed
sequencethatisongoing.

WhentheoriginalslaveisabletocompletetheSPLITtransfer,itwillsignalthistothearbiteronHSPLITand
thearbitercanthenregranttheoriginalmaster,andtheLOCKedsequencecanthencontinue.

HoweverastheslavehasanHMASTLOCKinputtellingitthatthecurrenttransferispartofaLOCKed
sequence,itshouldknowthatthereisnosystemadvantageinreturningaSPLIT.

Soyes,aslavecanreturnaSPLITresponsetoaLOCKedtransfer,andthearbitermustthengrantthedummy
master,buttheslaveshouldusetheHMASTLOCKinputtoseethataSPLITresponseisnotusefulatthistime.

ExplainWrapBoundaryCalculationinAHB?WRAP4,WRAP8,WRAP16?

Answer
WrapboundarydependsonbothHsizeandtheNoofbeats(4,8,16)
"Forwrappingbursts,ifthestartaddressofthetransferisnotalignedtothetotalnumberofbytes
in the burst (size x beats) then the address of the transfers in the burst will wrap when the
boundaryisreached"
Case1:StartAddressis0x4,Wrap4,Hsizeis2.
00000100beat10x4
00001000beat20x8
00001100beat30xc
00000000beat40x0
HereasHsizeis2,itmeans4bytesaretobetransfered.AsitisWrap4noofbeatsare4.Totalnoofbytesis
16(beats*Hsizeinbytes).Therefore4bitalignmentistobedone.
Inbeat3theaddressis00001100.NowasHsizeis2,addressshldbeincrementedby4.
00001100
+00000100

00010000(itiscrossingtheaddressboundary(4bits))
Sowearealigningitto00000000.beat4
Case2:StartAddressis0x4,Wrap4,Hsizeis1.

00000100beat10x4
00000110beat20x6
00000000beat30x0
00000010beat40x2
HereasHsizeis1,itmeans2bytesaretobetransfered.AsitisWrap4noofbeatsare4.Totalnoofbytesis
8(beats*Hsizeinbytes).
Therefore3bitalignmentistobedone.Inbeat2theaddressis00000110.NowasHsizeis1,addressshlould
beincrementedby2.
00000110
+00000010

00001000(itiscrossingtheaddressboundary(3bits).)

Sowearealigningitto00000000.beat3

Case3:StartAddressis0x4,Wrap8,Hsizeis1.

00000100beat10x4
00000110beat20x6
00001000beat30x8
00001010beat40xa
00001100beat50xc
00001110beat60xe
00000000beat70x0
00000010beat80x2

HereasHsizeis1,itmeans2bytesaretobetransfered.
AsitisWrap8noofbeatsare8.
Totalnoofbytesis16(beats*Hsizeinbytes).
Therefore4bitalignmentistobedone.
Inbeat6theaddressis00001110.NowasHsizeis1,addressshldbeincrementedby2.

00001110
+00000010

00010000(itiscrossingtheaddressboundary(4bits)).

Sowearealigningitto00000000.beat7

AnotherWrapBoundryCalculation:
1)converthexaddrtodecimal0x38=56(dec)
2)asitsawordtransfer(4bytes)andWRAP4so4x4=16
3)56/16=3.5
4)takethewholenumberfrompreviouscalculationas3
5)now3x16=48(dec)
6)yourrolloveraddris48(dec)=0x30(hex)!!!

sotheaddressgoesas383c30and34

ExaplainWrapBeatCalulationinAHB?
Answer
FollowingTaskswillGiveInformationAboutWrapBoundaryBeatLocationCalculation

//
//wrap4_beat_info()
//
taskwrap4_beat_info(logic[2:0]hburst,logic[31:0]haddr,logic[2:0]hsize)
if(hsize==3'b010&&hburst==`AHB_WRAP4)
begin
if(haddr[3:2]==2'b00)wrap4_boundry_location=0//NoWrap
elseif(haddr[3:2]==2'b01)wrap4_boundry_location=3//Wrapat3rdBeat
elseif(haddr[3:2]==2'b10)wrap4_boundry_location=2//Wrapat2ndBeat
elseif(haddr[3:2]==2'b11)wrap4_boundry_location=1//Wrapat1stBeat
end
endtask:wrap4_at_info
//
//wrap8_beat_info()
//
taskwrap8_beat_info(logic[2:0]hburst,logic[31:0]haddr,logic[2:0]hsize)
if(hsize==3'b010&&hburst==`AHB_WRAP8)
begin
if(haddr[5:3]==3'b000)wrap8_boundry_location=0
elseif(haddr[5:3]==3'b001)wrap8_boundry_location=7
elseif(haddr[5:3]==3'b010)wrap8_boundry_location=6
elseif(haddr[5:3]==3'b011)wrap8_boundry_location=5
elseif(haddr[5:3]==3'b100)wrap8_boundry_location=4
elseif(haddr[5:3]==3'b101)wrap8_boundry_location=3
elseif(haddr[5:3]==3'b110)wrap8_boundry_location=2
elseif(haddr[5:3]==3'b110)wrap8_boundry_location=1
end
endtask:wrap8_beat_info
//
//wrap16_at_info()
//
taskwrap16_beat_info(logic[2:0]hburst,logic[31:0]haddr,logic[2:0]hsize)
if(hsize==3'b010&&hburst==`AHB_WRAP16)
begin
if(haddr[7:4]==4'b0000)wrap8_boundry_location=0
elseif(haddr[7:4]==4'b0001)wrap8_boundry_location=15
elseif(haddr[7:4]==4'b0010)wrap8_boundry_location=14
elseif(haddr[7:4]==4'b0011)wrap8_boundry_location=13
elseif(haddr[7:4]==4'b0100)wrap8_boundry_location=12
elseif(haddr[7:4]==4'b0101)wrap8_boundry_location=11
elseif(haddr[7:4]==4'b0110)wrap8_boundry_location=10
elseif(haddr[7:4]==4'b0111)wrap8_boundry_location=9
elseif(haddr[7:4]==4'b1000)wrap8_boundry_location=8
elseif(haddr[7:4]==4'b1001)wrap8_boundry_location=7
elseif(haddr[7:4]==4'b1010)wrap8_boundry_location=6
elseif(haddr[7:4]==4'b1011)wrap8_boundry_location=5
elseif(haddr[7:4]==4'b1100)wrap8_boundry_location=4
elseif(haddr[7:4]==4'b1101)wrap8_boundry_location=3
elseif(haddr[7:4]==4'b1110)wrap8_boundry_location=2
elseif(haddr[7:4]==4'b1111)wrap8_boundry_location=1
end
endtask:wrap16_beat_info

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