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Vlsi Design May, 2015

This document contains information about a JNTU examination for the course VLSI Design. It provides 8 questions related to topics in VLSI design. Some of the questions cover: 1) MOSFET fabrication processes like BICMOS, SOI, pMOS, nMOS and CMOS processes. 2) MOSFET device physics concepts like threshold voltage, current equations, and channel length modulation. 3) VLSI design techniques like layout diagrams, stick diagrams, logic families, and delay calculations. 4) VHDL modeling concepts like procedures, concurrent/sequential statements, and modeling styles. The document provides the question number, part, and number of marks allocated for each sub

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0% found this document useful (0 votes)
78 views4 pages

Vlsi Design May, 2015

This document contains information about a JNTU examination for the course VLSI Design. It provides 8 questions related to topics in VLSI design. Some of the questions cover: 1) MOSFET fabrication processes like BICMOS, SOI, pMOS, nMOS and CMOS processes. 2) MOSFET device physics concepts like threshold voltage, current equations, and channel length modulation. 3) VLSI design techniques like layout diagrams, stick diagrams, logic families, and delay calculations. 4) VHDL modeling concepts like procedures, concurrent/sequential statements, and modeling styles. The document provides the question number, part, and number of marks allocated for each sub

Uploaded by

ratnams
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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www.alljntuworld.

in JNTU World

Set No. 1
Code No: R32045 R10
III B.Tech II Semester Regular/Supplementary Examinations, May/June - 2015
VLSI DESIGN
(Comm to ECE, ECM, EIE)
Time: 3 hours Max. Marks: 75
Answer any FIVE Questions
All Questions carry equal marks

ld
*****
1 a) With a neat sketch explain BICMOS fabrication in p-well process and also explain its [8]
operation.
b) What are the advantages of SOI? [7]

2 a) Explain effect of threshold voltage on MOSFET current equations. [8]

or
b) For a CMOS inverter calculates the shift in transfer characteristic curve when n/p ratio is [7]
varied from 1/1 to 10/1.

3 a) What is a stick diagram and explain different symbols used for components in stick diagram. [8]
/
b) Design a layout diagram for pMOS logic Y= (AB+CD) [7]

4 a)
b)
W
What is inverter delay? How delay is calculated for multiple stages.
Two nMOS inverters are cascaded to drive a capacitive load CL = 16 Cg. Calculate the pair
delay in turns of for the inverter indicated in the figure below. What are the ratios of each
inverter?
[7]
[8]
TU

Inverter 1 Inverter 2

LPU = 16 LPU = 2
WPU = 2 WPU = 2
LPd = 2 LPd = 2
WPd = 2 WPd = 8
JN

5 a) Explain clocked CMOS logic, domino logic and n-PCMOS logic. [8]
b) Explain switch logic and its arrangements? [7]
6 a) Draw the typical standard cell structure showing regular-power cell and explain it. [8]
b) Explain the principle of gate arrays. [7]
7 a) What are procedures? How are they used in VHDL? Explain. [8]
b) Give the comparisons of Concurrent and Sequential Statements. [7]
8 a) With the help of a block diagram, explain the stages of compilation, elaboration and [8]
simulation.
b) Describe synthesis of VHDL code with examples. [7]
*****
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JNTU World
www.alljntuworld.in JNTU World

Set No. 2
Code No: R32045 R10
III B.Tech II Semester Regular/Supplementary Examinations, May/June - 2015
VLSI DESIGN
(Comm to ECE, ECM, EIE)
Time: 3 hours Max. Marks: 75
Answer any FIVE Questions
All Questions carry equal marks

ld
*****
1 a) Explain the nMOS enhancement mode fabrication process for different conditions of [8]
Vds?
b) Explain latch up problems in CMOS circuits? [7]

2 a) Explain different forms of pull ups used as load in CMOS and in enhancement and [8]

or
depletion modes of nMOS.
b) An nMOS transistor is operating in active region with the following parameters: [7]
VGS=3.9V,Vtn=1V,W/L=100, nCox=90A/V2. Find ID and RDS.

3 a) What is the need for design rules? Explain different types of design rules. [8]

4
W
b) Draw the stick diagram layout for y= (A.B) +E+ (C.D)

a) What is sheet resistance? Derive the Expression for RS?


b) Calculate the ON resistance from VDD to GND for the nMOS and CMOS inverter
circuits.
[7]

[7]
[8]

5 a) Explain about static, dynamic and domino logics with examples. [8]
b) What are the limitations on scaling in VLSI design? [7]
TU

6 a) Draw the typical architecture of PLA and explain its operation. [8]
b) What are the advantages, disadvantages and applications of PLAs? [7]

7 a) Explain package declaration and package body in VHDL with an example. [8]
b) Bring out the comparisons between VHDL functions and procedures. [7]

8 a) Explain the different styles of modeling in VHDL. Discuss the salient features of them [8]
taking the example of a full adder.
JN

b) Write a short note on Technology Libraries? [7]

*****

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JNTU World
www.alljntuworld.in JNTU World

Code No: R32045 R10 Set No. 3


III B.Tech II Semester Regular/Supplementary Examinations, May/June - 2015
VLSI DESIGN
(Comm to ECE, ECM, EIE)
Time: 3 hours Max. Marks: 75
Answer any FIVE Questions

ld
All Questions carry equal marks
*****
1 a) Elaborate steps in pMOS fabrication process with suitable sketch? [8]
b) Give the steps for single metal CMOS n-well process and additional steps for bipolar [7]
devices.

or
2 a) Clearly explain channel length modulation of the MOSFET. [7]
b) Define threshold voltages of a MOS device and explain its significance. [8]

3 a) Explain 2m Double Metal, Double Poly. CMOS / BiCMOS Rules. [8]

4
b)

a)
b)
W
Design stick diagram for nMOS logic Y= ((A+B).C)/

Explain different interconnect parasitics.


Explain the problem of driving large capacitive loads? How such loads can be
driven?
[7]

[7]
[8]

5 Discuss the limits of scaling. Why scaling is necessary for VLSI circuits? [15]
TU
6 a) With neat schematic explain the architectural building blocks of CPLD? [7]
b) Explain the following terms: [8]
i) LUT ii) CLB iii) IOB iv) Switch matrix

7 a) Discuss the various data types in VHDL with examples. [8]


b) Explain the following with declaration format and an example each: [7]
i) Variable ii) Signal iii) Constant

8 a) List the three styles of modeling a digital system in VHDL. Give the VHDL code for [8]
JN

each of them, with reference to half adder.


b) Explain about synthesis process? [7]
*****

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JNTU World
www.alljntuworld.in JNTU World

Set No. 4
Code No: R32045 R10
III B.Tech II Semester Regular/Supplementary Examinations, May/June - 2015
VLSI DESIGN
(Comm to ECE, ECM, EIE)
Time: 3 hours Max. Marks: 75
Answer any FIVE Questions
All Questions carry equal marks

ld
*****
1 a) Explain the steps in twin-tub process of CMOS fabrication with suitable sketch. [8]
b) What are the advantages of BICMOS process over CMOS technology? [7]

2 a) Derive an equation for transconductance of an n-channel enhancement MOSFET [8]

or
operating in active region.
b) Explain the possibility of using a CMOS inverter as an amplifier. [7]

3 a) Explain 2m CMOS design rules for wires. [8]


/
b) Design a stick diagram for CMOS logic Y= (A+B+C) . [7]

5
a)
b)

a)
W
Explain the model for deviation of time delay.
Two nMOS inverters are cascaded to drive a capacitive load CL=16Cg. Calculate pair
delay Vin to Vout in terms of .

Draw the basic structure of a dynamic CMOS gate and explain.


[7]
[8]

[8]
b) How switch logic can be implemented using Pass Transistors? [7]
TU
6 a) What are FPGAs? Explain the principle and operation. [8]
b) Explain how the pass transistors are used to connect wire segments for the purpose of [7]
FPGA programming.

7 Write short notes on [15]


a) File types b) Drivers c) Statement concurrency d) Attributes

8 a) Explain in brief the evolution of VHDL and mention the capabilities of the language. [8]
b) Explain about simulation process in VHDL. [7]
JN

*****

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JNTU World

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