ECEN474/704: (Analog) VLSI Circuit Design

Fall 2016

Lecture 5: Layout Techniques

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements
Exam1 is on 9/29
It will be in WEB 236C
2:20-3:45PM (10 extra minutes)
Closed book w/ one standard note sheet
8.5x11 front & back
Bring your calculator
Covers material through lecture 5
Previous years exam 1s are posted on the website for
reference
Reference Material
Razavi Chapter 18 & 19

2
Agenda
MOS Fabrication Sequence
CMOS Design Rules
Layout Techniques
Layout Examples

3
ECEN-474-2009 Jose Silva-Martinez

Fundamentals on Layout Techniques:

N-Well CMOS Technologies

P+ N+ P+

N-Well
Substrate is always connected
to the most negative voltage,
and is shared by all N-type
transistors

4
 MOS Fabrication Sequence
[Razavi]

5
 MOS Fabrication Sequence
[Razavi]

6
 MOS Fabrication Sequence
[Razavi]

Front-End
Back-End
A silicide step, where highly
conductive metal is deposited
on the gate and diffusion
regions, reduces transistor
terminal resistance
To prevent potential gate-
source/drain shorting an oxide
spacer is first formed before
silicide deposition
7
 Contact and Metal Fabrication
[Razavi]

8
Transistor Geometries
-based design rules allow a process and feature size-
independent way of setting mask dimensions to scale
Due to complexity of modern processing, not used often today

Minimum drawing feature =

L Assume w.c. mask alignment <0.75
X Relative misalignment between 2
masks is <1.5
AGate W * L
AD, AS W * X
PS , PS W 2 X (3 sides)

X depends on contact size

5 in this example

9
ECEN-474-2009 Jose Silva-Martinez

BASIC SCNA CMOS LAYERS

Physical Layer P-channel MOSFET

N-well Metal 1
CVD Oxide
Drain Source
Silicon Nitride
Poly Gate
Polysilicon Layer 1
p+ Gate Oxide p+
Polysilicon Layer 2 n-well Bulk

P+ Ion Implant p substrate

N+ Ion Implant Bulk

Contact cut to n+/p_

N-channel MOSFET
CVD Oxide
Metal 1 Source
Metal 1
Drain
Via Oxide Cuts Poly Gate
Metal 2
n+ n+
Gate Oxide
Pad Contact (Overglass)
p substrate

Bulk
10
 ECEN-474-2009 Jose Silva-Martinez

X
Design Rule Basics d

X X

Metal

d
n+
n+
Implanted dopants
p, Na p, Na (a) Contact size
(a) Mask definition (b) After annealing Metal
S

Patterning sequence for a doped n+ n+

Minimum width and line. p, Na

spacing
xp
S (b) Side view
Geometry of a contact
cut
Depletion
regions
x
n+ n+
Nd Nd

n+ n+

p, Na (a) Masking (b) Registration

Design tolerance
Depletion regions due to parallel n+ lines
11 Contact spacing rule
 Nselect
Active area border
ECEN-474-2009 Jose Silva-Martinez

Poly gate
Active
W

Nselect Active Gate overhang in MOSFET

layout
n+
n+
p-Substrate
p-Substrate
Poly gate Poly gate

(a) Correct mask sizing (b) Incorrect mask sizing

Formation of n+ regions in an n-channel (a) No overhang (b) With

MOSFET misalignment
Active area border
Effect of misalignment without overhang
Resist
Metal Metal Metal
s

poly
Poly gate
substrate substrate substrate
W

Gate spacing form an (a) Resist pattern (b) Isotropic etch (c) anisotropic etch
n+ edge
Effect12 of misalignment without overhang
ECEN-474-2009 Jose Silva-Martinez

Mask Number Mask Layer

1 NWELL Nselect

Poly
2 ACTIVE Active

W'
W
3 POLY
L'
4 SELECT Side View

5 POLY CONTACT

6 ACTIVE CONTACT

7 METAL1 n+
L
n+

8 VIA FrontView

9 METAL2
Difference between the drawn and physical
10 PAD
values for channel length and the channel
11 POLY2 width

Design Rule Layers

13
ECEN-474-2009 Jose Silva-Martinez

Polysilicon Gate L'

Metal Drain
xox
Polysilicon
Gate
n+ n+ W
Gate Oxide Field
oxide n+ L n+
p substrate (Bulk)
p
Bulk

Structure of a n-channel MOSFET Perspective view of an n-channel

MOSFET

n+/p+ n+/p+ or
Minimum transistor width is set
by minimum diffusion width

Active
Poly
Poly
2 or 3 (check with TA)
contact

Often, we use a use a slightly

contact

larger minimum that is equal

Example of Layout Rules to the contact height (4 in this
example)
14
ECEN-474-2009 Jose Silva-Martinez
N-channel MOSFET P-channel MOSFET
CVD Oxide CVD Oxide
Metal 1 Metal 1
Source Drain Drain Source

Poly Gate Poly Gate

n+ n+ p+ Gate Oxide p+
Gate Oxide
n-well Bulk
p substrate p substrate

Bulk Bulk
Gate
(a) Cross section Gate

Source Drain Drain Source

Bulk Bulk

(b) Circuit symbol

n+ Poly n+
W

(c) Top 15view

 ECEN-474-2009 Jose Silva-Martinez

Stick Diagrams
D
Poly
G
Metal 1
N+/P+
Contact S

(a) Definitions (b) MOSFET

VDD
VDD VDD

Mp Mp In
Mp

Vin Vout
In Out
Out

Mn Mn
Mn

Gnd Gnd

Stick diagrams for the CMOS Inverter

16
 ECEN-474-2009 Jose Silva-Martinez

The CMOS Inverter

VDD
VDD VDD

Mp Mp In
Mp

Vin Vout
In Out
Out

Mn Mn
Mn

Gnd Gnd
Wp

Lp
N-Well
Metal
Metal VDD VDD p+
n+
Lp pFET
pFET

Wp
Metal Out

p+
nFET Poly In

WN
nFET
LN

Metal GND

n+
WN
LN

Basic Inverter Layout Alternate Inverter Layout

17
ECEN-474-2009 Jose Silva-Martinez

Standard Cells: VDD, VSS and output run in Parallel

Metal VDD
pFET

B MpB MpA

Vo

MnB
Out

A MnA
n+
CMOS NAND2 logic gate
A B nFET
Metal GND

Metal VDD

MpA pFET

p+
MpB

Vo Out
A B nFET

MnA MnB

CMOS NOR2 logic gate

A B
Metal GND

18
 ECEN-474-2009 Jose Silva-Martinez

Wide Analog Transistor: Analog techniques

Unacceptable drain and source resistance
Stray resistances in transistor structure
Contacts short the distributed resistance of diffused areas
Most of the current will be shrunk to this side Current is spread

19
ECEN-474-2009 Jose Silva-Martinez

Transistor orientation
Orientation is important in analog circuits for matching purposes

20
 ECEN-474-2009 Jose Silva-Martinez

Stacked Transistors

Wide transistors need to be split

Parallel connection of n elements (n = 4 for this example)
Contact space is shared among transistors
Parasitic capacitances are reduced (important for high speed )
Gate resistance is reduced

Drain

Gate
Source

Note that parasitic capacitors are lesser at the drain

21
ECEN-474-2009 Jose Silva-Martinez

Matched Transistors

Simple layouts are prone to process variations, e.g. VT, KP, Cox
Matched transistors require elaborated layout techniques

M1 M2

Differential pair requiring matched transistors

Process Variations

Drain M1 Drain M2

Source
22
ECEN-474-2009 Jose Silva-Martinez

Interdigitized Layout
Averages the process variations among transistors
Common terminal is like a serpentine

23
ECEN-474-2009 Jose Silva-Martinez

Why Interdigitized?

M1 M2 M2 M1 M1 M2 M2 M1

KP=1 KP2 KP3 KP4 KP5 KP6 KP7 KP8

Process variations are averaged among transistors

KPs for M1:KP1+KP4+KP5+KP8 (Avg=4.5)
M2:KP2+KP3+KP6+KP7 (Avg=4.5)
Technique maybe good for matching dc conditions
Uneven total drain area between M1 and M2. This is undesirable for ac
conditions: capacitors and other parameters may not be equal
A more robust approach is needed (Use dummies if needed !!)
24
 ECEN-474-2009 Jose Silva-Martinez
A method of achieving better capacitive matching :
Using the previous
slide values, we would
have M2 with KP=3.5
and M1 with KP=5.5

Each transistor is split in four equal parts interleaved in two by twos.

So that for one pair of pieces of the same transistor we have currents
flowing in opposite direction.
Transistors have the same source and drain area and perimeters, but
this topology is more susceptible to gradients
25 (not common centroid)
 ECEN-474-2009 Jose Silva-Martinez

Common Centroid Layouts

Usually routing is more complex
CENTROID
3 M1 M2 M1 M2 (complex layout)

M1: 8 transistors
M2 M1 M2 M1 (0,3) (0,1)
2
(1,2) (1,0)
(2,3) (2,1)
(3,2) (3,0)
1 M1 M2 M1 M2
M2: 8 transistors
(0,2) (0,0)
M2 M1 M2 M1 (1,3) (1,1
0 (2,2) (2,0)
(3,3) (3,1)
0 1 2 3

26
ECEN-474-2009 Jose Silva-Martinez

Common Centroid Layouts

Split into parallel connections of even parts
Half of them will have the drain at the right side and half at the left
Be careful how you route the common terminal
Cross talk (effect of distributed capacitors RF applications)!

27
ECEN-474-2009 Jose Silva-Martinez

Many contacts placed close to one another reduces series resistance

and make the surface of metal connection smoother than when we use
only one contact; this prevents microcraks in metal;

Splitting the transistor in a number of equal part connected in parallel

reduces the area of each transistor and so reduces further the parasitic
capacitances, but accuracy might be degraded!

28
 ECEN-474-2009 Jose Silva-Martinez

Integrated Resistors
Highly resistive layers (p+, n+, well or polysilicon)
R defines the resistance of a square of the layer
Accuracy less than 30% L
Current flow t
Resistivity (volumetric
measure of materials
resistive characteristic)
(-cm) W

L
Sheet resistance (measure
of the resistance of a R = /t ( )
uniform film with arbitrary W
thickness t

W R = 2Rcontact + (L/W) R
L
29
ECEN-474-2009 Jose Silva-Martinez

Diffusion resistors

Diffused resistance
p-substrate

Diffused resistance

well resistance

Pinched n-well resistance

30
ECEN-474-2009 Jose Silva-Martinez

Poly Resistors
First polysilicon resistance

First polysilicon resistance with a

well shielding

Second polysilicon resistance

Second polysilicon resistance with a

well shielding

31
ECEN-474-2009 Jose Silva-Martinez

TYPICAL INTEGRATED RESISTORS

L
R 2R cont R W
W L

Type Sheet Accuracy Temperature Voltage

of layer Resistance Coefficient Coefficient
W/0 % ppm/oC ppm/V
n + diff 30 - 50 20 - 40 200 - 1K 50 - 300
p + diff 50 -150 20 - 40 200 - 1K 50 - 300
n - well 2K - 4K 15 - 30 5K 10K
p - well 3K - 6K 15 - 30 5K 10K
pinched n - well 6K - 10K 25 - 40 10K
pinched p - well 9K - 13K 25 - 40 10K
first poly 20 - 40 25 - 40 500 - 1500 20 - 200
second poly 15 - 40 25 - 40 500 - 1500 20 - 200

Special poly sheet resistance for some analog processes might be as high as 1.2 K/
32
 ECEN-474-2009 Jose Silva-Martinez

Large Resistors
In order to implement large resistors :

Use long strips (large L/W)

Use layers with high sheet resistance (bad performances see previous table)
High temperature coefficient and non-linearityt

Layout : rectangular serpentine

L L
R R
W W xj

Estimating the resistance in the

corners can be difficult

33
 ECEN-474-2009 Jose Silva-Martinez

Well-Diffusion Resistor
Example shows two long resistors for K range
Alternatively, serpentine shapes can be used
Noise problems from the body
Substrate bias surrounding the well
Substrate bias between the parallel strips

Dummies

34
 ECEN-474-2009 Jose Silva-Martinez

Factors affecting accuracy :

Plastic packages cause a large pressure on the die (= 800 Atm.). It determines a variation of
the resistivity.

For <100> material the variation is unisotropic, so the minimum is obtained if the resistance
have a 45o orientation. compensated

Temperature :

Temperature gradient on the

chip may produce thermal
induced mismatch.

uncompensated

35
 ECEN-474-2009 Jose Silva-Martinez

Etching

Wet etching : isotropic (undercut effect)

HF for SiO2 ; H3PO4 for Al
x for polysilicon may be 0.2 0.4 m with
standard deviation 0.04 0.08 m.
Reactive ion etching (R.I.E.)(plasma etching
associated to bombardment) : unisotropic.
x for polysilicon is 0.05 m with standard deviation 0.01 m

Boundary :

The etching depends on the

boundary conditions

Use dummy strips

36
ECEN-474-2009 Jose Silva-Martinez

Side diffusion effect : Contribution of endings

Impact of Rcont depends on relative geometry

Side Diffusion widens R Best to always use a resistor W that is at
R is not constant with W least as large as the contact
Interdigitized structure :

37
MOS Capacitors

[Razavi]

One of the most dense capacitors available (fF/um2)

Often used to de-couple DC power supply and bias signals
Capacitor non-linearity can be important if used in the
signal path

38
 Integrated Capacitors
Poly - Diffusion Poly - Poly Metal1 - Poly

[Razavi]
Vertical Metal Sandwich Lateral Metal-Oxide-Metal (MOM)

[Wang]

[Ho]

39
 ECEN-474-2009 Jose Silva-Martinez

Poly1 - Poly2 Capacitor

Poly 2
Poly 1

Area is determined by poly2

Problems
undercut effects
nonuniform dielectric thickness
matching among capacitors

40
ECEN-474-2009 Jose Silva-Martinez

Factor affecting RELATIVE accuracy/matching

Oxide damage
Impurities
ox y
Bias condition
Bias history (for CVD) ox Real Area x
Stress of Poly 2
Temperature
y
t ox
Grow rate
Poly grain size t ox x
L W
Etching ;
L W C
Alignment 1 0.1%
C

2 2 Note, the absolute C may

C r t ox L W
2 2 2

L W
vary as high as 20% due to
C r t
ox process variations
41
ECEN-474-2009 Jose Silva-Martinez

Accuracy of integrated capacitors

Perimeter imperfections effect the total

capacitance:
C = CA A
CA = capacitance per unit area
A = (x-2x)(y- 2y)
= xy - 2xy - 2yx + 4x y y
Assuming that x = y = e
A = xy - 2e(x + y) + 4(e)2
Real Area x
A xy - 2e(x + y) y
Ce = - 2e(x + y) of Poly 2

The relative error is

= Ce/C
= -2e(x + y) / xy x
Then maximize the area and minimize the
perimeter use squares!!!
42
Capacitor Matching
If we want to match the ratio of two caps C1 and C2

C1 C1,ideal 1 e1

C2 C2,ideal 1 e2
To minimize the error in the cap ratio, we need to have
e1=e2. This implies that the Perimeter/Area should be equal.
Generally, we break up both caps C1 and C2 into square unit
caps, Cu

Au xu2

43
Capacitor Matching
If both C1 and C2 are integer multiples of Cu, then simply
use I1 unit caps for C1 and I2 unit caps for C2
C1 I1Cu

C2 I 2Cu

If C1 I1Cu and C2 I 2Cu 1 f Cu , where f is a fraction,

then we want the non - unit cap, Cnu 1 f Cu , to have equal
Perimeter
as a unit cap.
Area
Why is the non - unit cap 1 f Cu ?
Because we don' t want a cap smaller than the unit cap, or bigger
than 2Cu . Overall, we want to use as many unit caps as possible,
but none smaller than Cu .
44
Capacitor Matching
How to size Cnu?
Anu xnu ynu
Define N 1 f
Au xu2
Pnu Pu
For matching
Anu Au
Pnu Anu 2 xnu ynu
N
Pu Au 4 xu
xnu ynu 2 Nxu
Nxu2
From N definition xnu
ynu
Plugging this into the previous expression, we can solve for ynu
2
ynu 2 Nxu ynu Nxu2 0

ynu xu N N 2 N
If you want ynu xnu choose "", ynu xnu choose "-"
45
Capacitor Matching
If C1 I1Cu 1 f1 Cu and C2 I 2Cu 1 f 2 Cu
where N1 1 f1 and N 2 1 f 2

N1xu2 N 2 xu2
xnu1 xnu 2
ynu1 ynu 2

ynu1 xu N1 N 12 N1
ynu 2 xu N 2 N 22 N 2
Although, generally we have the flexibility to size Cu to set
C1 I1Cu

46
 ECEN-474-2009 Jose Silva-Martinez

Common Centroid Capacitor Layout

Unit capacitors are connected in

parallel to form a larger capacitance

Typically the ratio among capacitors

is what matters

The error in one capacitor is

proportional to perimeter-area ratio

Use dummies for better matching

(See Razavi Book, page 752)

47
ECEN-474-2009 Jose Silva-Martinez
Approximate Common Centroid Structure

C1 C2 C3 C4 C5

TC1 TC2 TC3 TC4 TC5

C2 = C1
C3 = 2C1
C4 = 4C1
C5 = 8C1

48
 ECEN-474-2009 Jose Silva-Martinez

Floating Capacitors
Be aware of parasitic capacitors

poly2
Polysilicon-Polysilicon: Bottom plate
CP1 C1 CP2
capacitance is comparable (10-30 %) poly1
with the poly-poly capacitance CP2

substrate
C1
CP1, CP2 are very small (1-5 % of C1)
CP1 CP2 is around 10-50 % of C1
CP2

metal2
Metal1-Metal2: More clean, C1
but the capacitance per
CP1 metal1
micrometer square is smaller. CP2 Thick oxide
Good option for very high
frequency applications ( C~ 0.1- substrate
0.3 pF).
CP2 is very small (1-5 % of C1)

49
ECEN-474-2009 Jose Silva-Martinez

Analog Cell Layout Key Points

Use transistors with the same orientation

Minimize S/D contact area by stacking transistors (to

reduce parasitic capacitance to substrate)

Respect symmetries

Use low resistive paths when current needs to be carried (to

avoid parasitic voltage drops)

Shield critical nodes (to avoid undesired noise injection)

Include guard rings everywhere; e.g. Substrate/well should

not have regions larger than 50 um without guard
protections (latchup issues) 50
 Bipolar Transistors Latchup
Equivalent Circuit
[Razavi]

Potential for parasitic BJTs (Vertical PNP and Lateral NPN) to form a
positive feedback loop circuit
If circuit is triggered, due to current injected into substrate, then a
large current can be drawn through the circuit and cause damage
Important to minimize substrate and well resistance with many
contacts/guard rings
51
ECEN-474-2009 Jose Silva-Martinez

Stacked Layout for Analog Cells

Stack of elements with the same width

Transistors with even number of parts have the source (drain) on both
sides of the stack

Transistors with odd number of parts have the source on one end and the
drain on the other. If matching is critical use dummies

If different transistors share a same node they can be combined in the

same stack to share the area of the same node (less parasitics)

Use superimposed or side by side stacks to integrate the cell

52
 ECEN-474-2009 Jose Silva-Martinez

M1 and M2 must match. Layout is interdigitized

M3 and M4 must match. M6 must be wider by 4*M3
M7 must be 2*M5
Layout is an interconnection of 3 stacks; 2 for NMOS and 1 for PMOS
Capacitor made by poly-poly
Not the best floorplan, but OK

M3 M6 M6 M6 M6 M4
M3 M4

M6 C
M1 M2 M1 M2 M1 M2
M1 M2

M8
M5 M5 M7 M7 M7 M7 M5 M8
M7

Pay attention to your floor plan! It is critical for

minimizing53iterations: Identify the critical elements
ECEN-474-2009 Jose Silva-Martinez

54
ECEN-474-2009 Jose Silva-Martinez

55
ECEN-474-2009 Jose Silva-Martinez

Following slides were provided by some of Dr. Silvas

graduate students.

Special thanks to Fabian Silva-Rivas, Venkata Gadde, Marvin

Onabajo, Cho-Ying Lu, Raghavendra Kulkarni and Jusung Kim

56
 ECEN-474-2009 Jose Silva-Martinez

Figure: Layout of a single stage fully differential

57
amplifier and its CMFB circuit.
1. I/p NMOS diff pair 2. PMOS (Interdigitated) 3. Resistors for VCM 4.Capacitors (Common centroid)
 ECEN-474-2009 Jose Silva-Martinez

Capacitive network
Resistive network (Common centroid)

Fully differential
amplifier

Figure: Layout of a second order Active

58 RC low-pass Filter (Bi-quad)
ECEN-474-2009 Jose Silva-Martinez

3-bit quantizer in Jazz 0.18m CMOS technology

S/H: sample-and-hold circuit that is used to sample the continuous-input signal
Core: contains matched differential pairs and resistors to create accurate reference levels for the analog-to-
digital conversion 59
Latches: store the output bits; provide interface to digital circuitry with rail-to-rail voltage levels
ECEN-474-2009 Jose Silva-Martinez

High-speed D-Flip-Flop in Jazz 0.18m CMOS technology

Resolves a small differential input with 10mV < Vp-p < 150mV in less than 360ps
Provides digital output (differential, rail-to-rail) clocked at 400MHz
The sensitive input stage (1st differential pair) has a60separate analog supply line to isolate it from the noise
on the supply line caused by switching of digital circuitry
ECEN-474-2009 Jose Silva-Martinez

Design example (industrial quality): Simplest OTA

61
ECEN-474-2009 Jose Silva-Martinez

Overall amplifier: Have a look on the

62
guard rings and additional well!
ECEN-474-2009 Jose Silva-Martinez

BIAS: you may be able to see the dummies,

63
symmetry and S/D connections
ECEN-474-2009 Jose Silva-Martinez

From downstairs

Differential pair
64
ECEN-474-2009 Jose Silva-Martinez

65
ECEN-474-2009 Jose Silva-Martinez

Details on the P-type current mirrors

66
ECEN-474-2009 Jose Silva-Martinez

Q-value of Spiral
Inductors in CMOS
Process
Most of the following slides were taken from

Seminar by: Park, Sang Wook

TAMU, 2003

67
 What is Q?
energy stored
Q
average power dissipated

Ls
Q
Simple Inductor Model: Rs

Integrated Spiral Inductor Pi Model

68
ECEN-474-2009 De-Embedding Jose Silva-Martinez

69
 ECEN-474-2009 Jose Silva-Martinez
Equivalent Circuit & Calculation

Cs

9
Q-factor
Port1 Ls Rs Port2 8

6
Cox1 Cox2 5

2
Csub Rsub Csub Rsub 1

0
0 1 2 3 4 5 6
Frequncy (GHz)

Equivalent Circuit Parameter Calculation

70
ECEN-474-2009 Jose Silva-Martinez
Layout & Structure

Metal-6
(thickness=2um)

Metal-5
under path
N : # of Turns
Via-5

R : Radius
Oxide

Substrate

S : Space W : Width
(=1.5um) (=14.5um)

71
ECEN-474-2009 Jose Silva-Martinez
Layout Split 1
Shape & Radius
9
Q-factor
8 NxWxS
square (R=60)
(4.5x15x1.5)
7

5
octagon (R=60)

3
square (R=60)
2 octagon (R=60) square (R=30)
square (R=30)
1
octagon (R=30)
0
0 1 2 3 4 5 6 octagon (R=30)
Frequncy (GHz)

Shape : Octagon > Square

Radius : 60 > 30
72
ECEN-474-2009 Layout Split 2 Jose Silva-Martinez

PGS (Patterned Ground Shield) material

9

8
Q-factor none
NxRxWxS
(4.5x60x15x1.5)
7

6
nwell
5

3
none poly
2 nwell
poly
1
metal1
0
0 1 2 3 4 5 6
metal 1
Frequncy (GHz)

PGS : Poly > Nwell > none > Metal1

73
 ECEN-474-2009 Layout Split 3 Jose Silva-Martinez

GS (Ground Shield) type

9
none
8 Q-factor
NxRxWxS
7 (4.5x60x15x1.5)

poly PGS(wide)
6

4
SGS poly

3
none
2 poly PGS(wide)
nonsal poly SGS
1 nonsal poly PGS nonsal poly SGS
poly PGS
0
0 1 2 3 4 5 6
Frequncy (GHz) poly PGS
GS : Poly PGS > Poly(nonsal) SGS > Poly(nonsal) PGS > none
PGS = patterned ground shield
SGS = solid ground shield
74
ECEN-474-2009 Layout Split 4 Jose Silva-Martinez

Metal Stack
9

8 Q-factor
NxRxWxS
7 (4.5x60x15x1.5)

5
M6
4

3 M 5/6
M6
2 M 5/6
M 4/5/6 M 4/5/6
1
M 3/4/5/6
0
0 1 2 3 4 5 6 M 3/4/5/6
Frequncy (GHz)

Stack : M6 > M5/6 > M4/5/6 > M3/4/5/6

75
 TAMU Mixed-Signal Research Chip
A 10 Gb/s Hybrid ADC-Based Receiver w/ Embedded Analog
and Per-Symbol Dynamically Enabled Digital Equalization
10GS/s asynchronous SAR
ADC with embedded 3-tap FFE
Digital equalizer with 4-tap
FFE and 3-tap DFE
Fabricated in GP 65nm CMOS
BER w/ 36.4dB Loss Channel

A. Shafik et al, A 10Gb/s Hybrid ADC-Based Receiver with Embedded 3-Tap Analog FFE and Dynamically-Enabled Digital Equalization in 65nm
CMOS, ISSCC 2015.
A. Shafik et al, A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization, JSSC 2016. 76
Next Time
Table-Based (gm/ID) Design Examples

77