HEADLINE

HEADLINE Radio-Frequency and Analog/

Mixed-Signal Circuits and Devices
for Wireless Communications
HEADLINE
Modeling the Scaling Limits of Double-Gate MOSFETs
with Physics-Based Compact Short-Channel Models of
Threshold Voltage and Subthreshold Swing

EYEWIRE

ireless communications have evolved from tradi- about 38% of this revenue (more than US$7.5 billion) comes

W tional radio and TV broadcasting to a broad spec-

trum of exciting applications in bidirectional and
interactive communications such as cellular sys-
tem/phones, smart handheld devices, wireless local area net-
works (WLANs), Bluetooth technology, global positioning
from RF and AMS ICs for cellular handsets [1]. The cellular
handset semiconductor market itself represents almost 13% of
the total worldwide semiconductor market. In addition to cellu-
lar handsets, other wireless communication products and sys-
tems, such as those used in cellular infrastructure, WLANs, and
systems (GPSs), broadband satellite communication solutions, satellite communications, will continue to drive the growth of
phased array radio frequency (RF) systems, and other emerging semiconductor revenue for wireless communications.
wireless communication applica- A key factor for continued semi-
tions. RF and analog/mixed-signal conductor market growth in wireless
(AMS) integrated circuits (ICs) are Herbert S. Bennett, Ralf Brederlow, communication applications is the
the critical and enabling elements for Julio Costa, Margaret Huang, advance of RF and AMS ICs and the
the success of these wireless commu- Anthony A. Immorlica, Jr., related very large scale integrated
nications. The demands to bring new circuit (VLSI) technologies. In con-
Jan-Erik Mueller, Marco Racanelli,
and advanced features in various trast to digital VLSI technology, RF
wireless communication products
Charles E. Weitzel, and Bin Zhao and AMS technologies depend on
and systems continue to drive the many very different materials sys-
revenue growth for semiconductors used in wireless communi- tems, some of which are compatible with complementary metal
cation systems. oxide semiconductor (CMOS) processing and others which are
Today, semiconductor revenue for wireless communications not compatible with CMOS processing (e.g., compound semi-
represents a significant portion of the total worldwide semicon- conductor electronics)at least on a single die.
ductor market. Just for cellular handsets, the semiconductor The 2003 International Technology Roadmap for Semicon-
market is estimated at more than US$20 billion in 2003, and ductors (ITRS) [2] recognizes wireless applications enabled by

38 8755-3996/04/$20.00 2004 IEEE IEEE CIRCUITS & DEVICES MAGAZINE NOVEMBER/DECEMBER 2004
RF and AMS devices and circuits as a separate new dom-access memory (DRAM), multiprocessing unit (MPU),
system/technology driver. Moores First Law predicts a dou- and application-specific integrated circuit (ASIC)], the corre-
bling of transistor density about every 1824 months [3] and lation between feature size and circuit performance is weaker
is a major metric for assessing mainstream CMOS logic tech- for analog and RF circuitry. Instead, analog and RF technolo-
nology. In contrast to all other ITRS drivers [dynamic ran- gies have to meet many other technology features and device

ACRONYMS
AA anti aliasing LAN local area network
AD analog-to-digital LDMOS laterally diffused metal oxide
ADC analog to digital converter semiconductor
AGC automatic gain control LF low frequency
AMS analog/mixed signal LMDS local multipoint distribution services
ASIC application-specific integrated circuit LNA low-noise amplifier
BAW bulk acoustic wave MEMS microelectromechanical systems
BiCMOS bipolar-complementary metal oxide semi- MESFET metal semiconductor transistor
conductor MHEMT metamorphic high electron mobility
BVCBO breakdown voltage between collector and transistor
base, emitter open MMIC monolithic microwave integrated circuit
BVCEO breakdown voltage between collector and MOS metal oxide semiconductor
emitter, base open MPU multiprocessing unit
CDMA code division multiple access NF noise figure
CMOS complementary metal oxide semiconductor NMOS n-type channel MOS
CPU computer processing unit PA power amplifier
CV current-voltage PAE power added efficiency
DA digital-to-analog PCS personal communication service
DAC digital to analog converter PDC personal digital cellular
dc direct current PD-SOI partially depleted silicon on insulator
DCS digital cellular system PHEMT pseudomorphic high electron mobility
DECT digital European cordless telephone transistor
DRAM dynamic random-access memory PM power management
DSP digital signal processor Q quality factor
E/D enhancement/depletion RF radio frequency
EDA electronic design automation RFIC radio frequency integrated circuit
f frequency SAT satellite terminal
FBAR film bulk acoustic resonator SAW surface acoustic wave
FD-SOI fully depleted silicon on insulator SiC silicon carbide
FET field effect transistor SiGe silicon germanium
FOM figure of merit SIP system-in-package
Fref reference frequency SOC system-on-chip
Ft transit frequency SOI silicon on insulator
F max maximum frequency of oscillation SS small signal
GaAs gallium arsenide T/R transmit/receive
GaN gallium nitride UWB ultra wideband
GPS global position system VCO voltage controlled oscillator
GSM global system for mobile communications VLSI very large scale integrated circuit
HBT hetero bipolar transistor V voltage
HEMT high electron mobility transistor Vdd drain supply voltage
HFET heterojunction field effect transistor Vdd, analog speed maximum supply voltage for analog speed
HV high voltage device
I current Vth threshold voltage
IP intellectual property W Watt
IC integrated circuit WCDMA wideband code division multiple access
InP indium phosphide WLAN wireless local area network
I/O input/output 3D three dimensional
ISM industrial, scientific, medical frequency 2G second generation wireless network
band (unlincensed) (digital)
ITRS International Technology Roadmap for 3G third generation wireless network
Semiconductors (multimedia)

IEEE CIRCUITS & DEVICES MAGAZINE NOVEMBER/DECEMBER 2004 39

 GaAs
SiGe

CMOS

0.8 GHz 2 GHz 5 GHz 10 GHz 28 GHz 77 GHz 94 GHz

PDC DCS Sat Radio SAT TV Contraband

GSM
GPS PCS 802.11 b/g UWB WLAN WLAN LMDS AUTO Detection
CDMA
DECT HomeRF WiMax 802.11a Hyperlink WLAN RADAR All Weather
ISM
CDMA Bluetooth UWB Landing

1. Application spectrum. (Adapted from Figure 1 in the D. Barlas et al. article in Microwave Journal, page 22, June 1999. Printed with permission.)

parameters that do not scale in the same manner as logic dards. Together, they will determine device needs and even
device metrics [e.g., current-voltage/current (CV/I)] do [4]. the choice of technology.
The most important drivers for wireless communications Figure 2 shows the circuit functions of a typical mobile
systems are cost, available frequency bands, power consump- communication system operating between 0.8 and
tion, functionality, size of mobile units, very high volumes of 10 GHz. These frequencies refer to the operating or carrier
product, appropriate performance requirements, and stan- frequencies of the wireless systems (and not to device corner
dards and protocols. Standards and protocols significantly frequencies or circuit clock frequencies). The four basic cir-
influence parameters such as operating frequency, channel cuit functions shown therein are RF transceiver, AMS, power
bandwidth, and transmit power. Such standards and protocols amplifier (PA) and power management (PM), and digital sig-
impact overall system performance and include regulations nal processor (DSP). In this article, we emphasize the first
from various governments that determine frequency availabil- three circuit functions, which drive analog and RF technology
ity. They often affect advances in RF and AMS technologies needs. The DSP is addressed by other parts of the ITRS
much more than they affect advances in many of the main- roadmap and will not be discussed here. Each of those three
stream CMOS technologies described in the 2003 ITRS. major parts in a RF front-end for a wireless system will be dis-
Figure 1 schematically presents the scope of this article in cussed in a separate section with special emphasis on the
terms of the interplay among commercial wireless communica- device needs and technology choices for those blocks and with
tion applications, available spectrum, and the kinds of elemen- main focus on the frequency range from 0.8 to 10 GHz. A sec-
tal and compound semiconductors likely to be used. tion on millimeter wave circuits and devices will cover device
Developing RF and AMS technologies for such applications is and technology integration issues for applications in the fre-
not straightforward. Cost versus performance is one of the key quency range starting from 10100 GHz. Strictly speaking,
factors determining the location of boundaries between the millimeter wave frequencies begin near 30 and not 10 GHz.
kinds of RF semiconductors (e.g., Si, SiGe, GaAs, and InP) We use 10 GHz for the approximate beginning because the
shown in the top part of Figure 1. These boundaries are broad technical challenges between 10 and 30 GHz from a technolo-
and diffuse, and they change with time and application. Two gy roadmapping perspective are similar. Finally, we will dis-
or more technologies may coexist with one another for cer- cuss the evolution of technology choices, integration issues,
tain applications. This means that we have to address and dis- and potentially new emerging devices, all within the time-
cuss the intersection of Si-based technologies, such as CMOS, frame for the 2003 ITRS roadmap (20032018).
BiCMOS (bipolar and CMOS), and SiGe heterojunction bipo-
lar transistors (HBTs), with III-V compound semiconductors ANALOG AND MIXED-SIGNAL:
and other potential technologies, such as microelectrome- REQUIREMENTS AND CHALLENGES
chanical systems (MEMS), bulk acoustic wave (BAW) devices, Mixed-signal ICs contain analog and digital circuitry. Analog cir-
and passive components. In addition, we must consider the cuitry refers to circuits such as amplifiers or filters for which the
frequency of operation and other criteria such as costs and signals vary continuously. Digital circuitry refers to circuits for
specifications given by the different communication stan- which the signals have two values or states. Mixed-signal circuits

40 IEEE CIRCUITS & DEVICES MAGAZINE NOVEMBER/DECEMBER 2004

or chips often utilize both analog and
digital functions such as analog-to-digi-
tal (AD) and DA conversion. The focus Mixer
of purely analog circuitry is shifting to LNA AA
AGC ADC
Filter
higher and higher frequencies due to the
increasing performance of post-analog VCO

Digital Signal Processor

digital signal processing. However, AD
and DA conversion performance Reference Clock
becomes increasingly important as it ?N I, V, f Tree
fref
opens the door to new high-volume but Analog
low-cost applications. The commodity Signal
driver applications for mixed-signal ICs Driver Processor
are projected to remain in consumer and PA DAC
communication markets where off-chip
interfaces require analog signals. Analog Power
Regulators
devices must often reuse and leverage Control Logic
mainstream digital CMOS technology to
remain low cost and meet the demand 2. Circuit functions of a typical mobile communication system.
for high performance and reliability.
Successful mixed-signal technologies will benefit from main- same dimensions for all parameters would make direct com-
stream digital technologies by integrating more value-added fea- parisons easier. However, because frequency and area are
tures and functions. Key ingredients to successful mixed-signal parameters used by circuit designers, we keep the three differ-
integration are the addition of special higher voltage analog pre- ent dimensions and define three analog margins as follows:
cision transistors, high-quality passive elements, adequate signal 1) the product of supply voltage and mismatch per unit area
isolation, and compatible active devices. Precision transistors 2) the product of supply voltage and 1/f-noise per unit area
have thicker oxides and longer gate lengths compared to stan- 3) the product of supply voltage and thermal noise.
dard digital CMOS transistors and have certain benefits that will The above three margins give three relative numbers that
be discussed later. High-quality passive devices often require relate to the dynamic ranges available in a given technology for
additional processing steps in the back end of the line. low, medium, and high frequencies. These margins depend on
This section includes discussions of analog high-speed circuit topology and designers choice for frequency. Even
devices, analog precision MOS devices, and capacitors and though slightly different parameters are used, the difference
resistors. All devices are optimized for precision, matching between supply voltages and noise levels approximate the trends
performance, 1/f noise, low nonlinearity, and low temperature in the dynamic ranges that are available for analog design at
gradients. The acceleration of the CMOS roadmap in recent each CMOS technology node. Figure 3 shows that the analog
years has hastened the integration possibilities of analog in margins remain approximately constant over technology gener-
logic processes. Continued focus on 1/f noise, passive compo- ations for the case of a constant area occupied by the devices.
nent density, and device matching is imperative to satisfy the Continued circuit performance improvement with scaling
increasing demands on power, speed, and area efficiency. is a demand in analog circuit design, but it is not assured
The change from constant voltage to constant field scaling in from these dynamic performance numbers. Increasing the
the 1990s had consequences for analog scaling. The dynamic device area in many cases results in increasing analog voltage
range of operation for an analog circuit is given by the difference margins, but at the penalty of increasing analog chip area
between the maximum available signal (~ supply voltage) and and/or power consumption. Progress in analog technology is
the minimum detectable signal (determined by noise and distor- achieved by increasing the speed of the devices in new CMOS
tion). Since supply voltages for CMOS tend to decrease with technologies (see Figure 4). Speed is driven by Fmax as shown
each new technology generation, the upper boundary for in Figure 4. Other possible performance tradeoffs are even
dynamic range decreases as well. At least, to maintain a constant overcompensated in this way. A more detailed view on the
dynamic range available for circuit design, noise and distortion interplay of device and circuit performance is given in [5].
have to decrease for each new CMOS technology. Due to the increased available signal swing and the need to
Figure 3 shows the evolution of the supply voltages and reuse analog IP-blocks over two or more technology nodes, a
the most important types of distortion and noise for MOS second, mixed-signal supply voltage for analog precision devices
transistors in circuits for the three different frequency bands is often introduced in the process platform. It normally lags that
of dc, low frequency (LF), and RF at the technology nodes of high-performance digital supply by two or more generations
given in the 2003 ITRS. Here the supply voltage is given in and shows a slightly higher analog margin. A combination of
volts, but some noise numbers are given in volts per square- multiple gate oxide thickness, multiple thresholds, and dcdc
root of frequency, and other noise numbers are given in volts conversion is needed to support the steadily increasing mixed-
per square-root of frequency and per unit area. Having the signal requirements. To accommodate higher voltages, analog

IEEE CIRCUITS & DEVICES MAGAZINE NOVEMBER/DECEMBER 2004 41

 101
Analog Speed
Vdd [V]
Analog Precision
High Vdd [V]
100 Analog Precision
Low Vdd [V]
Vth Mismatch Per
Area, Prec. [Vm]
101 Vth Mismatch Per
Area, Prec. [Vm]
1/f-Noise Per Area,
Voltage [V]

1Hz-1MHz, Speed
[V(m)2(Hz)1/2]
102
1/f-Noise Per Area,
1Hz-1MHz, Prec.
[V(m)2(Hz)1/2]
Thermal Noise,
103 1Hz-10MHz, Speed
[V(Hz)1/2]
Thermal Noise,
1Hz-10MHz, Prec.
104 [V(Hz)1/2]

DC Analog Design Margin

() Prec. () Speed
LF Analog Design Margin
105 () Prec. (+) Speed
RF Analog Design Margin
110 90 80 70 65 57 50 45 40 32 28 22 20 16
() Prec. () Speed
DRAM Pitch - Technology Node [nm] (at Constant Dev. Area)

3. Performance metric of several analog active device parameters from the 2003 ITRS roadmap versus technology node.

precision transistors have thicker gate oxides than standard nal swings at lower supply voltages. An alternative to full ana-
logic transistors have. This use of thicker gate oxides has two log integration is the use of system-in-package (SIP), which
benefits: it continues to support interfaces to the outside world combines circuits from different technologies and is opti-
and simultaneously meets the high signal-to-noise requirements mized for the desired functions.
for mixed-signal applications. The latter are achieved at the The trend of moving discrete passive elements from board
expense of some matching and 1/f noise scaling performance but level to chip level is driven by cost and by demand to reduce
at a slight increase in analog margin, as shown in Figure 3. board space and increase analog design freedom. Alternatively,
Many challenges will arise when trying to achieve technol- some passives may be integrated into the printed board or pack-
ogy integration of the foregoing device features with scaled age as a method of cost reduction and simplification. Finally,
technologies. For low mismatch, circuit design techniques cost-efficient solutions for achieving discrete-equivalent preci-
like active mismatch compensation are already under discus- sion on-chip passive components are expected. Integrated capaci-
sion. Active mismatch compensation is the active calibration tors with new high- dielectrics are needed to reduce their area,
of an analog circuit by adding more calibration circuitry. New mismatch, and distortion properties at a constant leakage cur-
technologies like fully depleted silicon on insulator (FD-SOI) rent. Integrated resistors need low parasitic capacitance and
may relax problems in achieving sufficient matching perfor- high-temperature linearity at a low mismatch and 1/f-noise level.
mance for new technology nodes [6]. The most important parameters for relative accuracy of the
A major challenge for 1/f-noise especially in analog high- devices with respect to available signal swing, which again is
speed devices will be the adoption of high- gate stacks for determined mainly by the supply voltage, are shown in
digital MOS devices, starting with the 65 nm node. Because Figure 5. For capacitors, they include relative device mismatch
interface state density is expected to be strongly enhanced and low integral nonlinearity. The integral nonlinearity relative
here compared to SiO2 gate dielectrics, this will result in to signal swing is given by the product of device nonlinearity in
much higher 1/f-noise for those devices. However, initial ppm/V2 and the supply voltage. For resistors, the most impor-
results for 1/f-noise with high- dielectrics show that this tant parameters include low mismatch and low 1/f-noise.
probably will not be an analog show-stopper [6]. Challenges for passive device integration arise from low cost
Solutions in active threshold regulation, substrate biasing, (low area, low additional mask count) and from the integration of
and novel design architecture will be required to decrease sig- new materials, especially from high- dielectrics for capacitors.

42 IEEE CIRCUITS & DEVICES MAGAZINE NOVEMBER/DECEMBER 2004

 As the integration density increases and the operation fre- most historically analog functions (e.g., most analog filtering)
quency rises, protection of noise-sensitive analog circuits and that digital clock frequencies will increasae with technology
from noisy digital circuits will become increasingly diffi- node except for signal amplification and AD conversion. This
cult. Signal isolation is managed through a combination of trend started in the mid-1990s and will continue with decreas-
substrate (e.g., high resistance), interconnect, and package ing energy consumption per logic operation, decreasing area per
solutions. Today, circuit blocks are protected by oxide isola- function, and increasing parallel processing capabilities of mod-
tion, guard rings, and buried wells (triple wells). Integrated ern digital circuits. Besides analog-related technology improve-
shielding structures may be required for protection of cir- ments, this has been and will continue to be a major driver for
cuits and interconnects in the future. Novel design architec- the success of signal processing applications.
tures may be employed to enhance circuit
signal/noise performance. The introduction of 450
SOIthough positive for signal isolationwill
pose additional challenges for mixed-signal cir- 400 Peak Ft SiGe Bipolar
cuits. Analog device performance for the SOI Peak Fmax
350
process is an area of research. Thermal and float-

Peak Ft, Fmax (GHz)

ing-body effects as well as high-resistive sub- 300
strate connections pose challenges for circuit
250
design. FD-SOI may relax most of the problems
associated with isolated body devices [6]. Howev- 200
er, in contrast to partially depleted (PD)-SOI, we
150
do not even know the detailed electrical behavior RF NMOS
and yield characteristics of those devices in com- 100
plex analog circuits. Finally, any cost-effective
50
solution addressing these problems and chal-
lenges must be compatible with the mainstream 0
CMOS technology of the time. 2002 2003 2004 2005 2006 2007 2008 2009 2010
With the steady improvement in high-fre- Year of Production
quency performance and decrease in speed-power 4. Peak Ft and Fmax at 5 GHz for SiGe bipolar and RF NMOS devices
product of CMOS, this technology will continue as predicted by the 2003 ITRS.
to gain on traditional BiCMOS
and bipolar implementations.
101
BiCMOS processes will continue
to be strong in the high-perfor-
mance application areas that
require high speed together with
high dynamic range, especially
102
when output power is needed to
drive off-chip, low-impedance
Accuracy [See Legend]

loads. This strength in high per-

formance occurs because the Capacitance Mismatch Per Area Relative to Available Signal
Swing [1/V(m)2]
bipolar devices are carefully opti-
103 Integral Voltage Linearity Relative to Available Signal Swing [1/V]
mized and have intrinsic but
Resistor 1/f-Noise Per Area from 1Hz-1MHz Relative to Available
nonscaling advantages in gain, Signal Swing [m/V]
noise, and matching. In contrast, Resistor 1/f-Noise Per Area from 1 Hz-1MHz Relative to Available
CMOS analog devices have equal- Signal Swing [1/V(m)2(Hz)1/2]
ly good frequency behavior com- 104
bined with lower cost and
steadily improved but slightly
lower performance on the other
parameters.
Continuously increasing digital
105
processing capabilities enable 110 90 80 70 65 57 50 45 40 32 28 22 20 16
more signal treatments to be
DRAM Pitch - Technology Node [nm]
done in the digital domain. It is
expected that full-digital imple- 5. Performance metric of several analog passive device parameters relative to the available signal swing
mentations in CMOS will replace (roughly determined by the supply voltage) from the 2003 ITRS roadmap versus technology node.

IEEE CIRCUITS & DEVICES MAGAZINE NOVEMBER/DECEMBER 2004 43

 RF TRANSCEIVERS: merit at each technology node. To close this gap, it is typical to
REQUIREMENTS AND CHALLENGES use more advanced CMOS nodes (by one or two generations) to
RF transceivers include both receive and transmit chains that realize similar performance to older SiGe BiCMOS nodes.
perform amplification, filtering, and frequency conversion. Performance of the VCO is typically measured by phase
The receiver and transmitter chain may be on one or multiple noise (magnitude of the signal at an unwanted frequency rela-
ICs and convert the carrier frequency to a lower frequency tive to the magnitude of the signal at the center frequency).
which can be used by the AD converters (ADCs) or DA con- Phase noise, and, thus, VCO performance, are typically linked
verters (DACs) discussed in the previous section. This conver- to the quality of inductor and varactor elements that are res-
sion can occur in one step in a direct conversion architecture onating at the center frequency and to the 1/f noise of active
or multiple steps in a heterodyne architecture. While the two devices. Bipolar devices have a significant advantage over RF
architectures drive slightly different requirements in perfor- CMOS devices in 1/f noise. This advantage is expected to
mance and linearity, major building blocks of an RF increase with more advanced technology. But good perfor-
transceiver are depicted schematically in Figure 2 for both mance VCOs have been realized in RF CMOS despite their 1/f
cases. These building blocks include the low-noise amplifier noise. Inductor performance is less a function of the underly-
(LNA), the frequency synthesizer that makes use of voltage ing device technology (RF CMOS versus BiCMOS) and more a
controlled oscillators (VCOs), mixers for the down and up fre- function of the metal and substrate resistivities. High-resistiv-
quency conversion, and drivers which amplify outgoing sig- ity substrates and low-resistivity thick metal layers are being
nals for transmission by a PA described in the next section. deployed both in RF CMOS and BiCMOS technologies to offer
Technologies used today to realize RF transceivers include improvements in inductor quality factors (Qs) and enable
silicon BiCMOS, SiGe BiCMOS, and RF CMOS. BiCMOS tech- integration of higher performance VCOs.
nologies (Si and SiGe) dominate today the RF transceiver mar- Drivers are responsible for preamplifying an outgoing signal
kets for carrier frequencies below 10 GHz. BiCMOS technologies to feed a PA module. Because large output power is desired, the
enable the use of bipolar devices for LNAs, low-power pre-scalers ability to handle higher voltages is a desirable feature. For this
and power drivers and CMOS devices for frequency synthesizers reason, high-voltage (HV) transistors are integrated both in
and for small amounts of logic. However, RF CMOS transceivers CMOS and SiGe technology. Figure 7 shows the maximum
are being introduced for less demanding applications. voltage-handling capability of HV SiGe bipolar devices [limited
The most stringent technology requirements for an RF by breakdown voltage between collector and base, emitter open
transceiver are driven by the demands of the LNA/mixer, VCO, (BVCBO)] and HV CMOS devices (limited by reliability), and
and power driver. We will discuss these in more detail in this sec- Figure 8 shows the Fmax of the these HV devices as defined by
tion. LNA/mixer design involves a tradeoff between power con- the ITRS roadmap. A large advantage exists for SiGe technolo-
sumption, gain, noise figure (NF), and linearity. This tradeoff is gy, both in voltage-handling capability and Fmax , that is not
related to basic device parameters described by the 2003 ITRS reduced in advanced CMOS nodes. Laterally diffused MOS tran-
roadmap such as Ft , Fmax , and minimum NF. Figures 4 and 6 sistors (LDMOS) or drain-extended MOS transistors offer possi-
depict the 2003 ITRS roadmap for peak Ft , peak Fmax , and mini- ble solutions to this problem for RF CMOS technology at the
mum NF at 5 GHz for both SiGe bipolar and RF CMOS devices. expense of a couple of additional masking layers.
The abscissa in these figures is the year of volume production. In summary, we have shown that current architectures lend
Based on the roadmap, SiGe devices are expected to maintain a themselves to implementation in either RF CMOS or Si and
performance advantage over CMOS for each of these figures of SiGe BiCMOS technology, with BiCMOS technology dominat-
ing the market at present for carrier frequencies below 10 GHz.
As RF CMOS is scaled, it can compete better in performance
0.90
with SiGe bipolar devices. But, other advantages of SiGe tech-
Minimum Noise Figure at 5 GHz (dB)

0.80 SiGe Bipolar nology, such as the ability to integrate efficiently power drivers,
RF NMOS can actually become more significant as CMOS supply voltage
0.70
is reduced. Cost favors a CMOS transceiver in a given technolo-
0.60
gy node, but, if a more advanced RF CMOS node is required
0.50 versus an older BiCMOS node to meet performance require-
0.40 ments, cost may or may not be on the side of the RF CMOS
0.30 solution. Finally, the cost of the overall radio is being reduced
by the integration of more functionality on fewer components.
0.20
Integration of the transceiver with the analog and digital sec-
0.10 tions of the radio favors an RF CMOS solution while integration
0.00 of the PA and PM functions with the transceiver favor a BiC-
2002 2003 2004 2005 2006 2007 2008 2009 2010
MOS solution. It is likely that these multifaceted constraints
Year will drive different decisions for different markets and stan-
6. Minimum noise figure at 5 GHz for SiGe bipolar and RF NMOS dards such that both BiCMOS and RF CMOS transceivers will
devices as predicted by the 2003 ITRS. co-exist in the market for the foreseeable future.

44 IEEE CIRCUITS & DEVICES MAGAZINE NOVEMBER/DECEMBER 2004

 PAS AND PM: REQUIREMENTS of the RF PA and other wireless circuit blocks, regulate bat-
AND CHALLENGES tery/charger surges, detect power levels, and provide the appro-
In 2003, the bulk of the consumer market (subscriber) for PA priate temperature/ ruggedness/leakage control for efficient
technologies continued to be RFICs and modules for cellular system operation. This PM function is typically accomplished
subscriber handsets, with handset volume yearly sales exceed- with HV CMOS technologies and typically requires very large
ing 400 million units. The cellular PA industry is already sup- periphery pass FET devices. The periphery of a pass FET refers
porting components in large volume for two-and-one-half to the combined width of all fingers that comprise the device.
and third-generation handsets that are capable of delivering The combined width typically exceeds hundreds of millimeters
much higher data rates necessary for convenient wireless Web in order to achieve very low series resistance. It is expected that
access functions. WLAN applications have also become anoth- the PM function will also be integrated as part of the SOC tech-
er significant driver of integrated PA modules, with volumes nology, instead of a separate IC within a module.
expected to exceed tens of millions of units in 2003. Both Since the module footprint is continually shrinking while
applications have very strict RF performance specifications the module complexity is continually growing, a technology
and are extremely sensitive to price/performance tradeoffs. capable of integrating more of the radio functions will ultimate-
This tradeoff continuously drives the industry towards highly ly be the technology of choice for cellular handsets. Two of
integrated low-cost system solutions. The market for PAs is these RF functions are filters and T/R switches. If MEMS switch
increasingly migrating away from packaged single die (RFICs) reliability improves and their voltage requirements decrease,
to multiband, multimode, integrated modules, delivering a they can potentially offer a post-processing integration solution
complete amplifier solution. These RF modules typically inte-
grate all or most of the matching and bypassing networks and
may also provide power detection, PM, filtering, and RF 14
switches for both transmit/receive (T/R) and band selection. SiGe Bipolar
12 RF NMOS
As a logical extension of the integrated PA module, there
is increased activity in the integration into the module of all 10
Voltage Limit (V)

other radio functions, such as transceivers, frequency synthe-

8
sis, filters, and digital sections, amongst others. Such inte-
gration provides a true single radio module solution in a 6
small footprint with a digital interface to the handsets
4
DSP/CPU. There is little doubt that such SIP single radios
will eventually become commonplace in the industry. The 2
challenges for the semiconductor technology community will
0
likely be how to meet the cost and performance targets, with 2002 2003 2004 2005 2006 2007 2008 2009 2010
as much integration as possible available in the semiconduc-
Year
tor technologies.
Because RF PAs have large signals, they require significant 7. Maximum voltage limit of HV bipolar devices and HV RF NMOS
devices plotted as a function of year. The y-axis is determined for SiGe
ruggedness and higher breakdown voltages than available in bipolar devices by their BVCBO given in the 2003 ITRS and for RF
standard CMOS submicron technologies. In addition, since NMOS devices by their reliability imposed power supply limits.
these amplifiers operate in battery-powered devices with typi-
cally 3 V, semiconductor technologies must have their perfor-
mance optimized for low voltages. Today, these PAs are 200
Minimum Noise Figure at 5 GHz (dB)

typically built as standalone components with either GaAs 180 SiGe Bipolar
HBT, Si LDMOS, or GaAs pseudomorphic high electron 160 RF NMOS
mobility transistor (PHEMT) technologies. At this time, InP-
140
based HBT devices do not appear to have found a niche in
120
commercial PA applications due largely to increased cost and
fabrication complexity. There are significant research and ini- 100
tial product releases for SiGe BiCMOS and standard Si CMOS 80
technologies for use in cellular PAs. But, no market penetra- 60
tion of these technologies has occurred to date. The integra- 40
tion of the RF power function into the silicon system-on-chip
20
(SOC) solution requires significant device optimization and
development efforts. These efforts are not just aimed at realiz- 0
2002 2003 2004 2005 2006 2007 2008 2009 2010
ing the required RF functionality, but also the required isola-
Year
tion necessary for effective system integration.
PM ICs are required for all but the simplest of wireless appli- 8. Peak Fmax plotted for HV SiGe bipolar and HV RF NMOS devices as
cations. Power management ICs condition the power demands described by the 2003 ITRS roadmap.

IEEE CIRCUITS & DEVICES MAGAZINE NOVEMBER/DECEMBER 2004 45

for both GaAs and Si technologies. Integration of filter func- frequencies less than 5 GHz versus time for various semicon-
tions also presents an issue for inclusion in semiconductor ductor technologies (Si LDMOS, GaAs PHEMT, SiC MESFET,
technology. To date, only thick film bulk acoustic resonator and GaN HFET) is shown in Figure 9. The power density of
(FBAR) technologies and MEMS resonators have appeared as RF power FETs is usually given in terms of watts-per-millime-
possible candidates for integration. ter of gate width. The major trends shown in Figure 9 are the
The signal isolation specifications necessary for the system increase in operating voltage and the resulting increase in RF
integration of cellular chipsets represents a very significant power density from 2004 to 2010. The power density of Si
challenge to both technologists and electronic design LDMOS, the present workhorse of the base-station industry,
automation (EDA) tools providers. With the exceedingly high will increase from about 0.7 W/mm at 28 V to 1.2 W/mm at 48
RF voltage created by the PA and PM circuits, in addition to V in the 2009 timeframe. GaAs PHEMT power densities are
the numerous frequencies generated internally by the IF expected to increase from 0.7 W/mm to 1.5 W/mm in the
blocks, signal isolation may become the most difficult obsta- same timeframe. GaAs PHEMT operating voltages will
cle preventing full SOC implementation. increase from 12 V today to 28 V in 2006. The power density
Cellular base stations also present unique challenges to semi- of SiC MESFETs will remain relatively constant over this time
conductor technologies. Base stations provide the communica- frame at 2 W/mm with an operating voltage of 48 V because
tions infrastructure to handle many local subscribers, require research dollars for wide bandgap semiconductors will be
much larger RF power and linearity levels, and have much high- directed at GaN HFETs which have the potential for even
er reliability specifications. The 2003 base station semiconductor higher power densities. The first commercial 30-W GaN
market is primarily at 2 GHz and below. The future market is HFETs will appear in 2006 with a power density of 2.5 W/mm
projected to expand to higher frequencies as new applications at 28 V. By 2008, GaN HFETs with 4 W/mm operating at 48 V
and frequency bands are allocated. Cost as measured by dollars will be commercially available. Currently, GaN HFETs are fab-
per RF watt is projected to steadily decrease from about US$1/W ricated on a variety of different substrates because of the lack
today to less than US$0.50/W by 2008. The application space is of a GaN substrate. At this time, the most commonly used
undergoing a conversion from ceramic to plastic packaging that substrate for GaN HFETs is SiC because of its very high ther-
will drive much of the cost reduction. In 2003, Si LDMOS FETs mal conductivity. However, progress towards high-volume
are the dominant semiconductor technology, easily command- manufacturing is hindered by the small size and high cost of
ing a 95% market share with GaAs FETs picking up the rest. SiC 2-in semi-insulating SiC wafers.
and GaN FETs are now appearing over the technology horizon, The base station application space is moving away from satu-
but significant research and development is required before these rated to more linear PAs to support the digital modulation for-
technologies approach mainstream manufacturing. mats of CDMA and WCDMA. The available linear power from a
A major trend for all semiconductor device technologies is given device is about half the saturated power from the same
the move to higher operating voltage that will increase power device. The power-added efficiencies for devices operated in linear
density and reduce device size for the same output power. The applications are substantially lower by between 15 and 25% than
reduced device size requires less complex impedance match- they are for devices operated in saturated applications. Maximum
ing networks, reduces power loss, and increases power effi- RF output power from a single device will not increase above
ciency. The RF power density trend for 60-W devices at approximately 240 W unless there is a major change in the design
of PA systems. Although LDMOS enjoys a near
monopoly in current cellular base stations, there is
a concern that its performance at frequencies high-
60-W Devices er than 2 GHz will not be sufficient to meet the
Saturated RF Power Density (W/mm)

Frequency < 5 GHz GaN HFET 48 V necessary specifications. Failing to meet this chal-
4
lenge will result in the utilization of the other more
expensive technologies. A major challenge for GaAs
GaN HFET 48 V FETs is the move to a higher operating voltage that
3
is closer to the operating voltage of LDMOS (28 V).
GaN HFET 28 V The major challenge for GaN technology is achiev-
2 SiC MESFET 48 V ing the very high level of device reliability that has
GaAs PHEMT 28 V been demonstrated using LDMOS and GaAs. High-
GaAs PHEMT 28 V heat dissipation packaging will need to be devel-
1 GaAs PHEMT 12 V Si LDMOS 48 V oped to take full advantage of the potential of GaN
Si LDMOS 40 V technology.
Si LDMOS 28 V

MILLIMETER WAVE:
2004 2005 2006 2007 2008 2009 2010 REQUIREMENTS AND CHALLENGES
Today, compound semiconductors dominate the
9. Power density versus year. 10100 GHz range. The device types most com-

46 IEEE CIRCUITS & DEVICES MAGAZINE NOVEMBER/DECEMBER 2004

monly used for analog millimeter-wave applications are need to be applied successfully to emerging III-V technologies
HEMT, PHEMT, and metamorphic HEMT (MHEMT), while of InP, SiC, and GaN. One of the critical challenges for high-
MESFET and HBT predominate for mixed-signal and high- power III-V devices is thermal dissipation. This challenge is
speed applications. Except for MESFET and SiGe HBTs, all especially true for high-power density devices such as GaN.
device types employ epitaxial layer stacks that are composed of The major classes of millimeter wave transistors are listed in
ternary or quaternary compounds derived from Columns III the following paragraphs. While the transport mechanisms and
and V of the periodic chart. structure within each type are similar, there are vast differences
Because device properties are critically dependent on the in performance attributable to the selection of substrate materi-
selection of materials, thickness, and doping in the stack, al and design of the epitaxial layer stack. See [7][9] for more
which are proprietary to the manufacturer, there is great in-depth descriptions of these device technologies.
diversity in the nature and performance of these devices. Field effect transistors (FETs) are majority carrier devices
Tradeoffs among power, efficiency, breakdown, NF, linearity, in which electron transport is in a thin layer parallel to the
and other performance parameters abound. One consequence wafer surface. The major types are as follows:
of these tradeoffs is that the lithography node is not the pri- 1) MESFETs are composed of homogeneous layers in
mary driver for millimeter-wave performance, although which electron transport occurs in an intentionally
lithography dimensions are certainly shrinking with the drive doped layer and are generally GaAs-based.
to high frequency figures of merit (e.g., maximum Ft and 2) HEMTs are composed of layers of different bandgap
Fmax ). Performance trends are driven more by a combination materials on a lattice-matched substrate. Carriers in
of desirable tradeoffs and bandgap engineering of the epitax- HEMTs are provided by a highly doped layer, and carrier
ial layer stack in concert with shrinking lithography. transport occurs in an adjacent undoped layer, resulting
Compound semiconductor technologies have a number of in much higher mobility due to the lack of ionized
similarities with silicon technologies yet, in many ways, are charge scattering. HEMTs are generally InP- and GaN-
distinctly different. While III-Vs have benefited from the based.
advances in manufacturing equipment and chemistries, the 3) PHEMTs are composed of layers with different bandgap
development of these tools and chemicals is focused on the materials on a substrate in which the lattice constant of
silicon industry and is not necessarily optimum for compound the layers are close, but not matched, to the lattice con-
semiconductor processing. Six-inch diameter semi-insulating stant of the substrate. PHEMTs have higher mobility
GaAs wafers are routinely available and are becoming the de than HEMTs and are generally GaAs-based.
facto standard, although some foundries are still at four-inch. 4) MHEMTs are composed of layers of different bandgap
The move to six- and eight-inch substrates will be driven not materials on a substrate in which the lattice constants
only by economies of scale and chip cost, but also by equip- of the layers are mismatched to the substrate. The
ment availability, as the tool industry focuses on products to resulting strain is taken up by a specially designed
handle larger wafer sizes used in the silicon industry. buffer layer. MHEMTs offer the highest degree of flexi-
GaAs tends to be two generations behind Si in wafer size, bility in design and in millimeter-wave performance.
with InP a further generation behind. It is crucial that sub- Generally, they are made on GaAs substrates to take
strate size keep up with Si advances if the III-V industry is to advantage of the more mature materials and processing
benefit from advances in processing equipment. This contin- technologies.
ued pace in substrate size is particularly true for InP and SiC, HBTs are minority carrier devices in which carrier trans-
the latter of which still suffers from a significantly high defect port is perpendicular to the wafer surface. The major types are
density. Today, there is no production source of GaN sub- as follows:
strates; most GaN device epitaxy is done on SiC substrates. 1) InP HBTs are composed of ternary and quaternary layers
Significant technology breakthroughs will be required before that contain elements from groups III and V, such as In,
GaN becomes commercially viable. Unresolved issues remain Ga, As, Sb, and P, and are closely lattice matched to InP
regarding SiC versus GaN substrates for GaN HEMTs. substrates. GaAs HBTs are generally used below 10 GHz.
Advances in high-resistivity Si substrates must also be 2) SiGe HBTs are composed of a single crystal mixture of
addressed as SiGe HBT and RF CMOS push toward the mil- Si and Ge on a Si substrate.
limeter-wave spectrum. InP HBTs and SiGe are ideal for high-speed logic and
Device challenges, some of which are unique to III-Vs, mixed-signal applications. These applications are due to the
include the following: much better threshold control in bipolars, in which the
1) the requirement for substrate vias for low-inductance threshold is a function of bandgap (a materials property) rather
grounds in microstrip millimeter-wave circuits than the Schottky Barrier and Fermi Level (a processing prop-
2) techniques for heat removal including wafer thinning erty). HBTs are also the devices of choice for low-phase noise
and low parasitic air-bridge interconnects, oscillators. MESFETs are likely to become obsolete for new
3) high breakdown voltages for power devices applications in about 2005 as InP and SiGe cost and perfor-
4) nonnative oxide passivation. mance advantages overtake MESFETs. Although the gap
While these issues have been mostly solved for GaAs, they between InP and SiGe is closing, InP will always have the

IEEE CIRCUITS & DEVICES MAGAZINE NOVEMBER/DECEMBER 2004 47

 advantage of higher breakdown, while SiGe BiCMOS holds the
advantage for integration density.
20032009 Technology Positioning
6 The ovals in Figures 1012 portray the projected technolo-
gy trends among the various device types over the near term.
5 In Figure 10, the PHEMT oval represents the NF versus fre-
quency for devices commercially available today. While
4 PHEMTs are the mainstay of low noise devices in the millime-
NF (dB)

PHEMT InP HEMT/ ter-wave spectrum at present, it is expected that they will
3 MHEMT quickly be supplanted by InP in the near term and eventually
MHEMT by the end of the decade. This projection is exhibited
2
by the InP/MHEMT bubble region that portrays the region in
the NF/frequency realm of reported research results through
1
2003. Current R&D results project future commercial trends.
Not only do InP HEMTs and MHEMTs exhibit lower NFs, but
0
20 30 40 60 100 200 also the required dc power dissipation is roughly four times
Frequency (GHz) lower for equivalent NF and gain performance.
Figure 11 shows the evolution of millimeter-wave power
10. LNAs. performance over time. The power performance figure of
merit (FOM) is MMIC power density (W/mm) times MMIC
small signal (SS) gain per stage (dB) at application center
frequency for a typical 1020% bandwidth. The power band-
50 width product for the different device technologies could
Power Performance FOM

40 have also been used and would have provided a similar

Ga

trend. GaAs PHEMT and InP HEMT are the premier millime-
N
HE

30 ter-wave power devices available today in production, with

MT

20 GaAs PHEMT the preferred technology for frequencies less

20

GaA
s PH than 77 GHz. However, present-day GaAs PHEMTs and InP
07

EMT
10 2005 Power MHEMT HEMTs do not have the power performance to meet future
GaAs PHEMT 2006 InP H
2003 EMT 2003
0 systems requirements. Continued evolution of GaAs
0 20 40 60 80 100 PHEMTs and InP HEMTs will offer increased performance
Frequency (GHz) but will still fall short of evolving demands.
In engineering a millimeter power device, the engineer is
11. The evolution of production power devices 20032009. The faced with a dilemma: increased power (or power density)
performance figure of merit is MMIC power density (W/mm) times
MMIC SS gain per stage (dB) at application center frequency (typically necessitates operating devices either at higher operating volt-
1020% bandwidth). ages or high current densities. For a given device technology,
in addition to the tradeoff between operating voltage and cur-
rent density, increasing operating voltage comes
at the expense of high frequency operation or
20032008 Technology Positioning gain. As an example, GaAs PHEMTs that can
1 operate at higher voltages compared to InP
HEMTs tend to be gain limited in the upper mil-
Normalized Performance

InP HBT - 2008 limeter frequency range. On the other hand,

todays InP HEMTs that have superior high-fre-
InP HBT - 2003
quency gain are limited to low-voltage (and sub-
SiGe Bipolar - 2008 InP E/D HEMT
2008 sequently low-power) operation. The challenge
SiGe Bipolar InP E/D HEMT
2003
for the device engineer is to develop a device
2003
structure that combines the best attributes of
CMOS
both GaAs PHEMTs (higher voltage operation)
Si CMOS 2008 and InP HEMTs (high-frequency gain).
GaAs 2003
MESFET One approach currently under development is
2003 MHEMT technology, which takes advantage of
20 40 60 80 100 120
bandgap engineering to create a device structure
Clock Frequency (GHz)
that exhibits the best compromise between the rel-
atively HV operation of GaAs PHEMTs and the
12. Mixed-signal/ultra high-speed digital: the metric for performance depends on the
class of circuit. It can include dynamic range, signal-to-noise, bandwidth, data rate, high gain of InP HEMTs. As shown in Figure 11,
and/or inverse power. power MHEMT technology is expected to eclipse

48 IEEE CIRCUITS & DEVICES MAGAZINE NOVEMBER/DECEMBER 2004

both GaAs PHEMT and InP HEMT performance in the 40100+ throughput (measured in hours per wafer, as opposed to
GHz frequency range and will be available in production in the wafers per hour) needs to be improved with high-current
2006+ timeframe. electron sources and fast alignment systems.
Another promising approach is the wide bandgap semicon- Substrate quality is still problematic for emerging wide
ductor GaN. At microwave frequencies, GaN HEMTs have bandgap devices. Research on GaN templates is continuing,
exhibited five to ten times the power density of GaAs but, in the interim, SiC substrates will become more viable as
PHEMTs, and GaN HEMTs have shown potential for operation defect density is improved. If SiGe is to challenge the millime-
through Ka-band. GaN HEMTs achieve this revolutionary ter-wave spectrum, high-resistivity low-loss silicon needs to
power performance through a combination of high current be addressed.
density and significantly higher operating voltage with only Thermal dissipation is the major challenge for wide-bandgap
modest reduction in gain compared to GaAs PHEMTs. With III-V power devices. While GaN and SiC substrates have higher
continued development within the next five years, GaN thermal conductance values compared to GaAs and InP, the 5
HEMTs are projected to become the premier and preferred to 10 higher power densities typically present in these wide
device technology for millimeter-wave power applications bandgap semiconductors somewhat offsets the advantage in
through Ka band. higher thermal conductance. These circumstances make ther-
Figure 12 shows the evolution of mixed-signal technology mal dissipation a critical device design aspect. Proven tech-
for millimeter-wave applications. Such applications are driven niques include thin (0.002 in) wafers, thermal shunts, and
by high center frequency, precise transistor matching, low- bathtub vias [10]. These techniques, as well as more innovative
noise operation, and high linearity in the underlying technolo- solutions, need to be applied to wide bandgap devices.
gy. With continuous scaling, CMOS technology is expected to HV breakdown is desirable for both mixed-signal as well as
address low-resolution circuits up to 1020 GHz. SiGe bipolar high-power devices. As dimensions are scaled downward for
extends the region of silicon performance to 4050 GHz, but higher frequency performance, operating voltage suffers. This
will likely be limited in dynamic range due to the breakdown is particularly troublesome for mixed-signal devices that
voltage (BVCEO) being less than 2 V. InP HBTs are the ultimate require more headroom for analog functions than for digital
performance technology once the core transistor technology is functions. In this regard, InP HBTs offer a distinct advantage
aggressively scaled. InP HBTs will be limited by substrate size over SiGe HBTs, although the integration level offered by
that is typically at 100 mm, but with 150 mm being sampled. SiGe will be orders of magnitude greater. Careful device scal-
InP enhancement/depletion (E/D) HEMTs offer higher frequen- ing and wide-bandgap collectors can help maintain break-
cy operation than InP HBTs when scaled to less than 100 nm. down in InP HBTs. For power FETs, gate recessing has been
E/D technology is also lower power than the HBT alterna- used successfully to achieve higher breakdown, but this has
tive, but the threshold voltage control of the HEMT is not as yet to be applied to GaN. Tailoring of the vertical dimensions
good. The HEMT also does not have as good 1/f noise perfor- of the source-drain region to optimize surface electric fields is
mance as the HBT. E/D technology should operate at lower a potential solution. Continued improvement of passivation
power than similar HBT circuits. and hot carrier effects is also needed.
For applications where high dynamic range is required Finally, high-frequency performance in III-Vs is driven as
(e.g., auto radar), bipolar devices are often preferred due to much by epitaxy (vertical scaling) as by lithography (horizon-
their high linearity and low 1/f noise. The market for tal scaling). Carrier velocity and mobility in the transport
advanced mixed-signal circuits will most likely drive layer can be tailored by proper engineering of the epitaxial
increased wireless communications bandwidth through the layer stack. Continued improvement in all of the III-V devices
real-time correction and synthesis of analog signals using dig- can be expected through bandgap engineering.
ital technologies. To do this, the associated digital and mixed-
signal circuits must run three to ten times faster than the IS THE FUTURE FOR RF AND AMS IN
analog carrier frequency. Additional opportunities exist for EMERGING RESEARCH DEVICES?
performing the control and routing in optical networks. Emerging research devices, such as resonant tunneling
Compound semiconductors must take advantage of the devices, spin transistors, carbon nanotubes, molecular elec-
advances in lithography and processing equipment that are tronics, planar double-gate transistors, and 3-D structures
evolving now in the digital silicon industry. In order to including vertical transistors [11], may have possible future
accomplish this, wafer diameter needs to be within one or two RF and AMS applications. In some cases, these possibilities
generations of the silicon industry. Six-inch semi-insulating are based on promising first performance laboratory results.
GaAs wafers are in production now with InP not far behind. All emerging research RF and AMS devices are expected to
However, the III-V industry needs to continue to push to larg- present severe challenges for high-volume manufacturing,
er wafer sizes as silicon transitions from 8- to 12-in diameter but may also present opportunities for RF and AMS applica-
wafers. While significant advances are being made in optical tions that demand increased performance, reliability, and
lithography tools, the cost of masks is prohibitive for most of functionality. A common technical challenge for most, if not
the relatively low volume III-V applications. Direct-write elec- all, RF and AMS applications of research devices is to under-
tron beams are a solution to the mask cost, but wafer stand the chemistry and physics of the electrical contacts at

IEEE CIRCUITS & DEVICES MAGAZINE NOVEMBER/DECEMBER 2004 49

the nanoscale well enough so that the RF and analog proper- tions. Such products serve the rapidly growing wireless com-
ties are controlled and reproducible in high volumes. Such munications market. They depend on many materials systems,
nanoscale understanding will be enhanced by computationally some of which are compatible with CMOS processing, such as
efficient physical models for carrier transport in elemental SiGe, and others of which are not compatible with CMOS pro-
and compound semiconductors and accurate, fast, and predic- cessing, such as those compound semiconductors composed
tive RF/analog compact models. Also, the figures of merit of elements from groups III and V in the periodic table.
such as 1/f noise, power added efficiency, linearity, bandwidth, The consumer portions of wireless communications mar-
gain, ruggedness, and reliability are not known well enough to kets are very sensitive to cost. As a result, developing RF and
advance nanoscale RF and AMS devices. Measuring and deter- AMS technologies for such applications is not straightforward.
mining such figures of merit will present new areas for signif- The boundary between the Group IV semiconductors Si and
icant research and development. Today, it is not even clear SiGe and the III-V semiconductor GaAs has been moving to
which, if any, nanometer structures could send enough power higher frequencies with time and for other applications the
to an antenna to be worthwhile and which circuit architecture boundary between GaAs and InP is tending to shift to lower
would be the best choice for wireless systems based on those frequencies. Eventually, MHEMTs may displace both GaAs
devices. All this research will exploit the additional degrees of PHEMTs and InP HEMTs. The wide bandgap semiconductors
engineering freedom that many emerging research devices such as SiC and GaN, which are not shown in Figure 1, will be
offer. Two examples of additional degrees of engineering free- used for infrastructures such as base stations at frequencies
dom are independently controlling the voltage of multiple- typically above about 2 GHz. Increased interests for the
gated devices and using an electric field applied 94-GHz band arises from its applications for all weather land-
perpendicularly to the axis of carbon nanotubes to alter their ing and contraband detection. III-V compound semiconduc-
band structures. tors have additional metrics than those usually associated
with CMOS processes. These other metrics include carrier fre-
SUMMARY AND CONCLUSIONS quency for wireless applications and the printed gate length.
Table 1 summarizes the major trends in the RF and AMS tech- The frequency range between about 1040 GHz is the region
nologies presented here. RF and AMS technologies now repre- in which the interplay and competition among elemental and
sent essential and critical technologies for the success of compound semiconductors is expected to occur. Today, group
many semiconductor products. There is increased demand for IV semiconductors (Si and SiGe) dominate below 10 GHz, and
high-end electronic products and products involved with the III-V compound semiconductors dominate above 40 GHz. This
convergence of computing, digital video, and communica- range in frequencies for competition amongst elemental and

Table 1. Summary of major trends.

Analog Mixed Signal
More and more analog functions are being realized by digital implementation instead of by analog implementation. However, increasing mixed-signal per-
formance will drive new applications and cheaper implementations of existing applications.
AMS functions tend now to be integrated together with other digital CMOS functions or sometimes alternatively with RF or PM ICs on the same die
because cost is the by far the most important driver. Process choice may either be BiCMOS or CMOS technology.
Cost may be even more important for AMS functions than for the other transceiver functions. CMOS implementation is occurring in some cases even
without high-precision analog transistors or precision passives that require additional masks.

RF Transceivers
RF transceivers are migrating from heterodyne to direct conversion or low-IF architectures. These architectures directly convert the carrier frequency to
a low frequency that feeds the AMS functions, thereby simplifying frequency conversion by eliminating intermediate steps and reducing the number of
external components.
RF transceivers are built today in Si, SiGe BiCMOS, and RF CMOS. Both BiCMOS and RF CMOS transceivers will co-exist for the foreseeable future to
address the varied market needs of wireless communication devices. Technology choice is dominated by tradeoffs that include the following:
1) required performance of the standard
2) market being addressedSiGe BiCMOS typically has higher performance
3) level of integrationRF CMOS enables integration with more digital functions while SiGe enables integration with more PM or PA functions
4) costRF CMOS is less expensive than SiGe BiCMOS of the same generation node.

PA and PM
Highly integrated PA modules will be realized on multilayer laminates or ceramics with embedded passive technologies. In addition to the active power
die, these modules will also provide all necessary matching, bypassing, band switching, PM, and filtering (SAW/BAW)
functions.
There will be a trend to improve the performance of silicon technologies (MOS and bipolar) towards cellular RF amplification through both technology and
circuit design optimization.
Plastic will become the dominant packaging format for base station semiconductor devices and will significantly reduce the component cost.
The use of compound semiconductors and higher operating voltages will increase the RF power density of base station devices.

Millimeter-Wave
SiGe will challenge InP HBT for applications up to 40 GHz, while InP will predominate for mixed signal applications up to 100 GHz in the near term. In the
far term, SiGe may challenge InP for high-volume applications such as 77-GHz auto radar.
MHEMT will supplant GaAs PHEMTs and InP HEMTs through out the spectrum for low noise/front end and power applications above 40 GHz, while GaN
will make inroads up to 40 GHz by the close of the decade.

50 IEEE CIRCUITS & DEVICES MAGAZINE NOVEMBER/DECEMBER 2004

compound semiconductors changes with time and is expected indentification does not imply recommendation by any of the
to move to high frequencies. Nevertheless, while SiGe has host institutions of the authors, nor does it imply that the
shown capability in the 1040 Gb range, it is an open question equipment or materials are necessarily the best available for
whether it will be able to replace III-Vs in applications where the intended purpose.
either high power gain or ultra-low noise is required.
In future years, we expect the frequency axis in Figure 1
will lose its significance in defining the boundaries among REFERENCES
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tions from James Hutchby at SRC who brought us all together power heterojunction bipolar transistors fabricated with thermal shunt
and established our ITRS RF and AMS Working Group in the and bathub, in Gallium Arsenide Integrated Circuit (GaAs IC) Symp.
Fall of 2002. We also thank the many anonymous reviewers Tech. Dig., 1995, pp. 155158.
whose comments contributed to improving this article. [11] J.A. Hutchby, G.I. Bourianoff, V.V. Zhironv, and J.E. Brewer, Extend-
This article is based in part on the 2003 ITRS Chapter enti- ing the Road Beyond CMOS, IEEE Circuits Devices Mag.,
vol. 18, pp. 2841, Mar. 2002.
tled RF and Analog Mixed-Signal Technologies for Wireless
Communications, Semiconductor Industry Association (ITRS, Herbert S. Bennett is with the National Institute of Standards
2003 edition, International SEMATECH: Austin, TX, 2003, and Technology in Gaithersburg, Maryland. Ralf Brederlow is
http://public.itrs.net/Files/2003ITRS/Home2003.htm). The with Infineon Technologies in Munich, Germany. Julio Costa
ITRS logo is used by permission from the Semiconductor is with RF Micro Devices in Greensboro, North Carolina. Mar-
Industry Association, ITRS, 2003 edition. International garet Huang is with Freescale Semiconductor in Tempe, Ari-
SEMATECH: Austin, TX, 2003. And the image of the cell zona. Anthony A. Immorlica, Jr., is with BAE Systems in
phone is adapted from Videomaker Magazine, December 1999 Nashua, New Hampshire. Jan-Erik Mueller is with Infineon
issue, page 13, and used by permission from the editor of Technologies in Munich, Germany. Marco Racanelli is with
Videomaker Magazine. Jazz Semiconductor in Newport Beach, California. Charles E.
Certain commercial equipment, instruments, or materials Weitzel is with Freescale Semiconductor in Tempe, Arizona.
are indentified in this article to specify adquately the experi- Bin Zhao is with Skyworks Solutions in Irvine, California. E-
mental or theoretical procedures and/or technologies. Such mail: [email protected].

IEEE CIRCUITS & DEVICES MAGAZINE NOVEMBER/DECEMBER 2004 51