PUNJABI UNIVERSITY, PATIALA

SCHEME AND SYLLABI

FOR

MASTER OF TECHNOLOGY (ELECTRONICS AND COMMUNICATION ENGG.)

REGULAR & PART-TIME

(SEMESTER SYSTEM)
YEAR 2006-2007
 YADAVINDRA COLLEGE OF ENGINEERING
PUNJABI UNIVERSITY GURU KASHI CAMPUS, TALWANDI SABO
 LIST OF CORE COURSES

MEC-101 WIRELESS AND MOBILE DATA COMMUNICATION

MEC-102 DATA AND COMPUTER COMMUNICATION NETWORKS
MEC-103 OPTICAL COMMUNICATION
MEC-104 VLSI DESIGN
MEC-105 MICROCONTROLLERS AND EMBEDDED SYSTEMS
MEC-106 DIGITAL SIGNAL PROCESSING AND APPLICATIONS

LIST OF ELECTIVE COURSES

MEC-201 ANTENNA SYSTEM ENGINEERING

MEC-202 DIGITAL IMAGE PROCESSING AND ANALYSIS

MEC-203 INFORMATION THEORY AND CODING
MEC-204 EMI AND EMC TECHNIQUES
MEC-205 SEMICONDUCTOR DEVICES AND MODELING
MEC-206 ARTIFICIAL NEURAL NETWORKS AND FUZZY SYSTEMS

1MEC-207 MEMS AND MICROSYSTEMS

TECHNOLOGY

MEC-208 TELECOMMUNICATION SWITCHING SYSTEMS AND NETWORKS

MEC-209 PROGRAMMABLE LOGIC CONTROLLER
MEC-210 NANOELECTRONICS DEVICES ENGINEERING
MEC-211 PARALLEL COMPUTING FUNDAMENTALS
MEC-212 SPEECH PROCESSING
MEC-213 COMPUTER SYSTEM ARCHITECTURE
MEC-214 MICROELECTRONICS TECHNOLOGY
MEC-215 ADVANCED DIGITAL SYSTEM DESIGN
MEC-216 ADVANCED MICROPROCESSORS AND INTERFACING

SEMINAR AND MINOR PROJECT

MEC-301 SEMINAR-1
MEC302 SEMINAR-2
MEC-303 MINOR PROJECT

DISSERTATION

MEC-401 DISSERTATION
 INTERNAL ASSESSMENT (THEORY PAPERS)

Distribution of marks among components of internal assessment:-

1. Three tests out of which two best to be counted 60%

2. Seminar/Assignments/Quizzes/Surprise tests etc. 30%

*3. Attendance 10%

INTERNAL ASSESSMENT (PRACTICAL PAPERS)

Distribution of Marks among components of internal assessment:-

1. Three tests out of which two best to be counted. 40%

2. Performance in practical session and preparation of notebooks, jobs or projects.

50%

*3. Attendance 10%

*Syndicate decision will be applicable for calculating marks for attendance..

Rounding off for internal assessment will be one after adding the marks of the three
components stated above.

EXTERNAL EXAMINATION FOR ALL THEORY PAPERS

The external examination for all theory papers will be conducted by the examination
branch of the University.

(A) INSTRUCTION FOR PAPER SETTER

 The Question paper will consist of five sections A.B.C.D and E Sections A.B.C and D
will have two questions from the respective sections of the syllabus Section E will have one
question with 10 short answer objective type parts which will cover the entire syllabus
uniformly . All questions will carry the same marks.

(B) INSTRUCTIONS FOR CANDIDATE

1. Candidates are required to attempt one question each from sections A, B, C, D. The
question in Section E is compulsory.

2 Use of non programmable scientific calculator is allowed.

EXTERNAL EXAMINATION FOR ALL PRACTICAL PAPERS

2 THE EXTERNAL EXAMINATION FOR ALL PRACTICAL PAPERS

WILL BE CONDUCTED JOINTLY BY AN INTERNAL AND AN
EXTERNAL EXAMINER (S). BOTH THE EXAMINERS WILL BE
APPOINTED BY THE RESPECTIVE DIRECTOR OF THE
ENGINEERING COLLEGES OF THE UNIVERSITY. THE
DIRECTORS ARE ALSO AUTHORIZED TO DECIDE THE
SCHEDULE OF ALL PRACTICAL EXAMINATIONS.

FACULTY OF ENGINEERING AND TECHNOLOGY

PUNJABI UNIVERSITY, PATIALA

Ordinances for M.Tech

 (Master of Technology)
In the Subject of:-

1. Electronics and Communication Engineering

2. Mechanical Engineering
3. Computer Engineering

Notwithstanding the integrated nature of a course spread over more

than one semester, the Ordinances in force at the time, a students joins a
course shall hold good only for the examinations held during or at the end
of the semester. Nothing in these ordinances shall be deemed to debar the
university from amending the ordinances if any, shall apply to all the
students whether old or new.

1. Structure of the Programme:-

The Course programmer for the degree of M.Tech in the faculty of

engineering and Technology shall consists of theory papers (core and
elective), seminar and dissertation etc. The total credits for M.Tech. degree
shall be 50 credits, which will be split as under.

Core Subject 21 Credit

Elective Subjects 21 Credit
Seminar/Minor Project 08 Credit (Maximum 03 Credit
Per-Semester)
Dissertation One Semester (last semester) Non
Credit
 However work of project will start at
least one semester prior to last semester.

A lecture work of one hour duration per week for a given subject will
carry on credit, where as in case of Tutorial of Practical & Seminar of 2
hours duration will carry one credit.

The M.Tech. degree can be completed in a regular or part-time mode.

One type of mod can be changed into another mode, but cannot be
changed during semester.
Prior permission of the Dean of faculty has to be obtained for any
case of inter change of mode. This has be done before the start of semester
not in between the semester.

A regular student can register for a maximum of 20 credits per

semester and part time candidates can register maximum of 12 credits per
semester. According a regular student can complete his M.Tech. degree in 2
years and part time students can complete the same in 3 years.

Maximum period for a degree shall be four years.

Director of the College will decide the subjects to offered during a
given semester and display the lists before the start/registration for a
semester.

In order to promote in service engineers to improve their

qualification and involves the regular students in teaching assignment
under assistantship scheme, M.Tech. classes can be arranged during
Saturdays, Sundays or order holidays.
 2. Eligibility Criteria:-

The eligibility criteria for M.Tech. Courses shall be minimum of 55%

marks in B.E./B.Tech. courses in addition to this, students must fulfill the
following criteria.

For M.Tech. in Mechanical Engineering he must have B.E./B.Tech. in

Mechanical, Industrial, Production, Manufacturing, Material Science,
Metallurgy, Aeronautical and Auto-mobile engineering.

For M.Tech. in Electronics and Communication he must have

B.E./B.Tech. in ECE, Electrical, Electronics and Instrumentation, Applied
electronics, Instrumentation and Control Engineering and Electrical &
Electronics.

M.Tech. in Computer Engineering as students must have B.E./B.Tech.

in any branch of Engineering or Technology.

3. Basis for Admission:-

For the purpose of Admission following criteria will be followed.

(i) Preference will be given for the candidates who have

qualified the GATE examination and candidate will be
admitted according to the merit of the GATE examination.
 (ii) The seats remaining vacant after adjusting the GATE
candidates will be open to all other candidates and
admission will be made on the basis of merit of the
qualifying examination.

4. Attendance Requirements:-

The Candidates admitted to M.Tech. Course must fulfill the following

requirements:-
(i) He has been the rolls of the department through out the
semester preceeding to the examination.
(ii) Every candidate will be required to attend minimum 75% of the
delivered lectures in each semester.
(iii) The shortage of attendance of lectures by the candidates can be
condoned as per University roles issued from time to time.

5. Number of Seats:-

Number of seats in each course shall be 20. (15 + (5) Sponsored by

Industry, Institutes or other organization.)

6. Schedule of Examination:-

(a) The last date by which the admission forms and fees must reach the
Registrar shall be as follows:-
 Exam Without With late With late fee of Rs.
. Late fee fee of Rs. 500/- 1000/-

Dec./ Sept. 30 Oct. 15 Oct. 21 (No form will

Jan be entertained after 21st
Oct.)

April Feb. 28 March 15 March 21 (No form

/ May will be entertained after
21st March)

(b) The candidate will be required to pay examination fees as prescribed

by the University from time to time. Candidate shall submit their
application forms for admission to the examination duly countersigned
by the Director, College of Engineering.

7. Distribution of Marks:-

Each credit will carry 40 marks thus, this total marks of M.Tech.
degree will be 50x40=2000 marks. In each theory paper 50% marks are
assigned to continuous evaluation (Internal Assessment) and 50% marks
are assigned to University examination which will be conducted at the end
of semester. University examination for theory papers will be of 3 hour
duration. Seminar and Minor project paper will be totally internal and its
internal assessment will also be 100% internal. Medium of instructions and
examination will be English only.
Pass marks for theory papers for University examination will be 40% in
external examination. Internal examination will have 50% as minimum
pass marks. Dissertation will not carry any marks but it will have only pass
or fail category.
 8. Award of Division or distinction:-

Successful candidates who obtain 60% or more marks in aggregate of

all the 50 credit shall be placed in first division. Those who obtain 50%
marks or more but less than 60% marks will be placed in 2 nd division.
Below 50% shall be placed in 3rd Division. Successful candidates who
obtains 75% marks or more in aggregate shall be placed in first division
with distinction.

9. Post Graduate Diploma:-

A candidate shall have the option for the award of post-graduate

Diploma after completion of all the subjects and seminar/main project work
i.e., 45 credit during this study, however, such candidates can seek re-
admission with in 5 years from the date of post graduate Diploma to,
pursue the dissertation work for the award of M.Tech degree.

10. Teaching Assignment to Regular Students:-

In order to promote the teaching capability and help the student

financially the regular students will be permitted teaching assignment at
under-graduate classes in Yadavindra Engineering College depending
upon the availability of time, and of the requirements of the college etc.
 MEC- 101 WIRELESS AND MOBILE DATA COMMUNICATION

LTP
3- 1- 0

Maximum Marks: 70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E. Sections A,
B, C and D will have two questions from the respective sections of the syllabus. Section E will have one question
with 10 short answer objective type parts, which will cover the entire syllabus uniformly. All questions will carry
same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A, B, C and
D of the question paper and the entire section E.

SECTION-A
Wireless Transmission: Introduction, Frequencies for radio transmission, Overview of signals and
antennas, signal propagation, Multiplexing techniques: TDM, FDM, CDM & SDM, Analog and Digital
Modulation techniques, Spread spectrum: Direct sequence, Frequency Hopping.

Mobile Communication: Introduction, Cellular concept, Frequency reuse, Co-channel and adjacent
channel interference, Cell splitting, Handover, Call processing.

SECTION-B
Digital Cellular Mobile Systems: Introduction, GSM digital cellular standard: GSM services, GSM
architecture, GSM Radio aspects, Security aspects, Handover, Call flow sequence in GSM, Evolutionary
directions

SECTION-C
CDMA Digital Cellular Standard: Services, Radio aspects, Security aspects, Traffic channels, Key
features of IS-95 CDMA system, Evolutionary directions

SECTION-D
Mobile Data Communications: Overview of circuit switched and packet switched data services on
cellular networks, Wireless local area networks: Introduction, IEEE 802.11 wireless LAN, Support of
mobility on the internet: Mobile IP
 References:

1. Jochen Schiller, “Mobile Communications”, Pearson Education

2. Raj Pandya, “Mobile and Personal Communication-System and Services”, PHI

3. W. Stallings, “Wireless Communications and Network”, Pearson Education

4. T.S. Rappaport, " Wireless Communications: Principles & Practice

MEC- 102 DATA AND COMPUTER COMMUNICATION NETWORKS

L T P
3- 1- 0

Maximum Marks: 70 Maximum Time: 3

Hrs.
Minimum Pass Marks: 40% Lectures to be delivered:
45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.

SECTION-A
Data Communication Techniques: Synchronous-Asynchronous Transmission, Digital
Transmission, Transmission Media, Impairments, Data encoding Techniques

Communication Networks: Circuit switching, Message switching, Packet Switching. X.25, LAN
Technologies, Virtual Circuits
 Network Reference Models: OSI and TCP/IP, Layered architecture

SECTION - B
Data Link Layer: Design issue, framing, error control, flow control, HDLC, SDLC, data link layer
in the Internet (SLIP, PPP)

Network Layer: Routing Algorithms, shortest path, distance vector routing, Link state routing, and
multicast routing. Congestion control, traffic shaping, leaky bucket, token bucket, choke packets, load
shedding, internetworking- connection oriented and connectionless, fragmentation, internet architecture
and addressing, IP protocol, ICMP, APR, RARP, OSPF, BGP, CIDR, IPv6.

SECTION - C
Transport and Session Layer: Transport Service, quality of service, connection management,
addressing, flow control and buffering, multiplexing, Internet transport protocols- TCP and UDP, Session
layer-Dialogue management, synchronization and remote procedure call.

SECTION - D
Presentation Layer: date representation, data compression, network security and cryptography

Application Layer: DNS, SNMP, Telnet, TFTP, NFS E- mail, SMTP and World Wide Web

References:

1. A. S. Tanenbaum, "Computer Networks", Pearson Education

2. W. Stallings,” Data and Computer Communications", PHI

3. J.F. Kurose, K.W. Ross, “Computer Networking: A Top-Down Approach featuring the Internet",
Pearson Education

4. L.L. Peterson, B.S. Davie, “Computer Networks: A Systems Approach”, Pearson Education
 3MEC-103 OPTICAL COMMUNICATION

L T P
3- 1- 0

Maximum Marks: 70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.

SECTION-A

Introduction: Need and role of Optical Communication Systems, Optical Fibers:

Attenuation, Dispersion and Bandwidth, Fabrication and Installation, Splicing, connectors and
nonlinear effects.

4SECTION-B

Optical Sources and Transmitter: Principle of optical sources, light emitting diodes, laser
diodes: characteristics and efficiency, Optical Transmitter modules.

Optical Detectors and Receivers: Photodiodes, Characteristics of Photodiodes, Noise

sources in Photodiodes, Receiver unit Design.

SECTION-C

Optical Amplifiers: Types of Optical Amplifiers: Semiconductor Laser Amplifier, Erbium

Doped Fiber Amplifiers, Raman and Brillouin Amplifiers, Noise in Optical Amplifiers,
Applications of Optical Amplifiers.
 Optical Network Components: Couplers, Splitters, Wavelength Division Multiplexer and
de-multiplexer, Isolators, Circulators, Attenuators, Optical Switches.

SECTION-D

Optical Communication Systems: Components, Transmitter, Receiver, Eye Pattern and

Probability of Error.

Fiber Optic Network: Architecture of Fiber-Optic Networks, Network Management and

the future.

References:

1. D. K. Mynbaev, “Fiber-Optic Communication Technology,” Pearson

52. V. K. JAIN, “OPTICAL COMMUNICATIONS COMPONENTS AND SYSTEMS,” NAROSA PUBLISHING

HOUSE

3. Senior, “Optical Fiber Communication: Principles and Practice,” PHI

4. Keiser, “Optical Fiber Communication,” Mc-Graw Hill

5. Gower, “Optical Communication Systems,” PHI

6MEC-104 VLSI DESIGN

6.1.1.1.1.1 L T P

310
Maximum Marks: 70 Maximum Time: 3 Hrs.
Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.
6.2
6.3SECTION-A
Introduction: CMOS Technology, Integrated Circuit Designing Techniques, Transistor
Fabrication Process, Design Rules, Layout Design and tools, Logic Gates.

Combinational Circuit Design: Documentation Standards, Circuit Timing, Combinational

PLDs, Decoders, Encoders, Tristate Devices, Adders, Subtractors, ALUs, Comparators,
Multiplexers.

SECTION-B

Sequential Circuit Design: Sequential- circuit Documentation Standards, Latches and

Flip-Flops, Sequential PLDs, Counters, Shift Registers, Synchronous Design Mehodology,
Impediments to Synchronous Design, Synchronizer Failure and Metastability.

Memory, CPLDs and FPGAs: Read-only Memory, R/W Memory, Static RAM, Dynamic
RAM, Complex Programmable Logic Devices, Field Programmable Logic Arrays.

6.3.1.1
6.3.1.2SECTION-C
VHDL: VHDL Background, Requirements, Design Methodology Based on VHDL,

Basic Concepts in VHDL: Structural Specification of Hardware, Design Organization and

parameters.

6.3.1.2.1

6.3.1.2.2 SECTION-D

Descriptions in VHDL: Data types, Operators, Attributes, Data Flow Description,

Behavior description.

References:

1. Wayne Wolf, “Modern VLSI Design,” Pearson Education

2. Johan F. Wakerly, “Digital Design Principles and Practices,”Pearson Education
3. Zainalabedin Navabi, “VHDL Analysis and Modeling of Digital Systems,” McGraw Hill
4. Geiger, “VLSI Design Techniques for Analog and Digital Circuits,” McGraw Hill.
5. Sze, “VLSI Technology,” Tata McGraw Hill.

8MEC-105 MICROCONTROLLERS AND EMBEDDED

SYSTEMS

9 L
T P

3 1 0

Maximum Marks: 70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.

9.1.1SECTION-A
9.1.2Introduction: The Overview of 8051 Microcontroller Family, The Inside of 8051
Microcontroller, Pin Description of the 8051, Addressing Modes.

Instruction Set: Arithmetic, Logic and Single Bit Instructions, I/O instructions, etc.
 10

11SECTION-B

Assembly Language Programming: I/O Programming, Timer/Counter Programming,

Serial Communication, Interrupts Programming.

12

13SECTION-C

Introduction to Embedded Systems: An Embedded System, Processor in the System,

Hardware Units, Software, and Embedded System Examples.

Processor and Memory Organization: Structural Units in a Processor, Processor Selection

for Embedded System, Memory Map, Interfacing Processor, Memories and I/O Devices.

14SECTION-D

Devices and Buses: I/O Devices, Timer and Counting Devices, Serial and Parallel
Communication Between Networked Multiple Devices Using I 2C, CAN, ISA, PCI and advanced
I/O Buses.

Hardware-Software Co-design in an Embedded System: Embedded System Project

Management, Design Issues in system Development Process, Design Cycle, Use of Target
System and In-Circuit Emulator, Software tools for Development of Embedded System, Issues
in Embedded System Design, Case Studies.

References:

1. Mazidi, “The 8051 Microcontroller and Embedded Systems, Pearson

 2. Raj Kamal, “Embedded Systems,” Tata McGraw Hill

3.Kenneth J. Ayala, “The 8051 Microcontroller,” Penram International

MEC-106 DIGITAL SIGNAL PROCESSING AND APPLICATIONS

L T P
3 1 0
Maximum Marks: 70 Maximum Time: 3 Hrs.
Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.

SECTION-A

Introduction: Review of, classification of signals and systems, convolution, difference

equations, correlation.

Fourier and Z Transforms: Properties of Fourier and Z transforms, Frequency analysis of

discrete time signals.

15SECTION-B

Discrete Fourier Transform: Definition and properties of DFT, Linear filtering methods
using DFT, Frequency analysis of signals using the DFT.

Fast Fourier Transform: FFT algorithms and their applications, linear filtering approach to
computation of the DFT.
 16SECTION-C

Implementation of Discrete Time systems: Structure of IIR and FIR systems, state space
analysis and structures.

IIR Filter Design: IIR filter design by Impulse invariance, Bilinear Transformation,
Matched-z Transformation and Approximation of Derivatives Methods Characteristics of
commonly used Analog Filters.

FIR Filter Design: FIR filter design by Frequency Sampling, Using windows methods.

SECTION-D

DSP Processors: Introduction to DSP Processors, Architecture TMS 320C54X and ADSP
2100 DSP processors.

Applications of DSP: Applications of DSP in Communications, speech processing, image

processing, Biomedical and in Radars with case studies.

References:

1. Johan G. Proakis and Dimitris G. Manolakis, “Digital Signal Processing Principles, Algorithms and
Applications,” PHI
2. N. G. Palan, “Digital Signal Processing,” Tech Max Publications Pune
3. Nair, “ Digital Signal Processing: Theory, Analysis and Digital Filter Design,” PHI
4. Digital Signal Processing By Mitra

5. Oppenheim & Schafer, “Digital Signal Processing,” PHI

17MEC-201 ANTENNA SYSTEM ENGINEERING

L T P
3- 1- 0
 Maximum Marks: 70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.

Instructions for candidates: Candidates are required to attempt one question each from sections
A, B, C and D of the question paper and the entire section E.

SECTION-A

Antenna Radiations: Introduction to antenna, retarded vector potential, radiations from

small current element, near and far field approximations, power radiated by current element
and its radiation resistance. Radiation form Half wave dipole, power radiation & its radiations
resistance

Antenna parameters: Radiation pattern ,Radiation intensity , antenna , gain , Directivity

Antenna Efficiency , Effective area , effective length, radiations resistance, Antenna Beam
width, band width, noise temperature of Antenna, Friis transmission Formula.

SECTION-B

Antenna Array: Broad Side array , End fire array , collinear array , parasitic array, Array of
two point sources. Non Isotropic sources, Multiplication pattern, Array of n isotropic point
sources .

Practical Antennas: Folded dipole antenna, Yagi – UDA antenna

SECTION-C

Microwave antennas: Antennas with parabolic reflectors and there feed systems, slot
antenna, and Various types of horn antennas.
 Loop antenna: its E.M.F equation, Directivity, radiation resistance, &Application in
direction finding

SECTION-D

Modes of propagation: Ground wave propagation, Inospheric propagation, Space wave

propagation, Tropospheric propagation, Duct propagation

Inospheric propagation: Structure of ionosphere, Mechanism of radio wave bending by

ionosphere, Critical frequency, maximum usable frequency , optimum working frequency,
virtual height & skip distance .

References:

1. Johan D. Kraus, “Antenna for all Applications,” Tata McGraw-Hill

2. Chatterjee R, “Antenna Theory and Practice,” New Age International

3. K. D. Parsad, “Antenna and Wave Propagation,” Satya Parkashan

18MEC-202 DIGITAL IMAGE PROCESSING AND

ANALYSIS

L T P
3- 1- 0

Maximum Marks: 70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.

19SECTION-A

Digital Image Fundamentals: Scenes and images, different stages of image processing and
analysis, components of image processing system, visual preliminaries, brightness adaptation
and contrast, acuity and contour, texture and pattern discrimination, shape detection and
recognition, colour perception, image formation, geometric and photometric models,
digitization including sampling, quantization and digital image visual details.

20SECTION-B

Image Enhancement and Restoration: Contrast intensification comprising of linear

stretching, non-linear stretching, fuzzy property modification, histogram specification,
modifying grey level co-occurrence matrix and local contrast stretching, smoothing including
image averaging, mean filter, ordered statistic filter, edge-preserving smoothing and low pass
filtering, image sharpening including high-pass filtering and homomorphic filtering, image
restoration fundamentals, minimum mean square error restoration least square error
restoration, constrained least square error restoration.

21

22SECTION-C
23IMAGE COMPRESSION: FUNDAMENTALS OF IMAGE
COMPRESSION, ERROR CRITERION, LOSSY COMPRESSION
INCLUDING TRANSFORM COMPRESSION, BLOCK TRUNCATION
COMPRESSION, VECTOR QUANTIZATION COMPRESSION,
LOSSLESS COMPRESSION INCLUDING HUFFMAN CODING
METHOD.

24

25SECTION-D

26IMAGE SEGMENTATION AND EDGE DETECTION: REGION

EXTRACTION, PIXEL BASED APPROACH INCLUDING FEATURE
THRESHOLDING, OPTIMUM THRESHOLDING AND
THRESHOLD SELECTION METHODS, EDGE DETECTION
FUNDAMENTALS, DERIVATIVE OPERATORS INCLUDING
ROBERTS, 4-NEIGHBOUR, PREWITT AND SOBEL OPERATORS,
CANNY EDGE DETECTOR, LAPLACIAN EDGE DETECTOR
AND LAPLACIAN OF GAUSSIAN EDGE DETECTOR.

27

28REFERENCES:

1. Digital Image Processing and Analysis By Chanda & Majmuder, PHI

2. Digital Image Processing By Gonzales & Woods, PHI

 3. Fundamentals of Digital Image Processing By Jain, Pearson Education

29MEC-203 INFORMATION THEORY AND CODING

L T P
3- 1- 0

Maximum Marks: 70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.

29.1.1.1SECTION-A
Introduction: Information, Entropy, Shanon’s noiseless coding theorem, Source Coding,
Channel Capacity, Shanon’s Channel Capacity Theorem. Sampling Theorem : Practical Aspects
and Signal Recovery.

30SECTION-B

Waveform Coding: PCM Channel Noise and error Probability. DPCM and DM Coding
Speech at Low Bit Rates Prediction and Adaptive Filters. Base Band Shaping for data
Transmission. PAM signals and their Power Spectra. Nyquist Criterion, ISI and eye Pattern
Equalization.

31SECTION-C

Binary and M-ary Modulation Techniques: Coherent and Non Coherent Detection. Error
probability and Bandwidth Efficiency. Bit error analysis Using Orthogonal Signaling.
 32SECTION-D

Channel Coding and Decoding Techniques: Channel Coding- Block Codes, Cyclic Codes
and Convolution Codes, Decoding, Viterbi Decoding Algorithm. Trellis Codes.

References:

1. Digital Communication Techniques: Signal Design and Detection by Simon, PHI

2. Principles of Communication Systems By Taub and Shilling: Tata Mc-Graw Hill
3. Digital and Analog communication By Couch, Pearson
4. Communication Systems Engineering, By John G. Proakis Masoud Salehi, Pearson

32.1.1.1.1.1.1.1 MEC-204 EMI AND EMC TECHNIQUES

L T P
3- 1- 0

Maximum Marks: 70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.
 SECTION-A

Introduction: Aspects of EMC with Examples, Common EMC Units, EMC Requirements
for Electronic Systems, Radiated Emission, Conducted Emission, ESD.

33

34SECTION-B

EMC Design: Application of EMC Design, wires, PCB Lands, Component Leads, Resistors,
Capacitors, Inductors, ferrites, Electromechanical Devices, Digital Circuit Devices.

35SECTION-C

Application Design: Mechanical Switches, Simple emission Model for Wires and PCB
Lands, Lice Impedance Stabilization Network (LISN), Power Supply Filters, Power Supplies
including SMPS, Three Conductor lines and Crosstalk, Shielded Wires, Twisted Wires,
Multiconductor Lines and Effect of incident fields, Shielding and Origin effect.

36SECTION-D

Immunity and Protection in Design: Prevention of ESD event, its hardware and immunity,
System Design for EMC, Grounding, System Configuration, PCB Design.

References:

1. The Technician's EMI Handbook: Clues and Solutions By Joseph Carr

2. Grounding and Shielding Techniques By Ralph Morrison
3. EMC for Product Designers, Third Edition By Tim Williams
4. Printed Circuit Board Design Techniques for EMC Compliance By Mark I. Montrose
 37MEC-205 SEMICONDUCTOR DEVICES AND
MODELING

L T P
3- 1- 0

Maximum Marks: 70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.

SECTION-A

Introduction: Semiconductors, Integrated Circuit Fabrication Technology, Charge

Transport in Semiconductors, Applications of PN junction, Bipolar Junction Transistor and
Thyristers, JFET and MOSFET.
 38SECTION-B

Diode and Transistor Modeling: Integrated Circuits Diodes and Transistors, Current
Voltage Characteristics, Ebersmoll Model and Gummel-Poon Model of Bipolar Transistors.
Current Gain, Early Effect and High Level Injection, 2-D effect, Transient Parameters.

39SECTION-C

MOSFET Modeling: MOSFETs, Analysis of MOSFET Parameters, Short Channel and

Narrow Width Effects, Hot Electron Effects, MOSFET Models.

40SECTION-D

FET Modeling: FETs, Modulation Doped FETs, HEMTs, Heterojunctions and HBTs,
Microwave and Optonic Devices, Outline of Numerical Approach to 2D and 3D Device Models.

References:

1. Semiconductor Devices: Modeling and Technology By Das Gupta PHI

2. Semiconductor Devices By Kano Pearson Education
 MEC-206 ARTIFICIAL NEURAL NETWORKS AND FUZZY SYSTEMS

L T P
3- 1- 0
Maximum Marks: 70 Maximum Time: 3 Hrs.
Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.

SECTION-A

Introduction: Biological neuron physiology, neuronal diversity, brain specifications,

artificial neural networks, historical development, neural attributes, terminology and topology
of neural networks, neuron model, learning in artificial neural networks, introduction to
supervised learning, unsupervised learning, reinforced learning, competitive learning, the delta
rule, gradient descent rule and Hebbian learning, ANN characteristics, ANN parameters, ANN
topologies, ANN discrimination ability including linearly separable ANNs, multilayer ANNs
and nonlinear separable ANNs.

SECTION-B
Neural Network Paradigms: Feed-forward neural networks, McCulloch model, perceptron,
ADALINE and MADALINE models, Winner-Takes-All learning algorithm, Back-propagation learning
algorithm and its mathematical analysis, feedback neural networks, Hopfield model and its mathematical
analysis, introduction to radial basis function and competitive learning neural networks, applications of
ANN.

SECTION-C
Fuzzy Logic Fundamentals: Basic concepts, propositional logic, linguistic variable, membership
functions, operations and rules of fuzzy sets, fuzzy logic, fuzzy rule generation, time dependent fuzzy
logic, temporal fuzzy logic, de-fuzzification

SECTION-D
 Fuzzy System Design: Inference algorithm, fuzzy system design, conventional control system,
fuzzy logic control system, simple design of subway train approaching or leaving a station, fuzzy logic
control vs, PID control, introduction to fuzzy neural networks and fuzzy neural control, industrial
applications of fuzzy logic control.

References:

1. Stamatios V. Kartalopoulos, “Understanding Neural Networks and Fuzzy Logic,” PHI

2. B. Yegnarayana, “Artificial Neural Networks,” PHI
3. Ahmad M. Ibrahim, Introduction to Applied Fuzzy Electronics, PHI
4. J T Ross, “Fuzzy Logic with Engineering Applications”, McGraw-Hill
5. J Nie & D Linkers, “Fuzzy Neural Control”, PHI

41MEC-207 MEMS AND MICROSYSTEMS

TECHNOLOGY

LTP
3- 1- 0

Maximum Marks: 70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.

41.1.1SECTION-A
Introduction: Introduction to Microsensors and MEMS, Evolution of Microsensors and
MEMS, Microsensors and MEMS Applications.
 42SECTION-B

Microelectronics: Microelectonic Technologies for MEMS, Micromachining Technology:

Surface and Bulk Micromachining, Micromachined Microsensors- Mechanical, Interial,
Chemical, Acoustic.

43SECTION-C

Microsystems: Micosystems Technology, Integrated Smart Sensors and MEMS, Interface

Electronics for MEMS.

43.1.1SECTION-D
Applications and Simulators: MEMS Simulators, MEMS for RF Applications, Bonding and
Packaging of MEMS, Future Trends.

References:

441. MEMS AND MICROSYSTEMS DESIGN AND

MANUFACTURE      BY HSU, TAI- RAN, MAC GRAW HILL

2. Introduction ot Microelectromechanical Systems Engineering, By Nadim Maluf and Kirt

Williams, Artech House Publishing

3. MEMS Mechanical Sensors,"By Steve Beeby and Graham Ensel and Michael Kraft and Neil
White , , Artech House Publishin

44.1.1.1.1.1.1.1
44.1.1.1.1.1.1.2 MEC-208 TELECOMMUNICATION SWITCHING SYSTEMS
AND NETWORKS

LTP
3- 1- 0

Maximum Marks: 70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.

44.1.2SECTION-A
Introduction: Evolution of Telecommunications, basics of switching system,
Telecommunication Networks. Strowger Switching Systems, Crossbar Switching, Electronic
Space Division Switching.

45SECTION-B

Data Transmission: Speech Digitization and Transmission, Time Division Multiplexing

Switching, Applications of Optical Fiber Systems in Telecommunications.
 46SECTION-C

Traffic Engineering:Network traffic Load and Parameters,Grade of servicing and Blocking

Probability, Modelling Switching Systems, incoming Traffic and service Time Characteristics,
blocking Models and Loss Estimates, Delay Systems.

Telephone Networks: Subscriber Loop Systems, Transmission Plan and Systems,

Numbering and Charging Plan, Signalling Techniques, cellular Mobile Telephony.

47SECTION-D

Data Networks: Data Transmission in PSTNs, switching Techniques for Data Transmission,
Data Communication Architecture, Link to Link and End to End Layers, Satellite Based Data
Networks, LAN, MAN, Fiber Optic Networks, Data Network Standards, Protocol Stacks and
Internetworking.

Integrated Services Digital Networks( ISDN): Network and Protocol Architecture,

Transmission Channels, User Network Interfaces, Signalling, Numbering and addressing, ISDN
Standards, Expert Systems in ISDN, Broadband ISDN.

References:

1. Telecommunicaion Switching Systems and Networks By Thiagarajan Viswanathan : PHI

2. Telecommunication Switching,Traffic and Networks, By Flood, Pearson

3. ISDN and Broadband ISDN By Stallings, PHI

48
 49MEC-209 PROGRAMMABLE LOGIC
CONTROLLER

LTP
3- 1- 0

Maximum Marks: 70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.

49.1.1SECTION-A

PLC Basics: An Overall Look at PLCs, The PLC: A Look Inside, PLC Programming
procedures, Devices to Which PLC Input and Output Modules are Connected.

Basic PLC Programming: Programming On/Off Inputs to Produce On/ Off Outputs,
Relation of Digital Gate Logic to Contact/ Coil Logic, creating Ladder Diagram from Process
Control Descriptions.

50SECTION-B

Basic PLC Functions: Registers, Timer Functions, Counter Functions, Arithmetic Functions,
Comparison Functions, Numbering Systems and Number Conversion Functions.
 51SECTION-C

Data Handling Functions: PLC Skip and Master Control Relay Functions, Jump Functions,
PLC Data Move Systems and data Handling Functions.

PLC Functions Handling with Bits: Digital Bit Functions, Sequencer Functions and Matrix
Functions.

52SECTION-D

Advanced PLC Functions: Analog PLC Operations, PID Control of Continuos Process,
Networking of PLCs, Factors to Consider in Selecting a PLC.

References:

1. John W. Webb, “Programmable Logic Controllers: Principles and Applications, PHI.

2. Gary Dunning, “Introduction to PLCs, Thomson Delmar

 53MEC 210 NANOELECTRONICS DEVICES
ENGINEERING

54

LTP
3- 1- 0

Maximum Marks: 70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.

55

56SECTION-A

Introduction: Nano, Size matters, Fundamental Science Behind Nanotechnology,Tools of

Nanosciences.
56.1.1.1.1.1.1 SECTION-B
Silicon Nanoelectronics and Ultimate CMOS Microelectronic Transistor: Structure,
operation, Obstacles to Miniaturization.:-Structure and Operation of a MOSFET, Obstacles to
Further Miniaturization of FETs.
 57SECTION-C

Solid State Quantum Effect and Single-electron Nanoelectronic Devices: Island, Potential
Wells, and Quantum effects, Resonant Tunneling Devices, Distincyion Among Types of

Devices: Other Energetic Effects, Taxonomy of Nanoelecronic Devices, Drawbacks and

Obstacles to Solid-State Nanoelectronic Devices.

58SECTION-D

Molecular Electronics: Molecular Electronic Switches Devices, Background of Molecular

Electronics, Molecular Wires, Quantum- effect Molecular Electronic Devices, Electromechanical
Molecular Electronic Devices.

References:

1. Ratner, “Nanotechnology: A Gentle Introduction to Next Big Idea,” Pearson

2 Overview of Nanoelectronic Devices : IEEE Proceedings.

3. Silicon Nanoelectronics By Shunri Oda

MEC-211 PARALLEL COMPUTING FUNDAMENTALS

L T P
3- 1- 0
 Maximum Marks: 70 Maximum Time: 3 Hrs.
Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.

SECTION-A
Introduction: Evolution, Parallel Processing Terminology, Data and Control Parallelism,
Pipelining, Flynn’s Taxonomy, Speedup, Scaled Speedup, and Parallelizability
PRAM Model, Parallel Algorithms

SECTION-B

Multiprocessors: Processor Arrays, Multiprocessors and Multi-computers: Processor

Organizations, Processor arrays, Multiprocessors- UMA, NUMA, Multi-computers

Parallel Processing: Instruction level Parallel Processing, Pipelining of processing elements,

Pipelining Limitations, Superscalar Processors, Very Long Instruction Word Processor

SECTION-C
Interconnection Networks: Basic Communication Operations, Interconnection Networks

Mapping and Scheduling: Embedding of task graphs in processor graphs, Dilation, Load Balancing
on Multicomputers, Static Scheduling techniques, Deterministic and Non-deterministic models,
Prevention of deadlocks

59

SECTION-D
 Performance Evaluation of Parallel Computers: Basics, Sources of Parallel overhead, Speed -Up
Performance Laws, Amdhal’s law, Scalability Metric, Performance Measurement Tools.

References:

1. Michael J. Quinn, "Parallel Computing, Theory & Practice", McGraw-Hill

2. V Rajaraman & C S R Murthy, “Parallel Computers, Architecture and Programming", PHI

3. A. Grama, “Introduction to Parallel Computing ", Pearson Education

4. Hwang & Briggs F.A., “Computer Architecture and Parallel Processing”

MEC –212 SPEECH PROCESSING

L T P
3- 1- 0

Maximum Marks: 70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and
E. Sections A, B, C and D will have two questions from the respective sections of the syllabus.
Section E will have one question with 10 short answer objective type parts, which will cover the
entire syllabus uniformly. All questions will carry same marks.

Instructions for candidates: Candidates are required to attempt one question each from
sections A, B, C and D of the question paper and the entire section E.

60SECTION-A

Introduction: Fundamentals of Digital Speech Processing, Digital Models of the Speech

Signal.
 61SECTION-B

Speech Processing Models: Time Domain Models of Speech Processing, Digital

Representation of Speech Waveform.

62SECTION-C

Fourier Analysis and Homomorphic Speech Processing: Short-Time Fourier Analysis,

Homomorphic Speech Processing.

62.1.1.1.1.1.1.1.1 SECTION-D

Coding and Digital Speech Processing: Linear Predictive Coding of Speech, Digital Speech
Processing for Man-Machine- Communication by Voice.

References:

1. Rabiner, “Digital Processing of Speech Signals,” Pearson

2. Thomas, ‘Discrete Time Speech Signal Processing,” Pearson
 63MEC- 213 COMPUTER SYSTEM ARCHITECTURE

L T P
3- 1- 0

Maximum Marks: 70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A,
B, C and D of the question paper and the entire section E.

SECTION-A
Basic Computer Organization: Introduction, Organization & Architecture, Computer Evolution
and Performance, computer System Buses, registers & stacks, ALU, CPU, Control Unit, Hardwired and
Micro programmed Control

SECTION-B
CPU Instruction Sets: Characteristics, Functions, Addressing modes and Formats, CPU Structure,
Processor & Register Organization, RISC and Superscalar Processors, PowerPC, Pentium

Computer Arithmetic: Integer & Floating Point Arithmetic

SECTION-C
Memory and I/O Devices: Internal & External memory, Virtual & High-Speed memories, I/O
Devices & Modules, Programmed & Interrupt driven I/O, DMA

SECTION-D
 Parallel Processing and Pipelining: Introduction and Fundamentals of Parallel Processing and
Pipelining.

References:

1. John P. Hayes, “Computer Architecture and Organization", McGraw-Hill

2. Stallings, “Computer Organization and Architecture", Pearson Education

3. M. M. Mano, “Computer System Architecture", PHI

4. Patterson and Hennessy, “Computer Architectures", Morgaon Kauffman

 MEC-214 MICROELECTRONICS TECHNOLOGY

LTP
3- 1- 0

Maximum Marks: 70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A, B,
C and D of the question paper and the entire section E.

SECTION-A

Crystal Growth and Wafer Preparation : Introduction, Electronic-Grade Silicon,

Czochralski Crystal Growth, Silicon Shaping

Epitaxy: Introduction, Vapor-Phase Epitaxy, Molecular Beam Epitaxy, Silicon on Insulators

Oxidation:Introduction, Growth Mechanism and Kinetics, Thin Oxides, Oxidation

Techniques and Systems

SECTION-B

Lithography: Introduction, Optical Lithography, Electron Lithography, X-ray Lithography,

Ion Lithography

Reactive Plasma Etching: Introduction, Plasma Properties, Feature- Size Control and
Anisotropic Etch Mechanisms
 Dielectric and Polysilicon Film Deposition: Introduction, Deposition Processes,
Polysilicon and Silicon Dioxide Layer Deposition

SECTION-C

Diffusion: Introduction, Models of Diffusion in Solids, Fick's One-Dimensional Diffusion

Equations, Atomic Diffusion Mechanisms

Ion Implantation: Introduction, Range Theory, Implantation Equipment, Annealing

SECTION-D

Metallization :Introduction, Metallization Applications, Metallization Choices, Physical

vapor Deposition, Patterning

VLSI Process Integration: Introduction, Fundamental Considerations for IC processing,

NMOS IC Technology, CMOS IC Technology, Bipolar IC Technology, IC Fabrication

References:

1. S.M. Sze, “VLSI Technology,”

2. S.K.Gandhi, “VLSI Fabrication Principles,”

3. D. Nagachaudhary, “Introduction to Microelectronics Technology,”

MEC-215 ADVANCED DIGITAL SYSTEM DESIGN

L T P
3- 1- 0

Maximum Marks: 70 Maximum Time: 3

Hrs.

Minimum Pass Marks: 40% Lectures to be delivered:

45-55
 Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.

Instructions for candidates: Candidates are required to attempt one question each from sections
A, B, C and D of the question paper and the entire section E.

SECTION-A

Minimization and Design of Combinational Circuits:- minimization with theorems ,

Karnaugh Map, Variable -entered mapping and Tabulation method,

MSI and LSI Circuits and Applications:- Arithmetic circuits , Comparators , Multiplexers ,
Code converters, EXOR AND-OR-INVERT Gates, Wired Logic, TRI -STATE BUS SYSTEM ,
Propagation Delay

SECTION-B

SEQUENTIAL MACHINE FUNDAMENTALS: Need for sequential circuits, Distinction

between combinational and sequential circuits, Concept of memory, Binary Cell, Classification
of sequential machines, Flip-Flop, Design of clocked Flop-Flops, Conversion of Flip- Flops.

TRADITIONAL APPROCH TO SEQUENTIAL ANALYSIS AND DESIGN: State

Diagram, Analysis, Design of Synchronous sequential circuits, State Reduction, Minimizing the
next state decoder, Out put decoder design, Counters, Design of Single Mode, Multi Mode
Counters, Ring Counters. Shift Registers.

SECTION-C

MULTI INPUT SYSTEM CONTROLLER DESIGN: System Controllers, timing and

frequency considerations, MDS Diagram Generation, Synchronizing to systems and choosing
controller Architecture, State Assignment ,Next State Decoder, Next State decoder maps,
Output Decoder , Control and display,

SYSTEM CONTROLLER UTILIZING COMBINATION MSI/LSI CIRCUITS: Using the

MSI decoders in system controller, MSI multiplexes in system controller, Indirect- Addressed
Multiplexer Configuration.

SECTION-D

ASYNCHRONOUS FINITE-STATE MACHINES: Introduction, Asynchronous Analysis,

The Design of Synchronous Machines, Cycles and races, Hazards, Read only memories, ROM'S
PROMS and applications, Using the ROM random logic, Programmed Logic arrays,
Applications of PLA

References:

1. Wiilian I Fletcher, “An Engineering Approach to Digital Design,” PHI

2. Morris Mano and Charles R. Kime, “Logic and Computer Design Fundamentals,”

MEC-216 ADVANCED MICROPROCESSORS AND INTERFACING

LTP
3-1-0

Maximum Marks:70 Maximum Time: 3 Hrs.

Minimum Pass Marks: 40% Lectures to be delivered: 45-55

Instructions for paper-setter: The question paper will consist of five sections A, B, C, D and E.
Sections A, B, C and D will have two questions from the respective sections of the syllabus. Section E
will have one question with 10 short answer objective type parts, which will cover the entire syllabus
uniformly. All questions will carry same marks.
Instructions for candidates: Candidates are required to attempt one question each from sections A, B,
C and D of the question paper and the entire section E.

SECTION-A

Introduction to Microprocessors: Types of Processors, 16 Bit Microprocessors, Features and

Internal Architecture of Microprocessor 8086, Register Organization and Block Diagram of 8086
Microprocessors. Addressing Modes of 8086, Pin Configuration of 8086, Maximum and Minimum Mode,
8284 Clock Generator, 8288 Bus Controller.

SECTION-B
 Instruction Set: 8086 Instruction Groups, Addressing Mode Byte, Segment Register Selection,
Segment Override and 8086 Instructions.

Debug and Assembler: Debug Commands, Assembler Directives, Operators, Assembly

Language Programming of 8086.

SECTION-C

Memory and I/O Interfacing: Interfacing EPROM and RAM to 8086. I/O Interfacing
Techniques. Interfacing of PPI 8255, Programmable DMA Controller 8237, Programmable
Interrupt Controller 8259.

SECTION-D

32-Bit Microprocessors: Introduction, features, architectures and addressing modes of 386,

486 and Pentium Microprocessors.

References:

1. Badri Ram, “Advanced Microprocessors and Interfacing,” Tata McGraw hill

2. Gilmore, “Microprocessor Principles and Applications,” Tata McGraw Hill

3. Walter A. Tribel and Avtar Singh, “8088 and 8086 Microprocessor, PHI

4. B. Bray, “Advanced Microprocessor and Interfacing,”