Introduction to

Digital System Design

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by P. Chu
 Outline
1. Why Digital?
2. Device Technologies
3. System Representation
4. Abstraction
5. Development Tasks
6. Development Flow

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by P. Chu
 1. Why Digital

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by P. Chu
 Advantages
• Advantage of digital devices
– Reproducibility of information
– Flexibility and functionality: easier to store, transmit
and manipulate information
– Economy: cheaper device and easier to design
• Moore’s law
– Transistor geometry
– Chips double its density (number of transistor) in
every 18 months
– Devices become smaller, faster and cheaper
– Now a chip consists of hundreds of million gates
– And we can have a “wireless-PDA-MP3-player-
camera-GPS-cell-phone” gadget very soon
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 Applications of digital systems
• “Digitization” has spread to a wide range of
applications, including information (computers),
telecommunications, control systems etc.
• Digital circuitry replaces many analog systems:
– Audio recording: from tape to music CD to MP3
(MPEG Layer 3) player
– Image processing: from silver-halide film to digital
camera
– Telephone switching networks
– Control of mechanical system: e.g., “flight-by-wire”
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 e.g, digital circuit in a wireless
communication
transmitter
system

A Error
Data Data
info / correction Modulation
compression encryption
D coding

digital implementation

D Error
Data de- Data De-
info / correction
compression decryption modulation
A de-coding

digital implementation

receiver
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 e.g, digital circuit in a control
system

Sen
A D sor
actu
/ Controller / Plant
ator output
D A

set point digital

implementation

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 How to implement a digital system
• No two applications are identical and every one
needs certain amount of customization
• Basic methods for customization
– “General-purpose hardware” with custom software
• General purpose processor: e.g., performance-oriented
processor (e.g., Pentium), cost-oriented processor
(e.g., PIC micro-controller)
• Special purpose processor: with architecture to perform
a specific set of functions: e.g., DSP processor (to do
multiplication-addition), network processor (to do
buffering and routing), “graphic engine” (to do 3D
rendering)
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 – Custom hardware
– Custom software on a custom processor (known as
hardware-software co-design)
• Trade-off between Programmability, Coverage,
Cost, Performance, and Power consumption
• A complex application contains many different
tasks and use more than one customization
methods

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 2. Device Technologies

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by P. Chu
 Fabrication of an IC
• Transistors and connection are made from many layers
(typical 10 to 15 in CMOS) built on top of one another
• Each layer has a special pattern defined by a mask
• One important aspect of an IC is the length of a smallest
transistor that can be fabricated
– It is measured in micron (μm, 10-6 meter)
– E.g., we may say an IC is built with 0.50 μm process
– The process continues to improve, as witnessed by
Moore’s law
– The state-of-art process approaches less than
a fraction of 0.1 μm (known as deep sub-micron)

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 Classification of device
technologies
• Where customization is done:
– In a fab (fabrication facility): ASIC (Application
Specific IC)
– In the “field”: non-ASIC
• Classification:
– Full-custom ASIC
– Standard cell ASIC
– Gate array ASIC
– Complex field programmable logic device
– Simple field programmable logic device
– Off-the-shelf SSI (Small Scaled IC)/MSI (Medium
Scaled IC) components
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 Full-custom ASIC
• All aspects (e.g., size of a transistor) of a
circuit are tailored for a particular application.
• Circuit fully optimized
• Design extremely complex and involved
• Only feasible for small components
• Masks needed for all layers

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 Standard-Cell ASIC
• Circuit made of a set of pre-defined logic,
known as standard cells
• E.g., basic logic gates, 1-bit adder, D FF etc
• Layout of a cell is pre-determined, but layout
of the complete circuit is customized
• Masks needed for all layers

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 Gate array ASIC
• Circuit is built from an array of a single type of
cell (known as base cell)
• Base cells are pre-arranged and placed in
fixed positions, aligned as one- or two-
dimensional array
• More sophisticated components (macro cells)
can be constructed from base cells
• Masks needed only for metal layers
(connection wires)
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Complex Field Programmable Device
• Device consists of an array of generic logic cells
and general interconnect structure
• Logic cells and interconnect can be “programmed”
by utilizing “semiconductor fuses or “switches”
• Customization is done “in the filed”
• Two categories:
– CPLD (Complex Programmable Logic Device)
– FPGA (Field Programmable Gate Array)
• No custom mask needed
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 Simple Field Programmable Device

• Programmable device with simple internal

structure
• E.g.,
– PROM (Programmable Read Only Memory)
– PAL (Programmable Array Logic)
• No custom mask needed
• Replaced by CPLD/FPGA

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 SSI/MSI components
• Small parts with fixed, limited functionality
• E.g., 7400 TTL series (more than 100 parts)
• Resource (e.g., power, board area,
manufacturing cost etc.) is consumed by
“package” but not “silicon”
• No longer a viable option

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 Three viable technologies
• Standard Cell ASIC
• Gate Array ASIC
• FPGA/CPLD

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 Comparison of technology
• Area (Size): silicon “real-estate”
– Standard cell is the smallest since the cells and
interconnect are customized
– FPGA is the largest
• Overhead for “programmability”
• Capacity cannot be completely utilized
• Speed (Performance)
– Time required to perform a task
• Power
• Cost

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 Cost
• Types of cost:
– NRE (Non-Recurrent Engineering) cost:
one-time, per-design cost
– Part cost: per-unit cost
– Time-to-market “cost” loss of revenue
• Standard cell: high NRE, small part cost
and large lead time
• FPGA: low NRE, large part cost and
small lead time
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 Graph of per-unit cost

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 Summary of technology

• Trade-off between optimal use of hardware

resource and design effort/cost
• No single best technology
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 3. System Representation
(View)

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• View: different perspectives of a system
• Behavioral view:
– Describe functionalities and i/o behavior
– Treat the system as a black box
• Structural view:
– Describe the internal implementation
(components and interconnections)
– Essentially block diagram
• Physical view:
– Add more info to structural view: component
size, component locations, routing wires
– E.g., layout of a print circuit board
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 e.g., structural and physical view

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 4. Abstraction

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• How to manage complexity for a chip with 10
million transistors?
• Abstraction: simplified model of a system
– show the selected features
– Ignore associated detail
• E.g., timing of
an inverter

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• Level of abstractions
– Transistor level
– Gate level
– Register transfer (RT) level
– Processor level
• Characteristics of each level
– Basic building blocks
– Signal representation
– Time representation
– Behavioral representation
– Physical representation.

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 Summary

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by P. Chu
 RT level
• RT (Register Transfer) is a misleading
term
• Should use “module-level”
• Two meanings:
– Loosely: represent the module level
– Formally: a design methodology in which the
system operation is described by how the
data is manipulated and moved among
registers

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• View and abstraction
are two independent
aspects.
• Combined in a Y-
chart

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 5. Development Tasks

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• Developing a digital system is a refining
and validating process
• Main tasks:
– Synthesis
– Physical design
– Verification
– Testing

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 Synthesis
• A refinement process that realizes a description
with components from the lower abstraction
level.
• The resulting description is a structural view in
the lower abstraction level
• Type of synthesis:
– High-level synthesis
– RT level synthesis
– Gate level synthesis
– Technology mapping

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 Physical Design
• Placement and routing
– Refining from structural view to physical view
– Derive lay out of a netlist
• Circuit extraction:
– Determine the wire resistance of capacitance
• Others
– Derivation of power grid and clock distribution
network, assurance of signal integrity etc.

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 Verification
• Check whether a design meets the
specification and performance goals.
• Concern the correctness of the initial
design and the refinement processes
• Two aspects
– Functionality
– Performance (timing)

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 Method of Verification
• Simulation
– spot check: cannot verify the absence of errors
– Can be computation inensive
• Timing analysis
– Just check delay
• Formal verification
– apply formal math techniques determine its property
– E.g, equivalence checking
• Hardware emulation

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 Testing
• Testing is the process of detecting
physical defects of a die or a package
occurred at the time of manufacturing
• Testing and verification are different tasks.
• Difficult for large circuit
– Need to add auxiliary testing circuit in design
– E.g., built-in self test (BIST), scan chain etc.

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 Limitation of EDA software
• EDA (Electronic Design Automation)
• EDA software can automate some tasks
• Can software replace human hardware
designer? (e.g., C-program to chip)
• Synthesis software
– should be treated as a tool to perform
transformation and local optimization
– cannot alter the original architecture or
convert a poor design into a good one

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 Development Flow

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• Medium design
data file process

targeting FPGA
Synthesis Physical Design Verification

• Circuit up to
RTL 1 1

50,000 gates description testbench

synthesis 3 simulation 2

netlist delay file

placement & 54 simulation 4

routing

configuration delay file

file

device simulation/
programming 7 timing 6
analysis

FPGA 8
chip

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 Additional tasks
• Large design targeting FPGA
– Design partition
– More verification
• Large design targeting ASIC
– Thorough verification
– Testing
– Physical design

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 Goal of this course
• Goal:
– Systematically develop efficient, portable RT level
designs that can be easily integrated into a larger
system
• Design for efficiency
• Design for “large”
– Large module, large system, overall development
process
• Design for portability
– Device independent, software dependent, design
reuse
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by P. Chu