UNIT-2

Embedded Processors
• Processors are the main functional units of an
embedded board, and are primarily responsible for
processing instructions and data.
• An electronic device contains at least one master
processor, acting as the central controlling device, and
can have additional slave processors that work with and
are controlled by the master processor.
• These slave processors may either extend the
instruction set of the master processor or act to manage
memory, buses, and I/O (input/output) devices.
• There are literally hundreds of embedded processors
available
• embedded processors can be separated into various
“groups” called architectures
• What differentiates one processor group’s architecture
from another is the set of machine code instructions
that the processors within the architecture group can
execute.
• Processors are considered to be of the same
architecture when they can execute the same set of
machine code instructions
ISA Architecture Models
 • An instruction set architecture (ISA) is an abstract
model of a computer. It is also referred to
as architecture or computer architecture.
• A realization of an ISA is called an implementation. An
ISA permits multiple implementations that may vary
in performance, physical size, and monetary cost
(among other things); because the ISA serves as the
interface between software and hardware.
• Software that has been written for an ISA can run on
different implementations of the same ISA.
• The ISA defines such features as the operations that can
be used by programmers to create programs for that
architecture, the operands (data) that are accepted and
processed by an architecture, storage, addressing
modes used to gain access to and process operands, and
the handling of interrupts.
• ISA implementation is a determining factor in defining
important characteristics of an embedded design, such
as performance, design time, available functionality, and
cost.
• An ISA defines everything a machine
language programmer needs to know in order to
program a computer
Operations
 • Operations are made up of one or more instructions
that execute certain commands
Types of Operations
Operations are the functions that can be performed on the
data, and they typically include
• computations (math operations)
• movement (moving data from one memory
location/register to another)
• branches conditional/unconditional moves to another
area of code to process)
• input/output operations (data transmitted between I/O
components and master processor)
• context switching operations (where location register
information is temporarily stored when switching to
some routine to be executed and after execution, by the
recovery of the
temporarily stored information, there is a switch back to
executing the original instruction
stream).
Sample ISA operations:
Operation Formats
• The format of an operation is the actual number and
combination of bits (1’s and 0’s) that represent the
operation, and is commonly referred to as the operation
code or opcode.
Operands
• Operands are the data that operations manipulate. An
ISA defines the types and formats of operands for a
particular architecture.
• For example, in the case of the MPC823
(Motorola/Freescale PowerPC), SA-1110 (Intel
StrongARM), and many other architectures, the ISA
defines simple operand types of bytes (8 bits), halfwords
(16 bits), and words (32 bits).
• An ISA also defines the operand formats (how the data
looks) that a particular architecture can support, such as
binary, decimal and hexadecimal.
 Example:
MOV registerX, 10d ; Move decimal value 10 into
register X
MOV registerX, $0Ah ; Move hexadecimal value A
(decimal 10) to register X
MOV registerX, 00001010b ; Move binary value
00001010 (decimal 10 ) to register X
Storage:
• The ISA specifies the features of the programmable
storage used to store the data being operated on,
primarily:
1. The organization of memory used to store operands.
Memory is simply an array of programmable storage,
that stores data, including operations, operands, and so
on.
• The indices of this array are locations referred to as
memory addresses, where each location is a unit of
memory that can be addressed separately.
• The actual physical or virtual range of addresses
available to a processor is referred to as the address
space.
• An ISA defines specific characteristics of the address
space, such as whether it is:
• Linear. A linear address space is one in which specific
memory locations are represented incrementally,
typically starting at “0”.
Segmented
• A segmented address space is a portion of memory that
is divided into sections called segments.
• Specific memory locations can only be accessed by
specifying a segment identifier, a segment number that
can be explicitly defined or implicitly obtained from a
register, and specifying the offset within a specific
segment within the segmented address space.
• The offset within the segment contains a base address
and a limit, which map to another portion of memory
that is set up as a linear address space. If the offset is
less than or equal to the limit, the offset is added to the
base address, giving the unsegmented address within
the linear address space.
• An important note regarding ISAs and memory is that
different ISAs not only define where data is stored, but
also how data is stored in memory—specifically in what
order the bits (or bytes) that make up the data is stored,
or byte ordering.
• The two byte-ordering approaches are big-endian, in
which the most significant byte or bit is stored first, and
 little-endian, in which the least significant bit or byte is
stored first.
Example:
• 68000 and SPARC are big-endian
• x86 is little-endian
2. Register Set
• A register is simply fast programmable memory
normally used to store operands that are immediately or
frequently used.
• A processor’s set of registers is commonly referred to as
the register set or the register file.
• Different processors have different register sets, and the
number of registers in their sets vary between very few
to several hundred (even over a thousand).
3. How Registers Are Used:
• An ISA defines which registers can be used for what
transactions, such as special purpose, floating point, and
which can be used by the programmer in a general
fashion (general purpose registers).
• Addressing Modes
Addressing modes define how the processor can
access operand storage. In fact, the
 usage of registers is partly determined by the ISA’s
Memory Addressing Modes.
The two most common types of addressing mode
models are:
• Load-Store Architecture, which only allows operations
to process data in registers, not anywhere else in
memory. For example, the PowerPC architecture has
only one addressing mode for load and store
instructions: register plus displacement (supporting
register indirect with immediate index, register indirect
with index, etc.).
• Register-Memory Architecture, which allows operations
to be processed both within registers and other types of
memory. Intel’s i960 Jx processor is an example of an
addressing mode architecture that is based upon the
register-memory model (supporting absolute, register
indirect, etc.).
Interrupts and Exception Handling:
• Interrupts (also referred to as exceptions or traps
depending on the type) are mechanisms that stop the
standard flow of the program in order to execute
another set of code in response to some event, such as
problems with the hardware, resets, and so forth.
• The ISA defines what if any type of hardware support a
processor has for interrupts.
There are several different ISA models that architectures.
1. Application-Specific ISA Models
• Controller Model
• Datapath Model
• Finite State Machine with Datapath (FSMD) Model
• Java Virtual Machine (JVM) Model
2. General-Purpose ISA models
• Complex Instruction Set Computing (CISC) Model
Reduced Instruction Set Computing (RISC) Model
3. Instruction-Level Parallelism ISA Models
• Single Instruction Multiple Data (SIMD) Model
• Superscalar Machine Model
• Very Long Instruction Word Computing (VLIW) Model
Internal Processor Design:
Internal processor components consists of
• CPU
• Memory
• Input components
• Output components
• Buses
These internal components are the basis of the von
Neumann model

Central Processing Unit (CPU)

• CPU is the processing unit within a processor.
• The CPU is responsible for executing the cycle of
fetching, decoding, and executing.
• This three-step process is commonly referred to as a
three stage pipeline.
• These cycles are implemented through some
combination of four major CPU components:
• The arithmetic logic unit (ALU) – implements the ISA’s
operations
• Registers – a type of fast memory
• The control unit (CU) – manages the entire fetching and
execution cycle
• The internal CPU buses – interconnect the ALU, registers,
and the CU
The MPC860 CPU – the PowerPC core

Internal CPU Buses

• The CPU buses are the mechanisms that interconnect
the ALU, the CU, and registers
• Buses are simply wires that interconnect the various
other components within the CPU.
Each bus’s wire is typically divided into logical functions,
such as
• Data (which carries data, bi-directionally, between
registers and the ALU)
• Address (which carries the locations of the registers that
contain the data to be transferred)
• Control (which carries control signal information, such
as timing and control signals, between the registers, the
ALU, and the CU)
• In the PowerPC Core, there is a Control Bus that carries
the control signals between the ALU, CU, and registers.
• In PowerPC source buses are the data buses that carry
the data between registers and the ALU. There is an
additional bus called the write-back which is dedicated
to writing back data received from a source bus directly
back from the load/store unit to the fixed or floating
point registers .
• The arithmetic logic unit (ALU) implements the
comparison, mathematical and logical operations
defined by the ISA.
• The format and types of operations implemented in the
CPU’s ALU can vary depending on the ISA.
• The ALU is responsible for accepting multiple n-bit
binary operands and performing any logical (AND, OR,
NOT, etc.), mathematical (+, –, *, etc.), and comparison
(=, <, >, etc.) operations on these operands.
• In the PowerPC core, the ALU is part of the “Fixed Point
Unit” that implements all fixed-point instructions other
than load/store instructions.
• The ALU is responsible for fixed-point logic, add, and
subtract instruction implementation.
• In the case of the PowerPC, generated results of the
ALU are stored in an Accumulator.
• Also, the PowerPC has an IMUL/IDIV unit (essentially
another ALU) specifically for performing multiplication
and division operations.
Registers
• Registers are simply a combination of various flip-flops
that can be used to temporarily store
data or to delay signals.
• A storage register is a form of fast programmable
internal processor memory usually used to temporarily
store, copy, and modify operands that are immediately
or frequently used by the system.
• Shift registers delay signals by passing the signals
between the various internal flip-flops with every clock
pulse.
• ISA designs do not use all registers in the same way to
process the data, storage typically falls under one of two
categories, either general purpose or special purpose
• General purpose registers can be used to store and
manipulate any type of data determined
by the programmer, whereas special purpose registers
can only be used in a manner
 specified by the ISA, including holding results for specific
types of computations, having predetermined flags
(single bits within a register that can act and be
controlled independently),acting as counters (registers
that can be programmed to change states—that is,
increment—asynchronously or synchronously after a
specified length of time), and controlling I/O
ports(registers managing the external I/O pins
connected to the body of the processor and to board
I/O).
• Shift registers are inherently special purpose, because of
their limited functionality.

• The PowerPC Core has a “Register Unit” which contains

all registers visible to a user.
• PowerPC processors generally have two types of
registers: general-purpose and special-purpose (control)
registers.
Control Unit (CU)
• The control unit (CU) is primarily responsible for
generating timing signals, as well as controlling and
coordinating the fetching, decoding, and execution of
instructions in the CPU.
• After the instruction has been fetched from memory
and decoded, the control unit then
determines what operation will be performed by the
ALU, and selects and writes signals
 appropriate to each functional unit within or outside of
the CPU (i.e., memory, registers,
ALU, etc.).
• PowerPC core’s CU is called a “sequencer unit,” and is
the heart of the PowerPC core.
• The sequencer unit is responsible for managing the
continuous cycle of fetching, decoding, and executing
instructions while the PowerPC has power, including
such tasks as:
• Provides the central control of the data and instruction
flow among the other major units within the PowerPC
core (CPU), such as registers, ALU and buses.
• Implements the basic instruction pipeline. Fetches
instructions from memory to issue these instructions to
available execution units.
• Maintains a state history for handling exceptions.
The CPU and the System (Master) Clock
• A processor’s execution is ultimately synchronized by an
external system or master clock ,located on the board.
• The master clock is an oscillator along with a few other
components, such as a crystal.
• It produces a fixed frequency sequence of regular
on/off pulse signals
On-Chip Memory
• Embedded platforms have a memory hierarchy, a
collection of different types of memory, each with
unique speeds, sizes, and usages
• Some of this memory can be physically integrated on
the processor, such as registers, read-only memory
(ROM), certain types of random access memory (RAM),
and level-1 cache.

Read-Only Memory (ROM)

• On-chip ROM is memory integrated into a processor
that contains data or instructions that remain even
when there is no power in the system, due to a small,
longer-life battery, and therefore is considered to be
nonvolatile memory (NVM).
• The content of on-chip ROM usually can only be read by
the system it is used in.
Most common types of on-chip ROM include:
• MROM (mask ROM), which is ROM (with data content)
that is permanently etched into the microchip during the
manufacturing of the processor, and cannot be modified
later.
• PROMs (programmable ROM), or OTPs (one-time
programmables), which is a type of ROM that can be
integrated on-chip, that is one-time programmable by a
PROM programmer (in other words, it can be
programmed outside the manufacturing factory).
• EPROM (erasable programmable ROM), which is ROM
that can be integrated on a processor, in which content
can be erased and reprogrammed more than once (the
number of times erasure and re-use can occur depends
on the processor). The content of EPROM is written to
the device using special separate devices and erased,
Either selectively or in its entirety using other devices
that output intense ultraviolet Light into the processor’s
built-in window.
• EEPROM (electrically erasable programmable ROM),
which, like EPROM, can be erased and reprogrammed
more than once. The number of times erasure and re-
use can occur depends on the processor. Unlike
EPROMs, the content of EEPROM can be written and
erased without using any special devices while the
embedded system is functioning. With EEPROMs,
 erasing must be done in its entirety, unlike EPROMs,
which can be erased selectively.
Random-Access Memory (RAM)
• RAM (random access memory), commonly referred to as
main memory, is memory in which
any location within it can be accessed directly
(randomly, rather than sequentially from some starting
point), and whose content can be changed more than
once (the number depending on the hardware).
• Unlike ROM, contents of RAM are erased if RAM loses
power, meaning RAM is volatile. The two main types of
RAM are static RAM (SRAM) and dynamic RAM
(DRAM).
Cache (Level-1 Cache)
• Cache is the level of memory between the CPU and main
memory in the memory hierarchy.
• Cache can be integrated into a processor or can be off-
chip. Cache existing on-chip is commonly referred to as
level-1 cache, and SRAM memory is usually used as
level-1 cache.
• Because (SRAM) cache memory is typically more
expensive due to its speed,processors usually have a
small amount of cache, whether on-chip or off-chip.
Data is usually stored in cache in one of three schemes:
• Direct Mapped, where data in cache is located by its
associated block address in memory (using the “tag”
portion of the block).
• Set Associative, where cache is divided into sets into
which multiple blocks can be placed. Blocks are located
according to an index field that maps into a cache’s
particular set.
• Full Associative, where blocks are placed anywhere in
cache, and must be located by searching the entire
cache every time.
On-Chip Memory Management
• Many different types of memory can be integrated into
a system, and there are also differences in how software
running on the CPU views memory addresses
(logical/virtual addresses) and the actual physical
memory addresses (the two-dimensional array or row
and column).
• Memory managers are ICs designed to manage these
issues, and in some cases are integrated onto the
master processor.
• The two most common types of memory managers that
are integrated into the master processor are memory
controllers (MEMC) and memory management units
(MMUs).
• A memory controller (MEMC) is used to implement and
provide glueless interfaces to the different types of
memory in the system, such as cache, SRAM, and
DRAM, synchronizing access to memory and verifying
the integrity of the data being transferred.
• Memory management units (MMUs) are used to
translate logical addresses into physical
addresses (memory mapping), as well as handle memory
security, control cache, handle
bus arbitration between the CPU and memory, and
generate appropriate exceptions.
Memory Organization
• Memory organization includes not only the makeup of
the memory hierarchy of the particular platform, but
also the internal organization of memory, specifically
what different portions of memory may or may not be
used for, as well as how all the different types of
memory are organized and accessed by the rest of the
system.
Processor Input/Output (I/O)
• Input/output components of a processor are responsible
for moving information to and from the processor’s
other components to any memory and I/O outside of
the processor, on the board. Processor I/O can either be
 input components that only bring information into the
master processor, output components that bring
information out of the master processor, or components
that do both.
Managing I/O Data: Serial vs. Parallel I/O
• Data can be transmitted between two devices in one of
three directions: one way, in both directions but at
separate times because they share the same
transmission line, and in both directions simultaneously.
• A simplex scheme for serial I/O data communication is
one in which a data stream can only be transmitted—
and thus received—in one direction as shown in Fig a.
• A half duplex scheme is one in which a data stream can
be transmitted and received in either direction, but in
only one direction at any one time as shown in Fig b.
• A full duplex scheme is one in which a data stream can
be transmitted and received in either direction,
simultaneously as shown in Fig c.

Fig a.
 Fig b.

Fig c.

Processor Buses:
• Like the CPU buses, the processor’s buses interconnect
the processor’s major internal components (in this case
the CPU, memory and I/O as shown in Figure 4-70)
together, carrying signals between the different
components
• In the case of the MPC860, the processor buses include
the U-bus interconnecting the system interface unit(SIU),
the communications processor module (CPM), and the
 PowerPC core. Within the CPM, there is a peripheral bus,
as well. Of course, this includes the buses within the
CPU.
Processor Performance
• There are several measures of processor performance,
but are all based upon the processor’s behavior over a
given length of time. One of the most common
definitions of processor performance is a processor’s
throughput, the amount of work the CPU completes in a
given period of time.
• CPU throughput (in bytes/sec or MB/sec) = 1 / CPU
execution time = CPU performance
• CPU execution time in seconds per program = (total
number of instructions per program or instruction count)
* (CPI in number of cycle cycles/instruction) * (clock
period in seconds per cycle) = ((instruction count) * (CPI
in number of cycle cycles/instruction)) / (clock rate in
MHz)
• CPI (average number of clock cycles per instruction) can
be determined CPI =∑ (CPI per instruction * instruction
frequency)
Other definitions of performance besides throughput
include:
• A processor’s responsiveness, or latency, which is the
length of elapsed time a processor takes to respond to
some event.
• A processor’s availability,which is the amount of time
the processor runs normally without failure; reliability,
the average time between failures or MTBF (mean time
between failures); and recoverability, the average time
the CPU takes to recover from failure or MTTR (mean
time to recover).
• One of the most common performance measures used
for processors in the embedded market is millions of
instructions per seconds or MIPS.
• MIPS = Instruction Count / (CPU execution time * 106) =
Clock Rate / (CPI * 106)
• The MIPS performance measure gives the impression
that faster processors have higher MIPS values, since
part of the MIPS formula is inversely proportional to the
CPU’s execution time.
• MIPS = Instruction Count / (CPU execution time * 106)
= Clock Rate / (CPI * 106)

Board Memory:
 **Note: Types of on-chip memory that can be
integrated into a processor were introduced in page
No.9.
Board memory, which is memory connected directly to
or integrated in the processor such as ROM, RAM, and
level-1 cache.
It is memory that is typically located outside of the
processor, or that can both be either integrated into the
processor or located outside the processor..
This includes other types of primary memory, such as
ROM, level-2+ cache, and main memory, and
secondary/tertiary memory, which is memory that is
connected to the board but not the master processor
directly, such as CD-ROM, floppy drives, hard drives, and
tape.
• Primary memory is typically a part of a memory
subsystem shown in below Figure made up of three
components:
• The memory IC
• An address bus
• A data bus
 A memory IC is made up of three units: the memory
array, the address decoder, and the data interface.
The memory array is actually the physical memory that
stores the data bits. While the master processor, and
programmers, treat memory as a one-dimensional
array,where each cell of the array is a row of bytes and
the number of bits per row can vary, in reality physical
memory is a two-dimensional array made up of memory
cells addressed by aunique row and column, in which
each cell can store 1 bit .
The locations of each of the cells within the two-
dimensional memory array are commonly referred to as
the physical memory addresses, made up of the column
and row parameters.
Memory Management of External Memory
There are several different types of memory that can be
integrated into a system, and there are also differences in how
software running on the CPU views logical/virtual memory
addresses and the actual physical memory addresses—the
two-dimensional array or row and column. Memory
managers are ICs designed to manage these issues.

The two most common types of memory managers found on

an embedded board are memory controllers (MEMC) and
memory management units (MMUs).

A memory controller (MEMC), shown in Figure, is used to

implement and provide glueless interfaces to the different
types of memory in the system, such as SRAM and DRAM,
synchronizing access to memory and verifying the integrity of
the data being transferred. Memory controllers access memory
directly with the memory’s own physical two- dimensional
addresses. The controller manages the request from the master
processor and accesses the appropriate banks, awaiting
feedback and returning that feedback to the master processor.
In some cases, where the memory controller is mainly
managing one type of memory, it may be referred to by that
memory’s name, such as DRAM controller, cache controller,
and so forth.
Memory management units (MMUs) mainly allow for the
flexibility in a system of having a larger virtual memory
(abstract) space within an actual smaller physical memory. An
MMU, shown in below Figure, can exist outside the master
processor and is used to translate logical (virtual) addresses
into physical addresses (memory mapping), as well as handle
memory security (memory protection), controlling cache,
handling bus arbitration between the CPU and memory, and
generating appropriate exceptions.

In the case of translated addresses, the MMU can use level-1

cache or portions of cache
allocated as buffers for caching address translations,
commonly referred to as the translation
lookaside buffer or TLB, on the processor to store the
mappings of logical addresses to physical addresses. MMUs
also must support the various schemes in translating
addresses, mainly segmentation, paging, or some
combination of both schemes.