Single Phase, Multifunction Metering IC

with Neutral Current Measurement

Data Sheet ADE7953
FEATURES The device incorporates three Σ-Δ ADCs with a high accuracy
Highly accurate; supports EN 50470-1, EN 50470-3, IEC 62053- energy measurement core. The second input channel simulta-
21, IEC 62053-21, IEC 62053-22, and IEC 62053-23 standards neously measures neutral current and enables tamper detection
Measures active, reactive, and apparent energy; sampled and neutral current billing. The additional channel incorporates
waveform; current and voltage rms a complete signal path that allows a full range of measurements.
Provides a second current input for neutral current Each input channel supports independent and flexible gain stages,
measurement making the device suitable for use with a variety of current sensors
Less than 0.1% error in active and reactive energy such as current transformers (CTs) and low value shunt resistors.
measurements over a dynamic range of 3000:1 Two on-chip integrators facilitate the use of Rogowski coil sensors.
Less than 0.2% error in instantaneous IRMS measurement The ADE7953 provides access to on-chip meter registers via a
over a dynamic range of 1000:1 variety of communication interfaces including SPI, I2C, and UART.
Provides apparent energy measurement and instantaneous Two configurable low jitter pulse output pins provide outputs that
power readings are proportional to active, reactive, or apparent energy, as well as
1.23 kHz bandwidth operation current and voltage rms. A full range of power quality information
Flexible PGA gain stage (up to ×22) such as overcurrent, overvoltage, peak, and sag detection are
Includes internal integrators for use with Rogowski coil sensors accessible via the external IRQ pin. Independent active, reactive,
SPI, I2C, or UART communication and apparent no-load detections are included to prevent “meter
GENERAL DESCRIPTION creep.” Dedicated reverse power (REVP), zero-crossing voltage
(ZX), and zero-crossing current (ZX_I) pins are also provided. The
The ADE7953 is a high accuracy electrical energy measurement
ADE7953 energy metering IC operates from a 3.3 V supply voltage
IC intended for single phase applications. It measures line voltage
and is available in a 28-lead LFCSP package.
and current and calculates active, reactive, and apparent energy,
as well as instantaneous rms voltage and current.
FUNCTIONAL BLOCK DIAGRAM
REF RESET VDD VINTA VINTD

AIRMSOS
ADE7953
1.2V REF AVAGAIN
X2 AIRMS
LPF
LOW DIGITAL
NOISE AIGAIN INTEGRATOR
PRE-AMP
X2 AVRMS
IAP LPF
PGA ADC
IAN HPF
VRMSOS

APHCAL VGAIN AWGAIN AWATTOS CF1DEN

VP
PGA ADC
HPF LPF
DFC : CF1
VN
PHASE
A AND B CF2DEN
ACTIVE, REACTIVE AND
DATA
APPARENT ENERGIES AND AVARGAIN AVAROS
VOLTAGE/CURRENT RMS
IBP CALCULATION FOR PHASE B
COMPUTATIONAL
DFC : CF2
PGA ADC (SEE PHASE A FOR DETAILED
IBN BLOCK FOR TOTAL
DATA PATH).
REACTIVE POWER

CONFIGURATION REVP REVP

AND CONTROL ZX ZX
AGND ZX_I ZX_I
PEAK
UART SPI INTERFACE I2C ANGLE
DGND POWER FACTOR
SAG
09320-001

CLKIN CLKOUT IRQ CS MISO/ MOSI/ SCLK

SDA/Tx SCL/Rx

Figure 1.
Rev. C Document Feedback
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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADE7953* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017

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ADE7953 Data Sheet

TABLE OF CONTENTS
Features .....................................................................................1 Period Measurement ............................................................... 36
General Description ..................................................................1 Instantaneous Powers and Waveform Sampling ...................... 37
Functional Block Diagram.........................................................1 Power Factor ........................................................................... 38
Revision History ........................................................................3 Using the Line Cycle Accumulation Mode to Determine the
Specifications.............................................................................4 Power Factor........................................................................ 38

Timing Characteristics...........................................................6 Power Factor with No-Load Detection ................................ 38

Absolute Maximum Ratings ......................................................8 Angle Measurement............................................................. 39

ESD Caution ..........................................................................8 No-Load Detection.................................................................. 40

Pin Configuration and Function Descriptions...........................9 Setting the No-Load Thresholds .......................................... 40

Typical Performance Characteristics .......................................11 Active Energy No-Load Detection....................................... 40

Test Circuit ..............................................................................16 Reactive Energy No-Load Detection ................................... 41

Terminology ............................................................................17 Apparent Energy No-Load Detection .................................. 41

ADE7953 Power-Up Procedure ...............................................18 Zero-Crossing Detection ......................................................... 43

Required Register Setting.....................................................18 Zero-Crossing Output Pins.................................................. 43

Theory of Operation................................................................19 Zero-Crossing Interrupts..................................................... 43

Analog Inputs ......................................................................19 Zero-Crossing Timeout ....................................................... 44

Analog-to-Digital Conversion .............................................19 Zero-Crossing Threshold..................................................... 44

Current Channel ADCs .......................................................21 Voltage Sag Detection.............................................................. 45

Voltage Channel ADC..........................................................21 Setting the SAGCYC Register .............................................. 45

Reference Circuit .................................................................22 Setting the SAGLVL Register ............................................... 45

Root Mean Square Measurement.............................................23 Voltage Sag Interrupt ........................................................... 45

Current Channel RMS Calculation ......................................23 Peak Detection ........................................................................ 46

Voltage Channel RMS Calculation .......................................23 Indication of Power Direction ................................................. 47

Active Power Calculation.........................................................24 Reverse Power...................................................................... 47

Sign of Active Power Calculation .........................................25 Sign Indication .................................................................... 47

Active Energy Calculation....................................................25 Overcurrent and Overvoltage Detection ................................. 48

Active Energy Accumulation Modes....................................27 Setting the OVLVL and OILVL Registers ............................ 48

Reactive Power Calculation .....................................................28 Overvoltage and Overcurrent Interrupts ............................. 48

Sign of Reactive Power Calculation......................................28 Alternative Output Functions.................................................. 49

Reactive Energy Calculation ................................................29 ADE7953 Interrupts ................................................................ 50

Reactive Energy Accumulation Modes ................................30 Primary Interrupts (Voltage Channel and Current
Channel A) .......................................................................... 50
Apparent Power Calculation ....................................................31
Current Channel B Interrupts.............................................. 50
Apparent Energy Calculation...............................................31
Communicating with the ADE7953........................................ 51
Ampere-Hour Accumulation ...............................................32
Communication Autodetection ........................................... 51
Energy-to-Frequency Conversion............................................33
Locking the Communication Interface................................ 51
Pulse Output Characteristics................................................33
SPI Interface ........................................................................ 52
Energy Calibration...................................................................34
I2C Interface......................................................................... 53
Gain Calibration ..................................................................34
UART Interface.................................................................... 55
Phase Calibration .................................................................34
Communication Verification and Security .............................. 57
Offset Calibration ................................................................35
Rev. C | Page 2 of 72
Data Sheet ADE7953
Write Protection ..........................................................................57  ADE7953 Register Descriptions ............................................... 62 
Communication Verification.....................................................57  Layout Guidelines ........................................................................... 68 
Checksum Register .....................................................................58  Outline Dimensions ........................................................................ 69 
ADE7953 Registers .........................................................................60  Ordering Guide ........................................................................... 69 

REVISION HISTORY
12/2016—Rev. B to Rev. C Changes to Table 15 ........................................................................ 61
Changed CP-28-6 to CP-28-10 .................................... Throughout Changes to Table 18 ........................................................................ 62
Changes to Figure 4........................................................................... 9 Added Layout Guidelines Section................................................. 68
Changes to Period Measurement Section ....................................36 Updated Outline Dimensions........................................................ 69
Updated Outline Dimensions ........................................................69
Changes to Ordering Guide ...........................................................69 11/2011—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
11/2013—Rev. A to Rev. B Changes to Table 1 ............................................................................ 3
Changes to Features Section ............................................................ 1 Changes to Absolute Maximum Ratings Section ......................... 8
Changed Input Clock Frequency from 3.58 MHz (Max) to Changes to Table 5 ............................................................................ 9
3.54 MHz (Min)/3.58 MHz (Typ)/3.62 MHz (Max) .................... 5 Replaced Typical Performance Characteristics Section ............. 11
Changed tDAV from 80 ns (Min) to 80 ns (Max) ............................ 6 Changes to Figure 35 ...................................................................... 16
Changed tHD;DAT (Min) from 0 μs to 0.1 μs ..................................... 7 Added ADE7953 Power-Up Procedure Section ......................... 18
Changes to EPAD Note..................................................................... 9 Changes to Voltage Channel Section ............................................ 19
Changes to Figure 35 ......................................................................16 Changes to Current Channel RMS Calculation Section and
Changes to Current Channel ADCs Section and Voltage Voltage Channel RMS Calculation Section ................................. 23
Channel ADC Section ....................................................................21 Changes to Active Power Calculation Section ............................ 24
Changes to Figure 45 ......................................................................24 Changes to Active Energy Integration Time Under Steady
Changes to Figure 46 ......................................................................25 Load Section .................................................................................... 25
Changes to Current Channel Gain Adjustment Section ............34 Changes to Reactive Power Calculation Section ........................ 28
Changes to RMS Offsets Section ...................................................35 Changes to Reactive Energy Integration Time Under Steady
Changes to Equation 37 ..................................................................38 Load Section .................................................................................... 29
Changes to First Paragraph in No-Load Detection Section ......40 Changes to Figure 65 ...................................................................... 47
Changes to Communication Autodetection Section and Changes to Write Protection Section ........................................... 57
Locking the Communication Interface Section ..........................51 Replaced Checksum Register Section and added Figure 75 and
Changes to I2C Interface Section...................................................53 Figure 76 ........................................................................................... 58
Changes to Write Protection Section............................................57 Changes to Table 12 ........................................................................ 59
Changes to Figure 76 ......................................................................58 Changes to Table 14 ........................................................................ 60
Changes to Table 12 ........................................................................59 Changes to Table 15 ........................................................................ 61
Changes to Table 13 and Table 14 .................................................60 Replaced Interrupt Enable Section and Interrupt Status
Registers Section ............................................................................. 66

2/2011—Revision 0: Initial Version

Rev. C | Page 3 of 72
ADE7953 Data Sheet

SPECIFICATIONS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, TMIN to TMAX = −40°C to +85°C, Register Address 0x120
set to 0x30, unless otherwise noted.

Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
PHASE ERROR BETWEEN CHANNELS Line frequency = 45 Hz to 65 Hz, HPF on
Power Factor = 0.8 Capacitive ±0.05 Degrees Phase lead 37°
Power Factor = 0.5 Inductive ±0.05 Degrees Phase lag 60°
ACTIVE ENERGY MEASUREMENT
Active Energy Measurement Error 0.1 % Over a dynamic range of 3000:1, PGA = 1,
(Current Channel A) PGA = 22, integrator off
Active Energy Measurement Error 0.1 % Over a dynamic range of 1000:1, PGA = 1,
(Current Channel B) PGA = 16, integrator off
AC Power Supply Rejection VDD = 3.3 V ± 120 mV rms, 100 Hz
Output Frequency Variation 0.01 %
DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc
Output Frequency Variation 0.01 %
Active Energy Measurement Bandwidth 1.23 kHz −3 db
REACTIVE ENERGY MEASUREMENT
Reactive Energy Measurement Error 0.1 % Over a dynamic range of 3000:1, PGA = 1,
(Current Channel A) PGA = 22, integrator off
Reactive Energy Measurement Error 0.1 % Over a dynamic range of 1000:1, PGA = 1,
(Current Channel B) PGA = 16, integrator off
AC Power Supply Rejection VDD = 3.3 V ± 120 mV rms, 100 Hz
Output Frequency Variation 0.01 %
DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc
Output Frequency Variation 0.01 %
Reactive Energy Measurement 1.23 kHz −3 db
Bandwidth
RMS MEASUREMENT
IRMS and VRMS Measurement 1.23 kHz
Bandwidth
IRMS (Current Channel A) Measurement 0.2 % Over a dynamic range of 1000:1, PGA = 1,
Error PGA = 22, integrator off
IRMS (Current Channel B) and VRMS 0.2 % Over a dynamic range of 500:1, PGA = 1,
Measurement Error PGA = 16, integrator off
ANALOG INPUTS
Maximum Signal Levels ±500 mV peak Differential inputs: IAP to IAN, IBP to IBN
±500 mV peak Single-ended input: VP to VN, IBP to IBN
±250 mV peak Single-ended input: IAP to IAN
Input Impedance (DC)
IAP Pin 50 MΩ
IAN Pin 50 MΩ
IBP, IBN, VP, VN Pins 540 kΩ
ADC Offset Error Uncalibrated error (see the Terminology
section)
Current Channel B, Voltage Channel 0 ±10 mV
Current Channel A −12 mV PGA = 1
−1 mV PGA = 16, PGA = 22
Gain Error External 1.2 V reference
Current Channel A ±3 %
Current Channel B ±3 %
Voltage Channel ±3 %

Rev. C | Page 4 of 72
Data Sheet ADE7953
Parameter Min Typ Max Unit Test Conditions/Comments
ANALOG PERFORMANCE
Signal-to-Noise Ratio
Current Channel A 74 dB
Current Channel B 72 dB
Voltage Channel 70
Signal-to-Noise-and-Distortion Ratio
Current Channel A, Current Channel B 68 dB
Voltage Channel 65 dB
Bandwidth (−3 dB) 1.23 kHz
CF1 AND CF2 PULSE OUTPUTS
Maximum Output Frequency 206.9 kHz
Duty Cycle 50 % CF1 or CF2 frequency > 6.25 Hz
Active Low Pulse Width 80 ms CF1 or CF2 frequency < 6.25 Hz
Jitter 0.04 % CF1 or CF2 frequency = 1 Hz
Output High Voltage, VOH 2.4 V I SOURCE = 500 µA at 25°C
Output Low Voltage, VOL 0.4 V I SINK = 8 mA at 25°C
REFERENCE Nominal 1.2 V at REF pin
REF Input Voltage Range 1.19 1.2 1.21 V TMIN to TMax
Input Capacitance 10 pF
Reference Error ±0.9 mV TA = 25°C
Output Impedance 1.2 kΩ
Temperature Coefficient 10 50 ppm/°C
CLKIN/CLKOUT PINS All specifications CLKIN = 3.58 MHz
Input Clock Frequency 3.54 3.58 3.62 MHz
Crystal Equivalent Series Resistance 30 200 Ω
LOGIC INPUTS—RESET , CLKIN, CS, SCLK,
MOSI/SCL/Rx, MISO/SDA/Tx
Input High Voltage, VINH 2.4 V VDD = 3.3 V ± 10%
Input Low Voltage, VINL 0.8 V VDD = 3.3 V ± 10%
Input Current, I IN VIN = 0 V
MOSI/SCL/Rx, MISO/SDA/Tx, RESET −10 µA
CS, SCLK 1 µA
Input Capacitance, CIN 10 pF
LOGIC OUTPUTS—IRQ, REVP , ZX, ZX_I, VDD = 3.3 V ± 10%
CLKOUT, MOSI/SCL/Rx, MISO/SDA/Tx
Output High Voltage, VOH 3.0 V I SOURCE = 800 µA
Output Low Voltage, VOL 0.4 V I SINK = 2 mA
POWER SUPPLY For specified performance
VDD 3.0 V 3.3 V − 10%
3.6 V 3.3 V + 10%
I DD 7 9 mA

Rev. C | Page 5 of 72
ADE7953 Data Sheet
TIMING CHARACTERISTICS
SPI Interface Timing
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.

Table 2.
Parameter Description Min 1 Max1 Unit
t CS CS to SCLK edge 50 ns
t SCLK SCLK period 200 ns
t SL SCLK low pulse width 80 ns
t SH SCLK high pulse width 80 ns
t DAV Data output valid after SCLK edge 80 ns
t DSU Data input setup time before SCLK edge 70 ns
t DHD Data input hold time after SCLK edge 5 ns
t DF Data output fall time 20 ns
t DR Data output rise time 20 ns
t SR SCLK rise time 20 ns
t SF SCLK fall time 20 ns
t DIS MISO disabled after CS rising edge 5 40 ns
t SFS CS high after SCLK edge 0 ns
t SFS_LK CS high after SCLK edge (when writing to 1200 ns
COMM_LOCK bit)

1 Min and max values are typical minimum and maximum values.

SPI Interface Timing Diagram

CS

tCS tSCLK
tSFS_LK
tSFS

SCLK

tSL
tSH tSF tSR
tDAV
tDIS

MISO MSB OUT INTERMEDIATE BITS LSB OUT

tDF tDR

INTERMEDIATE BITS

MOSI MSB IN LSB IN

tDSU
09320-003

tDHD

Figure 2. SPI Interface Timing

Rev. C | Page 6 of 72
Data Sheet ADE7953
I2C Interface Timing
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.

Table 3.
Standard Mode Fast Mode
Parameter Description Min1 Max1 Min1 Max1 Unit
fSCL SCL clock frequency 0 100 0 400 kHz
tHD;STA Hold time for a start or repeated start condition 4.0 0.6 μs
tLOW Low period of SCL clock 4.7 1.3 μs
tHIGH High period of SCL clock 4.0 0.6 μs
tSU;STA Setup time for a repeated start condition 4.7 0.6 μs
tHD;DAT Data hold time 0.1 3.45 0.1 0.9 μs
tSU;DAT Data setup time 250 100 ns
tR Rise time of SDA and SCL signals 1000 20 300 ns
tF Fall time of SDA and SCL signals 300 20 300 ns
tSU;STO Setup time for stop condition 4.0 0.6 μs
tBUF Bus-free time between a stop and start condition 4.7 1.3 μs
tSP Pulse width of suppressed spikes N/A 50 ns
1
Min and max values are typical minimum and maximum values.

I2C Interface Timing Diagram

SDA

tBUF
tF tSU;DAT tHD;STA tSP tR
tR
tLOW tF

SCL

tHD;STA
tHD;DAT tSU;STA tSU;STO
tHIGH

09320-002
START REPEATED START STOP START
CONDITION CONDITION CONDITION CONDITION

Figure 3. I2C Interface Timing

Rev. C | Page 7 of 72
ADE7953 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
Table 4. stress rating only; functional operation of the product at these
Parameter Rating or any other conditions above those indicated in the operational
VDD to AGND −0.3 V to +3.7 V section of this specification is not implied. Operation beyond
VDD to DGND −0.3 V to +3.7 V the maximum operating conditions for extended periods may
Analog Input Voltage to AGND, −2 V to +2 V affect product reliability.
IAP, IAN, IBP, IBN, VP, VN
Reference Input Voltage to AGND −0.3 V to VDD + 0.3 V ESD CAUTION
Digital Input Voltage to DGND −0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND −0.3 V to VDD + 0.3 V
Operating Temperature
Industrial Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Note that regarding the temperature profile used in soldering
RoHS-compliant parts, Analog Devices, Inc., advises that reflow
profiles should conform to J-STD 20 from JEDEC. Refer to the
JEDEC website for the latest revision.

Rev. C | Page 8 of 72
Data Sheet ADE7953

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

MOSI/SCL/Rx
MISO/SDA/Tx
SCLK
CF2
23 CF1
22 IRQ
28 CS
27
26
25
24
ZX 1 21 ZX_I
RESET 2 20 REVP
VINTD 3 19 CLKOUT
DGND 4
ADE7953 18 CLKIN
TOP VIEW
IAP 5 (Not to Scale) 17 VDD
IAN 6 16 AGND
PULL_HIGH 7 15 VINTA

8
9

VN 11
IBN 10

VP 12
REF 13
PULL_LOW 14
PULL_HIGH
IBP
NOTES
1. CREATE A SIMILAR PAD ON THE PCB UNDER THE EXPOSED

09320-004
PAD. SOLDER THE EXPOSED PAD TO THE PAD ON THE PCB
TO CONFER MECHANICAL STRENGTH TO THE PACKAGE.
CONNECT THE PAD TO AGND AND DGND.

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description
1 ZX Voltage Channel Zero-Crossing Output Pin. See the Voltage Channel Zero Crossing section. This pin can
be configured to output a range of alternative power quality signals (see the Alternative Output Functions
section).
2 RESET Active Low Reset Input. To initiate a hardware reset, this pin must be brought low for at minimum of 10 µs.
3 VINTD This pin provides access to the 2.5 V digital LDO. This pin should be decoupled with a 4.7 µF capacitor in
parallel with a 100 nF ceramic capacitor.
4 DGND Ground Reference for the Digital Circuitry.
5, 6 IAP, IAN Analog Input for Current Channel A (Phase Current Channel). This differential voltage input has a maximum
input range of ±500 mV. The maximum pin voltage for single-ended use is ±250 mV. The PGA associated
with this input has a maximum gain stage of 22 (see the Analog Inputs section).
7, 8 PULL_HIGH These pins should be connected to VDD for proper operation.
9, 10 IBP, IBN Analog Input for Current Channel B (Neutral Current Channel). This differential voltage input has a maximum
input range of ±500 mV. The PGA associated with this input has a maximum gain of 16 (see the Analog
Inputs section).
11, 12 VN, VP Analog Input for Voltage Channel. This differential voltage input has a maximum input range of ±500 mV. The
PGA associated with this input has a maximum gain of 16 (see the Analog Inputs section).
13 REF This pin provides access to the on-chip voltage reference. The internal reference has a nominal voltage
of 1.2 V. This pin should be decoupled with a 4.7 µF capacitor in parallel with a 100 nF ceramic capacitor.
Alternatively, an external reference voltage of 1.2 V can be applied to this pin (see the Reference Circuit
section).
14 PULL_LOW This pin should be connected to AGND for proper operation.
15 VINTA This pin provides access to the 2.5 V analog LDO. This pin should be decoupled with a 4.7 µF capacitor in
parallel with a 100 nF ceramic capacitor.
16 AGND Ground Reference for the Analog Circuitry.
17 VDD Power Supply (3.3 V) for the ADE7953. For specified operation, the input to this pin should be within
3.3 V ± 10%. This pin should be decoupled with a 10 µF capacitor in parallel with a 100 nF ceramic capacitor.
18 CLKIN Master Clock Input for the ADE7953. An external clock can be provided at this input. Alternatively, a parallel
resonant AT crystal can be connected across the CLKIN and CLKOUT pins to provide a clock source for the
ADE7953. The clock frequency for specified operation is 3.58 MHz. Ceramic load capacitors of a few tens of
picofarads should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for
the load capacitance requirements.
19 CLKOUT A crystal can be connected across this pin and CLKIN to provide a clock source for the ADE7953.

Rev. C | Page 9 of 72
ADE7953 Data Sheet
Pin No. Mnemonic Description
20 REVP Reverse Power Output Indicator. See the Reverse Power section. This pin can be configured to output a
range of alternative power quality signals (see the Alternative Output Functions section).
21 ZX_I Current Channel Zero-Crossing Output Pin. See the Current Channel Zero Crossing section. This pin can be
configured to output a range of alternative power quality signals (see the Alternative Output Functions
section).
22 IRQ Interrupt Output. See the ADE7953 Interrupts section.
23 CF1 Calibration Frequency Output 1.
24 CF2 Calibration Frequency Output 2.
25 SCLK Serial Clock Input for the Serial Peripheral Interface. All serial communications are synchronized to the
clock (see the SPI Interface section). If using the I 2 C interface, this pin must be pulled high. If using the
UART interface, this pin must be pulled to ground.
26 MISO/SDA/Tx Data Output for SPI Interface/Bidirectional Data Line for I 2 C Interface/Transmit Line for UART Interface.
27 MOSI/SCL/Rx Data Input for SPI Interface/Serial Clock Input for I 2 C Interface/Receive Line for UART Interface.
28 CS Chip Select for SPI Interface. This pin must be pulled high if using the I 2 C or UART interface.
EPAD Exposed Pad. Create a similar pad on the PCB under the exposed pad. Solder the exposed pad to the pad
on the PCB to confer mechanical strength to the package. Connect the pad to AGND and DGND.

Rev. C | Page 10 of 72
Data Sheet ADE7953

TYPICAL PERFORMANCE CHARACTERISTICS

1.0 1.0

0.8 0.8
–40°C PF = –0.5
0.6 +25°C 0.6 PF = +0.5
+85°C PF = +1.0
ERROR (% OF READING)

ERROR (% OF READING)
0.4 0.4

0.2 0.2

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

–0.8 –0.8

–1.0 –1.0

09320-101

09320-104
0.01 0.1 1 10 100 0.01 0.1 1 10 100
CURRENT CHANNE L (% FULL SCALE) CURRENT CHANNE L (% FULL SCALE)

Figure 5. Current Channel A Active Energy Error as a Percentage of Reading Figure 8. Current Channel A Active Energy Error as a Percentage of Reading
(Gain = 1, Power Factor = 1) over Temperature with Internal Reference, (Gain = 22, Temperature = 25°C) over Power Factor with Internal Reference,
Integrator Off Integrator Off

1.0 1.0

0.8 0.8
PF = –0.5 VDD = 3.30V
0.6 PF = +0.5 0.6 VDD = 2.97V
PF = +1.0 VDD = 3.63V
ERROR (% OF READING)

ERROR (% OF READING)

0.4 0.4

0.2 0.2

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

–0.8 –0.8

–1.0 –1.0
09320-102

09320-105
0.01 0.1 1 10 100 0.01 0.1 1 10 100
CURRENT CHANNE L (% FULL SCALE) CURRENT CHANNE L (% FULL SCALE)

Figure 6. Current Channel A Active Energy Error as a Percentage of Reading Figure 9. Current Channel A Active Energy Error as a Percentage of Reading
(Gain = 1, Temperature = 25°C) over Power Factor with Internal Reference, (Gain = 22, Temperature = 25°C, Power Factor = 1) over Supply Voltage
Integrator Off with Internal Reference, Integrator Off

1.0 1.0

0.8 0.8 PF = –0.5

–40°C PF = +0.5
0.6 +25°C 0.6 PF = +1.0
+85°C
ERROR (% OF READING)

ERROR (% OF READING)

0.4 0.4

0.2 0.2

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6
09320-106

–0.8 –0.8

–1.0 – 1.0
09320-103

0.01 0.1 1 10 100 45 50 55 60 65

CURRENT CHANNE L (% FULL SCALE) FREQUENCY (Hz)

Figure 7. Current Channel A Active Energy Error as a Percentage of Reading Figure 10. Current Channel A Active Energy Error as a Percentage of Reading
(Gain = 22, Power Factor = 1) over Temperature with Internal Reference, (Gain = 22, Temperature = 25°C) over Frequency and Power Factor
Integrator Off with Internal Reference, Integrator Off

Rev. C | Page 11 of 72
ADE7953 Data Sheet
1.0 1.0

0.8 0.8
–40°C PF = –0.866
0.6 +25°C 0.6 PF = 0
+85°C PF = +0.866
ERROR (% OF READING)

ERROR (% OF READING)
0.4 0.4

0.2 0.2

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

–0.8 –0.8

–1.0 –1.0

09320-107

09320-110
0.01 0.1 1 10 100 0.01 0.1 1 10 100
CURRENT CHANNE L (% FULL SCALE) CURRENT CHANNE L (% FULL SCALE)

Figure 11. Current Channel A Reactive Energy Error as a Percentage of Reading Figure 14. Current Channel A Reactive Energy Error as a Percentage of Reading
(Gain = 1, Power Factor = 0) over Temperature with Internal Reference, (Gain = 22, Temperature = 25°C) over Power Factor with Internal Reference,
Integrator Off Integrator Off

1.0 1.0

0.8 0.8 PF = –0.866

PF = –0.866 PF = 0
0.6 PF = 0 0.6 PF = +0.866
PF = +0.866
ERROR (% OF READING)

ERROR (% OF READING)
0.4 0.4

0.2 0.2

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

09320-111
–0.8 –0.8

–1.0 – 1.0
09320-108

0.01 0.1 1 10 100 45 50 55 60 65

CURRENT CHANNE L (% FULL SCALE) FREQUENCY (Hz)

Figure 12. Current Channel A Reactive Energy Error as a Percentage of Reading Figure 15. Current Channel A Reactive Energy Error as a Percentage of Reading
(Gain = 1, Temperature = 25°C) over Power Factor with Internal Reference, (Gain = 22, Temperature = 25°C) over Frequency and Power Factor
Integrator Off with Internal Reference, Integrator Off

1.0 1.0

0.8 –40°C 0.8

+25°C GAIN = 1
0.6 +85°C 0.6 GAIN = 22
ERROR (% OF READING)

ERROR (% OF READING)

0.4 0.4

0.2 0.2

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

–0.8 –0.8

–1.0 –1.0
09320-109

09320-112

0.01 0.1 1 10 100 0.1 1 10 100

CURRENT CHANNE L (% FULL SCALE) CURRENT CHANNE L (% FULL SCALE)

Figure 13. Current Channel A Reactive Energy Error as a Percentage of Reading Figure 16. Current Channel A IRMS Error as a Percentage of Reading
(Gain = 22, Power Factor = 0) over Temperature with Internal Reference, (Temperature = 25°C, Power Factor = 1) over Gain with Internal Reference,
Integrator Off Integrator Off

Rev. C | Page 12 of 72
Data Sheet ADE7953
1.0 1.0

0.8 0.8 PF = –0.5

–40°C PF = +0.5
0.6 +25°C 0.6 PF = +1.0
+85°C
ERROR (% OF READING)

ERROR (% OF READING)
0.4 0.4

0.2 0.2

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

09320-116
–0.8 –0.8

–1.0 – 1.0

09320-113
0.1 1 10 100 45 50 55 60 65
CURRENT CHANNE L (% FULL SCALE) FREQUENCY (Hz)

Figure 17. Current Channel B Active Energy Error as a Percentage of Reading Figure 20. Current Channel B Active Energy Error as a Percentage of Reading
(Gain = 1, Power Factor = 1) over Temperature with Internal Reference, (Gain = 1, Temperature = 25°C) over Frequency and Power Factor
Integrator Off with Internal Reference, Integrator Off

1.0 1.0

0.8 0.8
PF = –0.5 –40°C
0.6 PF = +0.5 0.6 +25°C
PF = +1.0 +85°C
ERROR (% OF READING)

ERROR (% OF READING)
0.4 0.4

0.2 0.2

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

–0.8 –0.8

–1.0 –1.0
09320-114

09320-117
0.1 1 10 100 0.1 1 10 100
CURRENT CHANNE L (% FULL SCALE) CURRENT CHANNE L (% FULL SCALE)

Figure 18. Current Channel B Active Energy Error as a Percentage of Reading Figure 21. Current Channel B Reactive Energy Error as a Percentage of Reading
(Gain = 1, Temperature = 25°C) over Power Factor with Internal Reference, (Gain = 1, Power Factor = 0) over Temperature with Internal Reference,
Integrator Off Integrator Off

1.0 1.0

0.8 0.8
VDD = 3.30V PF = –0.866
0.6 VDD = 2.97V 0.6 PF = 0
VDD = 3.63V PF = +0.866
ERROR (% OF READING)

ERROR (% OF READING)

0.4 0.4

0.2 0.2

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

–0.8 –0.8

–1.0 –1.0
09320-115

09320-118

0.1 1 10 100 0.1 1 10 100

CURRENT CHANNE L (% FULL SCALE) CURRENT CHANNE L (% FULL SCALE)

Figure 19. Current Channel B Active Energy Error as a Percentage of Reading Figure 22. Current Channel B Reactive Energy Error as a Percentage of Reading
(Gain = 1, Temperature = 25°C, Power Factor = 1) over Supply Voltage (Gain = 1, Temperature = 25°C) over Power Factor with Internal Reference,
with Internal Reference, Integrator Off Integrator Off

Rev. C | Page 13 of 72
ADE7953 Data Sheet
1.0 1.0

0.8 PF = –0.866 0.8

PF = 0 –40°C
0.6 PF = +0.866 0.6 +25°C
+85°C

ERROR (% OF READING)
ERROR (% OF READING)

0.4 0.4

0.2 0.2

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

09320-219
–0.8 –0.8

– 1.0 –1.0

09320-122
45 50 55 60 65 0.01 0.1 1 10 100
FREQUENCY (Hz) CURRENT CHANNE L (% FULL SCALE)

Figure 23. Current Channel B Reactive Energy Error as a Percentage of Reading Figure 26. Current Channel A Active Energy Error as a Percentage of Reading
(Gain = 1, Temperature = 25°C) over Frequency and Power Factor (Gain = 16, Power Factor = 1) over Temperature with Internal Reference,
with Internal Reference, Integrator Off Integrator On

1.0 1.0

0.8 0.8
PF = –0.5
0.6 0.6 PF = +0.5
ERROR (% OF READING) PF = +1.0
ERROR (% OF READING)

0.4 0.4

0.2 0.2

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

–0.8 –0.8

–1.0

09320-123
–1.0
09320-220

0.1 1 10 100 0.01 0.1 1 10 100

CURRENT CHANNE L (% FULL SCALE) CURRENT CHANNE L (% FULL SCALE)

Figure 24. Current Channel B IRMS Error as a Percentage of Reading Figure 27. Current Channel A Active Energy Error as a Percentage of Reading
(Gain = 1, Temperature = 25°C, Power Factor = 1) (Gain = 16, Temperature = 25°C) over Power Factor with Internal Reference,
with Internal Reference, Integrator Off Integrator On

1.0 1.0

0.8 0.8
–40°C
0.6 0.6 +25°C
+85°C
ERROR (% OF READING)
ERROR (% OF READING)

0.4 0.4

0.2 0.2

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

–0.8 –0.8

–1.0
09320-124
09320-121

0.1 1 10 100 0.1 1 10 100

VOLTAGE CHANNEL (% FULL SCALE) CURRENT CHANNE L (% FULL SCALE)

Figure 25. VRMS Error as a Percentage of Reading (Temperature = 25°C, Figure 28. Current Channel B Active Energy Error as a Percentage of Reading
Power Factor = 1) with Internal Reference, Integrator Off (Gain = 16, Power Factor = 1) over Temperature with Internal Reference,
Integrator On

Rev. C | Page 14 of 72
Data Sheet ADE7953
1.0 1.0

0.8 0.8 –40°C

PF = –0.5 +25°C
0.6 PF = +0.5 0.6 +85°C
PF = +1.0
ERROR (% OF READING)

ERROR (% OF READING)
0.4 0.4

0.2 0.2

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

–0.8 –0.8

–1.0 –1.0

09320-225

09320-228
0.1 1 10 100 0.1 1 10 100
CURRENT CHANNE L (% FULL SCALE) CURRENT CHANNE L (% FULL SCALE)

Figure 29. Current Channel B Active Energy Error as a Percentage of Reading Figure 32. Current Channel B Reactive Energy Error as a Percentage of Reading
(Gain = 16, Temperature = 25°C) over Power Factor with Internal Reference, (Gain = 16, Power Factor = 0) over Temperature with Internal Reference,
Integrator On Integrator On

1.0 1.0

0.8 0.8
–40°C PF = –0.866
0.6 +25°C 0.6 PF = 0
+85°C PF = +0.866
ERROR (% OF READING)

ERROR (% OF READING)
0.4 0.4

0.2 0.2

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

–0.8 –0.8

–1.0 –1.0
09320-126

09320-129
0.01 0.1 1 10 100 0.1 1 10 100
CURRENT CHANNE L (% FULL SCALE) CURRENT CHANNE L (% FULL SCALE)

Figure 30. Current Channel A Reactive Energy Error as a Percentage of Reading Figure 33. Current Channel B Reactive Energy Error as a Percentage of Reading
(Gain = 16, Power Factor = 0) over Temperature with Internal Reference, (Gain = 16, Temperature = 25°C) over Power Factor with Internal Reference,
Integrator On Integrator On

1.0 1.0

0.8 CHANNEL A
0.8
CHANNEL B
PF = –0.866
0.6 PF = 0 0.6
PF = +0.866
ERROR (% OF READING)
ERROR (% OF READING)

0.4 0.4

0.2 0.2

0 0

–0.2 –0.2

–0.4 –0.4

–0.6 –0.6

–0.8 –0.8

–1.0 –1.0
09320-130
09320-227

0.01 0.1 1 10 100 0.1 1 10 100

CURRENT CHANNE L (% FULL SCALE) CURRENT CHANNE L (% FULL SCALE)

Figure 31. Current Channel A Reactive Energy Error as a Percentage of Reading Figure 34. IRMS Error as a Percentage of Reading (Gain = 16,
(Gain = 16, Temperature = 25°C) over Power Factor with Internal Reference, Temperature = 25°C) with Internal Reference, Integrator On
Integrator On

Rev. C | Page 15 of 72
ADE7953 Data Sheet

TEST CIRCUIT
3.3V

+ +
3.3V 4.7µF 0.1µF 4.7µF 0.1µF

10kΩ 1µF 15 17 3

VINTA

VDD

VINTD
2 RESET ZX 1
1kΩ

33nF 5 IAP REVP 20

33nF ZX_I 21
6 IAN
1kΩ CS 28
1kΩ MOSI/SCL/Rx 27

33nF 9 IBP MISO/SDA/Tx 26 3.3V

33nF 10 IBN SCLK 25
10kΩ
1kΩ
ADE7953 CF2 24
SAME AS 3.3V
CF1 23 CF2 500Ω
1kΩ 33nF
11 VN 10kΩ
1MΩ IRQ 22
12 VP
REF 13
110V 1kΩ 33nF 3.3V +
20pF
7 PULL_HIGH 4.7µF 0.1µF
CLKOUT 19
8 PULL_HIGH 3.58MHz
DGND

AGND

14 PULL_LOW CLKIN 18
20pF
4 16

09320-099
Figure 35. Test Circuit

Rev. C | Page 16 of 72
Data Sheet ADE7953

TERMINOLOGY
Measurement Error ADC Offset Error
The error associated with the energy measurement made by the The ADC offset error refers to the dc offset associated with the
ADE7953 is defined by analog inputs to the ADCs. It means that, with the analog inputs
Measurement Error = (1) connected to AGND, the ADCs still see a dc analog input signal.
The magnitude of the offset depends on the gain and input range
Energy Registered by ADE7953 − True Energy
× 100% selection. However, the offset is removed from the current and
True Energy
voltage channels by a high-pass filter (HPF), and the power
Phase Error Between Channels calculation is not affected by this offset.
The high-pass filter (HPF) and digital integrator introduce a Gain Error
slight phase mismatch between the current channels and the The gain error in the ADCs of the ADE7953 is defined as the
voltage channel. The all-digital design ensures that the phase per-channel difference between the measured ADC output code
matching between the current channels and the voltage channel (minus the offset) and the ideal output code (see the Current
is within ±0.05° over a range of 45 Hz to 65 Hz. This internal Channel ADCS section and the Voltage Channel ADC section).
phase mismatch can be combined with the external phase error The difference is expressed as a percentage of the ideal code.
(from current sensor or component tolerance) and calibrated
with the phase calibration registers.
Power Supply Rejection (PSR)
PSR quantifies the ADE7953 measurement error as a percentage
of reading when the power supplies are varied. For the ac PSR
measurement, a reading at nominal supplies (3.3 V) is taken. A
second reading is obtained with the same input signal levels when
an ac signal (120 mV rms/100 Hz) is introduced onto the supplies.
Any error introduced by this ac signal is expressed as a percentage
of reading (see the Measurement Error definition). For the dc PSR
measurement, a reading at nominal supplies (3.3 V) is taken. A
second reading is obtained with the same input signal levels when
the power supplies are varied by ±10%. Any error introduced is
again expressed as a percentage of reading.

Rev. C | Page 17 of 72
ADE7953 Data Sheet

ADE7953 POWER-UP PROCEDURE

The ADE7953 contains an on-chip power supply monitor that Once the start-up sequence is complete, communication with
supervises the power supply (VDD). While the voltage applied the ADE7953 can begin. See the Communicating with the
to the VDD pin is below 2 V ± 10%, the chip is in an inactive ADE7953 section for further details.
state. Once VDD crosses the 2 V ± 10% threshold, the power
REQUIRED REGISTER SETTING
supply monitor keeps the ADE7953 in an inactive state for an
additional 26 ms. This time delay allows VDD to reach the For optimum performance, Register Address 0x120 must be
minimum specified operating voltage of 3.3 V – 10%. Once configured by the user after powering up the ADE7953. This
the minimum specified operating voltage is met, the internal register ensures that the optimum timing configuration is
circuitry is enabled; this is accomplished in approximately selected to maximize the accuracy and dynamic range. This
40 ms. register is not set by default and thus must be written by the
user each time the ADE7953 is powered up. Register 0x120 is
Once the start-up sequence is complete and the ADE7953 is a protected register and thus a key must be written to allow the
ready to receive communication from a microcontroller, the register to be modified. The following sequence should be
reset flag is set in the IRQSTATA register (Address 0x22D and followed:
Address 0x32D). An external interrupt is triggered on the IRQ
pin. The reset interrupt is enabled by default and cannot be • Write 0xAD to Register Address 0xFE:This unlocks
disabled, hence an external interrupt always occurs at the end Register 0x120
of a power-up procedure, hardware or software reset. • Write 0x30 to Register Address 0x120: This configures the
optimum settings
It is highly recommended that the reset interrupt is used by
the microcontroller to gate the first communication with the The above two instructions must be performed in succession to
ADE7953. If the interrupt is not used, a timeout can be be successful.
implemented; however, as the start-up sequence can vary part-
to-part and over temperature, a timeout of a least 100 ms is
recommended. The reset interrupt provides the most efficient
way of monitoring the completion of the ADE7953 start-up
sequence.

Rev. C | Page 18 of 72
Data Sheet ADE7953

THEORY OF OPERATION
ANALOG INPUTS the voltage channel with gain options of 1, 2, 4, 8, and 16 (see
The ADE7953 includes three analog inputs that form two current Table 6).
channels and one voltage channel. In a standard configuration, The voltage channel gain is configured by writing to the PGA_V
Current Channel A is used to measure the phase current, and register (Address 0x007). By default, the voltage channel PGA is
Current Channel B is used to measure the neutral current. The set to 1.
voltage channel input measures the difference between the phase
voltage and the neutral voltage. The ADE7953 can, however, be Table 6. PGA Gain Settings
Full-Scale
used with alternative voltage and current combinations as long as
Differential PGA_IA[2:0] PGA_IB[2:0] PGA_V[2:0]
the analog input specifications described in this section are met. Gain Input (mV) (Addr 0x008) (Addr 0x009) (Addr 0x007)
Current Channel A 1 ±500 000 1 000 000
2 ±250 001 001 001
Current Channel A is a fully differential voltage input that is
4 ±125 010 010 010
designed to be used with a current sensor. This input is driven
8 ±62.5 011 011 011
by two pins: IAP (Pin 5) and IAN (Pin 6). The maximum differ-
16 ±31.25 100 100 100
ential voltage that can be applied to IAP and IAN is ±500 mV. 22 ±22.7 101 N/A N/A
A common-mode voltage of less than ±25 mV is recommended.
Common-mode voltages in excess of this recommended value 1
When a gain of 1 is selected on Current Channel A, the maximum pin input is
limited to ±250 mV. Therefore, when using a single-ended configuration, the
may limit the available dynamic range. A programmable gain maximum input is ±250 mV with respect to AGND.
amplifier (PGA) stage is provided on Current Channel A with
gain options of 1, 2, 4, 8, 16, and 22 (see Table 6). ANALOG-TO-DIGITAL CONVERSION
The analog-to-digital conversion in the ADE7953 is performed
The maximum full-scale input of Current Channel A is ±250 mV
by three second-order Σ-Δ modulators. For the sake of clarity,
when using a single-ended configuration and, therefore, when
the block diagram in Figure 36 shows the operation of a first-
using a gain setting of 1, the dynamic range is limited. The Current
order Σ-Δ modulator. The analog-to-digital conversion consists
Channel A gain is configured by writing to the PGA_IA register
of a Σ-Δ modulator followed by a low-pass filter stage.
(Address 0x008). By default, the Current Channel A PGA is set
CLKIN/4
to 1. A gain option of 22 is offered exclusively on Current
ANALOG
Channel A, allowing high accuracy measurement for signals of LOW-PASS FILTER
DIGITAL
INTEGRATOR LOW-PASS
very small amplitude. This configuration is particularly useful R +
LATCHED
COMPARATOR
FILTER
+
when using small value shunt resistors or Rogowski coils. C
–
– 24
+VREF
Current Channel B
Current Channel B is a fully differential voltage input that is

09320-013
.....10100101.....
designed to be used with a current sensor. This input is driven 1-BIT DAC
–VREF
by two pins: IBP (Pin 9) and IBN (Pin 10). The maximum differ-
ential voltage that can be applied to IBP and IBN is ±500 mV. A Figure 36. Σ-Δ Conversion
common-mode voltage of less than ±25 mV is recommended. The Σ-Δ modulator converts the input signal into a continuous
Common-mode voltages in excess of this recommended value serial stream of 1s and 0s at a rate determined by the sampling
may limit the available dynamic range. A PGA gain stage is clock. The ADE7953 sampling clock is equal to 895 kHz
provided on Current Channel B with gain options of 1, 2, 4, 8, (CLKIN/4). The 1-bit DAC in the feedback loop is driven by the
and 16 (see Table 6). The Current Channel B gain is configured serial data stream. The DAC output is subtracted from the input
by writing to the PGA_IB register (Address 0x009). By default, signal. If the loop gain is high enough, the average value of the
the Current Channel B PGA is set to 1. DAC output (and, therefore, the bit stream) can approach that
Voltage Channel of the input signal level. For any given input value in a single
The voltage channel input a full differential input driven by sampling interval, the data from the 1-bit ADC is virtually
two pins: VP (Pin 12) and VN (Pin 11). The voltage channel meaningless. A meaningful result is obtained only when a large
is typically connected in a single-ended configuration. The number of samples is averaged. This averaging is carried out
maximum single-ended voltage that can be applied to VP is in the second part of the ADC, the digital low-pass filter. By
±500 mV with respect to VN. A common-mode voltage of less averaging a large number of bits from the modulator, the low-
than ±25 mV is recommended. Common-mode voltages in pass filter can produce 24-bit data-words that are proportional
excess of this recommended value may limit the dynamic range to the input signal level. The Σ-∆ converter uses two techniques—
capabilities of the ADE7953. A PGA gain stage is provided on oversampling and noise shaping—to achieve high resolution
from what is essentially a 1-bit conversion technique.

Rev. C | Page 19 of 72
ADE7953 Data Sheet
Oversampling Noise Shaping
Oversampling is the first technique used to achieve high Noise shaping is the second technique used to achieve high
resolution. Oversampling means that the signal is sampled at a resolution. In the -Δ modulator, the noise is shaped by the
rate (frequency) that is many times higher than the bandwidth integrator, which has a high-pass-type response for the quanti-
of interest. For example, the sampling rate in the ADE7953 is zation noise due to feedback. The result is that most of the noise
895 kHz, and the bandwidth of interest is 40 Hz to 1.23 kHz. is at the higher frequencies, where it can be removed by the
Oversampling has the effect of spreading the quantization noise digital low-pass filter. This noise shaping is shown in Figure 37.
(noise due to sampling) over a wider bandwidth. With the noise
Antialiasing Filter
spread more thinly over a wider bandwidth, the quantization
noise in the band of interest is lowered (see Figure 37). As shown in Figure 36, an external low-pass RC filter is required
ANTIALIASING FILTER
on the input to each modulator. The role of this filter is to prevent
DIGITAL FILTER
(RC) aliasing. Aliasing refers to the frequency components in the input
SIGNAL
SHAPED NOISE signal that are folded back and appear in the sampled signal. This
SAMPLING
FREQUENCY effect occurs with signals that are higher than half the sampling
NOISE rate of the ADC (also known as the Nyquist frequency) appear-
ing in the sampled signal at a frequency below half the sampling
0 3 447.5 895 rate. This concept is depicted in Figure 38.
FREQUENCY (kHz)
ALIASING EFFECTS
SAMPLING
FREQUENCY
HIGH RESOLUTION
OUTPUT FROM
DIGITAL LPF
SIGNAL

NOISE 0 1.23 3 447.5 895

FREQUENCY (kHz)

09320-015
09320-014

0 3 447.5 895 IMAGE

FREQUENCIES
FREQUENCY (kHz)
Figure 38. Aliasing Effect
Figure 37. Noise Reduction due to Oversampling and
Noise Shaping in the Analog Modulator The arrows shown in Figure 38 depict the frequency compo-
However, oversampling alone is not sufficient to improve the nents above the Nyquist frequency (447.5 kHz in the case of
signal-to-noise ratio (SNR) in the bandwidth of interest. For the ADE7953) being folded back down. Aliasing occurs with
example, an oversampling ratio of 4 is required to increase the all ADCs, regardless of the architecture.
SNR by only 6 dB (1 bit). To keep the oversampling ratio at a
reasonable level, it is possible to shape the quantization noise so
that the majority of the noise lies at the higher frequencies (see
the following section.

ZX_I DETECTION
LPF1

CURRENT PEAK,
OVERCURRENT
DETECTION

DSP INTENx BIT CURRENT RMS (IRMS)

HPFEN BIT CONFIG[1:0] CALCULATION
PGA_x BITS CONFIG[2]
×1, ×2, ×4, ×8, ×16, REFERENCE
Ix WAVEFORM
×22 (FOR IA ONLY) xIGAIN DIGITAL
SAMPLING REGISTER
IxP INTEGRATOR
ACTIVE AND REACTIVE
VIN PGA ADC POWER CALCULATION
09320-019

HPF
IxN

Figure 39. Current Channel ADC and Signal Path

Rev. C | Page 20 of 72
Data Sheet ADE7953
CURRENT CHANNEL ADCS The flux density of a magnetic field induced by a current is
Figure 39 shows the ADC signal path and signal processing for directly proportional to the magnitude of the current. Changes
Current Channel A, which is accessed through the IAP and IAN in the magnetic flux density passing through a conductor loop
pins. The signal path for Current Channel B is identical and is generate an electromotive force (EMF) between the two ends of
accessed through the IBP and IBN pins. The ADC output is a the loop. The EMF is a voltage signal that is proportional to the
twos complement, 24-bit data-word that is available at a rate of differential of the current over time (di/dt). The voltage output
6.99 kSPS (thousand samples per second). With the specified full- from the di/dt sensor is determined by the mutual inductance
scale analog input of ±250 mV and a PGA_Ix gain setting of 2, between the current-carrying conductor and the di/dt sensor.
the ADC produces its maximum output code. The ADC output The current signal must be recovered from the di/dt signal
swings between −6,500,000 LSBs (decimal) and +6,500,000 LSBs. before it can be used. An integrator is therefore necessary to
This output varies from part to part. The signal path includes a restore the signal to its original form.
xIGAIN register to modify the current gain for Current The ADE7953 has a built-in digital integrator on each current
Channel A or Current Channel B. This register can be used to channel that recovers the current signal from the di/dt sensor.
match Current Channel B to Current Channel A for simple Both digital integrators are disabled by default. The digital
calibration and computation. This gain is performed using the integrator on Current Channel A is enabled by setting the
BIGAIN register (Address 0x28C and Address 0x38C). The INTENA bit (Bit 0) in the CONFIG register (Address 0x102).
Current Channel A gain can be modified with the AIGAIN The digital integrator on Current Channel B is enabled by setting
register (Address 0x280 and Address 0x380). the INTENB bit (Bit 1) in the CONFIG register (Address 0x102).
As shown in Figure 39, there is a high-pass filter (HPF) in each VOLTAGE CHANNEL ADC
current channel signal path. The HPF is enabled by default and Figure 41 shows the ADC signal path and signal processing for
removes any dc offset in the ADC output. It is highly recom- the voltage channel input, which is accessed through the VP and
mended that this filter be enabled at all times, but it can be VN pins. The ADC output is a twos complement, 24-bit data-
disabled by clearing the HPFEN bit (Bit 2) in the CONFIG word that is available at a rate of 6.99 kSPS (thousand samples
register (Address 0x102). Clearing the HPFEN bit disables the per second). With the specified full-scale analog input of ±500 mV
filters in both current channels and in the voltage channel. and a PGA_V gain setting of 1, the ADC produces its maximum
di/dt Current Sensor and Digital Integrator output code. The ADC output swings between −6,500,000 LSBs
As shown in Figure 39, the current channel signal path for both (decimal) and +6,500,000 LSBs. Note that this output varies
Channel A and Channel B includes an internal digital integrator. from part to part. The signal path includes a xVGAIN register
This integrator is disabled by default and is required only when to modify the voltage gains for the voltage channel. AVGAIN
interfacing with a di/dt sensor, such as a Rogowski coil. When (Address 0x281 and Address 0x381) is the primary voltage gain
using either a shunt resistor or a current transformer (CT), this register used, affecting RMS and Channel A energy register
integrator is not required and should remain disabled. readings. Most frequently, the energy gain registers, not the
voltage gain registers, are used in calibration. In the unique case
A di/dt sensor detects changes in the magnetic field caused by that both the AVGAIN register and Current Channel B are
ac current. Figure 40 shows the principle of a di/dt current used, set BVGAIN (Address 0x28D and Address 0x38D) to the
sensor. same AVGAIN value to ensure equal gain in both channels.
As shown in Figure 41, there is a high-pass filter (HPF) in the
MAGNETIC FIELD CREATED BY CURRENT voltage channel signal path. The HPF is enabled by default and
(DIRECTLY PROPORTIONAL TO CURRENT)
removes any dc offset in the ADC output. It is highly recom-
mended that this filter be enabled at all times, but it can be
disabled by clearing the HPFEN bit (Bit 2) in the CONFIG
+ EMF (ELECTROMOTIVE FORCE) register (Address 0x102). Clearing the HPFEN bit disables the
09320-020

– INDUCED BY CHANGES IN
MAGNETIC FLUX DENSITY (di/dt)
filters in both current channels and in the voltage channel.

Figure 40. Principle of a di/dt Current Sensor

Rev. C | Page 21 of 72
ADE7953 Data Sheet
REFERENCE CIRCUIT the reference results in a 2x% deviation in meter accuracy. The
The ADE7953 has an internal voltage reference of 1.2 V nominal, reference drift is typically minimal and is usually much smaller
which appears on the REF pin. This reference voltage is used by than the drift of other components in the meter. By default, the
the ADCs in the ADE7953. The REF pin can be overdriven by ADE7953 is configured to use the internal reference. If Bit 0 of
an external source, for example an external 1.2 V reference. The the EX_REF register (Address 0x800) is set to 1, an external
voltage of the ADE7953 internal reference drifts slightly over voltage reference can be applied to the REF pin.
temperature (see the Specifications section). The value of the tem-
perature drift may vary slightly from part to part. A drift of x% in
VOLTAGE PEAK,
OVERVOLTAGE,
SAG DETECTION

DSP VOLTAGE RMS (VRMS)

HPFEN BIT CALCULATION
REFERENCE CONFIG[2]
PGA_V BITS V WAVEFORM
×1, ×2, ×4, ×8, ×16 xVGAIN
SAMPLING REGISTER
VP

ACTIVE AND REACTIVE

VIN PGA ADC
HPF POWER CALCULATION

VN

09320-025
ZX DETECTION
LPF1

Figure 41. Voltage Channel ADC and Signal Path

Rev. C | Page 22 of 72
Data Sheet ADE7953

ROOT MEAN SQUARE MEASUREMENT

Root mean square (rms) is a measurement of the magnitude the IRMSA (Address 0x21A and Address 0x31A) and IRMSB
of an ac signal. Specifically, the rms of an ac signal is equal to (Address 0x21B and Address 0x31B) registers, respectively. Both
the amount of dc required to produce an equivalent amount of these registers are updated at a rate of 6.99 kHz. With full-
of power in the load. The rms is expressed mathematically in scale inputs on Current Channel A and Current Channel B,
Equation 1. the expected reading on the IRMSA and IRMSB register is
t
9032007d.
1
RMS  f
2
(t ) dt (1) Because the LPF used in the rms signal path is not ideal, it is
t 0
recommended that the IRMSx registers be read synchronously
For time-sampled signals, rms calculation involves squaring to the zero-crossing signal (see the Zero-Crossing Detection
the signal, taking the average, and obtaining the square root. section). This helps to stabilize reading-to-reading variation
N
by removing the effect of any 2ω ripple present on the rms
1
RMS   f 2 [n] (2) measurement.
N n 1
VOLTAGE CHANNEL RMS CALCULATION
As implied by Equation 2, the rms measurement contains
The ADE7953 provides an rms measurement on the voltage
information from the fundamental and all harmonics over
channel. Figure 43 shows the signal path for this calculation.
a 1.23 kHz measurement bandwidth.
VRMSOS[23:0]
The ADE7953 provide rms measurements for Current
Channel A, Current Channel B, and the voltage channel
simultaneously. These measurements have a settling time of 212

approximately 200 ms and are updated at a rate of 6.99 kHz.

VOLTAGE

09320-041
CURRENT CHANNEL RMS CALCULATION SIGNAL X2
LPF
√ VRMS[23:0]
FROM HPF
The ADE7953 provides rms measurements for both Current
Figure 43. Voltage Channel RMS Signal Processing
Channel A and Current Channel B. Figure 42 shows the signal
path for this calculation. The signal processing is identical for As shown in Figure 43, the voltage channel ADC output
Current Channel A and Current Channel B. samples are used to continually compute the rms. The rms is
achieved by low-pass filtering the square of the output signal
×IRMSOS[23:0]
and then taking a square root of the result. The 24-bit unsigned
voltage channel rms measurement is available in the VRMS
212 register (Address 0x21C and Address 0x31C). This register is
CURRENT updated at a rate of 6.99 kHz. With full-scale inputs on the
SIGNAL voltage channel, a VRMS reading of 9032007d can be expected.
FROM HPF OR X2 √ IRMSx[23:0]
09320-040

INTEGRATOR LPF
(IF ENABLED) Because the LPF used in the rms signal path is not ideal, it is
Figure 42. Current Channel RMS Signal Processing recommended that the VRMS register be read synchronously
to the zero-crossing signal (see the Zero-Crossing Detection
As shown in Figure 42, the current channel ADC output samples
section). This helps to stabilize reading-to-reading variation by
are used to continually compute the rms. The rms is achieved by
removing the effect of any 2ω ripple present on the rms
low-pass filtering the square of the output signal and then taking
measurement.
a square root of the result. The 24-bit unsigned rms measurements
for Current Channel A and Current Channel B are available in

Rev. C | Page 23 of 72
ADE7953 Data Sheet

ACTIVE POWER CALCULATION

Power is defined as the rate of energy flow from the source to ripple associated with it. This ripple is sinusoidal and has a
the load. It is defined as the product of the voltage and current frequency equal to twice the line frequency. Because the ripple
waveforms. The resulting waveform is called the instantaneous is sinusoidal in nature, it is removed when the active power
power signal and is equal to the rate of energy flow at every signal is integrated to compute the active energy (see the Active
instant of time. The unit of power is the watt or joules/sec. Energy Calculation section).
V(t)  2  V  sin(ωt ) (3) INSTANTANEOUS
POWER SIGNAL
P(t) = VRMS × IRMS – VRMS × IRMS × cos(2ωt)

INSTANTANEOUS
I(t)  2  I  sin(ωt ) (4) ACTIVE POWER SIGNAL:
VRMS × IRMS
where:
V is the rms voltage. VRMS
×
I is the rms current. IRMS

P(t) = V(t) × I(t) (5)

P(t) = VI − VI × cos(2ωt) (6)
0x0 0000
The average power over an integral number of line cycles (n)
is given by the expression in Equation 7. I(t) = √2 × IRMS × sin(ωt)
V(t) = √2 × VRMS × sin(ωt)
nT
1

09320-043
P  P (t )dt  VI (7)
nT 0
Figure 44. Active Power Calculation
where:
P is the active or real power. The ADE7953 computes the active power simultaneously on
T is the line cycle period. Current Channel A and Current Channel B and stores the
resulting measurements in the AWATT (Address 0x212 and
The active power is equal to the dc component of the instan- Address 0x312) and BWATT (Address 0x213 and Address 0x313)
taneous power signal (P(t) in Equation 5). The active power is registers, respectively. With full-scale inputs, the expected
therefore equal to VI. This relationship is used to calculate active reading in the AWATT and BWATT registers is approximately
power in the ADE7953. Figure 44 illustrates this concept. 4862401 LSBs (decimal).
The signal chain for the active power and energy calculations in The active power measurements are taken over a bandwidth of
the ADE7953 is shown in Figure 45. The instantaneous power 1.23 kHz and include the effects of any harmonics within that
signal P(t) is generated by multiplying the current and voltage range. The active power registers are updated at a rate of 6.99 kHz
signals. The dc component of the instantaneous power signal and can be read using the waveform sampling mode (see the
is then extracted by LPF2 (low-pass filter) to obtain the active Instantaneous Powers and Waveform Sampling section).
power information. Because LFP2 does not have an ideal “brick
wall” frequency response, the active power signal has some
DIGITAL
AIGAIN INTEGRATOR
CURRENT
CHANNEL
A
HPF AWGAIN AWATTOS

48 0
+
PHCALA AVGAIN + INTERNAL AENERGYA
ACCUMULATION 23 0
LPF2
FIXED INTERNAL
HPF THRESHOLD
VOLTAGE ACTIVE POWER
CHANNEL SIGNAL
BVGAIN

HPF BWGAIN BWATTOS

DIGITAL 48 0
INTEGRATOR +
PHCALB BIGAIN + INTERNAL AENERGYB
ACCUMULATION 23 0
LPF2
FIXED INTERNAL
HPF THRESHOLD
CURRENT ACTIVE POWER
09320-044

CHANNEL SIGNAL
B

Figure 45. Active Energy Signal Chain

Rev. C | Page 24 of 72
Data Sheet ADE7953
AENERGYx[23:0]
SIGN OF ACTIVE POWER CALCULATION
The active power measurement in the ADE7953 is a signed 0x7FFFFF
xWGAIN = 0x200000
calculation. If the phase differential between the current and xWGAIN = 0x400000
voltage waveforms is more than 90°, the power is negative. xWGAIN = 0x600000
0x3FFFFF
Negative power indicates that energy is being injected back
into the grid. The ACCMODE register (Address 0x201 and
Address 0x301) includes two sign indication bits that show the 0x000000 TIME (Seconds)
20.26 40.5 60.78
sign of the active power of Current Channel A (APSIGN_A)
and Current Channel B (APSIGN_B). See the Sign Indication
section for more information. 0x400000

ACTIVE ENERGY CALCULATION

09320-042
As described in the Active Power Calculation section, power 0x800000
is defined as the rate of energy flow. This relationship can be
expressed mathematically as shown in Equation 8. Figure 46. Energy Register Roll-Over Time for Active Energy

dE Note that the energy register contents roll over to full-scale

P (8) negative (0x800000) and continue to increase in value when the
dt
power or energy flow is positive. Conversely, if the power is
where: negative, the energy register underflows to full-scale positive
P is power. (0x7FFFFF) and continues to decrease in value.
E is energy.
AENERGYA and AENERGYB are read-with-reset registers
Conversely, energy is given as the integral of power. by default. This means that the contents of these registers are
E   Pdt (9) reset to 0 after a read operation. This feature can be disabled
by clearing Bit 6 (RSTREAD) of the LCYCMODE register
The ADE7953 achieves the integration of the active power (Address 0x004).
signal in two stages. In the first stage, the active power signals
are accumulated in an internal 48-bit register every 143 μs The ADE7953 includes two sets of interrupts that are triggered
(6.99 kHz) until an internal fixed threshold is reached. When when the active energy register is half full (positive or negative)
this threshold is reached, a pulse is generated and is accumu- or when an overflow or underflow condition occurs. The first
lated in 24-bit, user-accessible accumulation registers. The set of interrupts is associated with the Current Channel A active
internal threshold results in a maximum accumulation rate energy, and the second set of interrupts is associated with the
of approximately 206.9 kHz with full-scale inputs. This process Current Channel B active energy. These interrupts are disabled
occurs simultaneously on Current Channel A and Current by default and can be enabled by setting the AEHFA and
Channel B, and the resulting readings can be read in the 24-bit AEOFA bits in the IRQENA register (Address 0x22C and
AENERGYA (Address 0x21E and Address 0x31E) and Address 0x32C) for Current Channel A, and the AEHFB and
AENERGYB (Address 0x21F and Address 0x31F) registers. AEOFB bits in the IRQENB register (Address 0x22F and
Both stages of the accumulation are signed and, therefore, Address 0x32F) for Current Channel B.
negative energy is subtracted from positive energy.
This discrete time accumulation, or summation, is equivalent
to integration in continuous time. Equation 10 expresses this
relationship.
 
E   P(t)dt  Lim   P(nT)  T  (10)
T 0 n  1 
where:
n is the discrete time-sampled number.
T is the sample period.
The discrete time sample period (T) for the accumulation
registers in the ADE7953 is 4.83 μs (1/206.9 kHz). This is
illustrated in Figure 46, which shows the energy register
roll-over rates with full-scale inputs.

Rev. C | Page 25 of 72
ADE7953 Data Sheet
Active Energy Integration Time Under Steady Load Line cycle accumulation mode is disabled by default and can be
The discrete time sample period (T) for the accumulation enabled on Current Channel A and Current Channel B by setting
registers is 4.83 μs (1/206.9 kHz). With full-scale sinusoidal the ALWATT and BLWATT bits to 1 in the LCYCMODE register
signals on the analog inputs and the AWGAIN and BWGAIN (Address 0x004). The accumulation time should be written to
registers set to 0x400000, a pulse is generated and added to the LINECYC register (Address 0x101) in the unit of number of
the AENERGYA and AENERGYB registers every 4.83 μs. half line cycles. The ADE7953 can accumulate energy for up to
The maximum positive value that can be stored in the 24-bit 65,535 half line cycles. This equates to an accumulation period
AENERGYA and AENERGYB registers is 0x7FFFFF before of approximately 655 sec with 50 Hz inputs and 546 sec with
the register overflows. The integration time under these 60 Hz inputs.
conditions can be calculated as follows: The number of half line cycles written to the LINECYC register
Time = 0x7FFFFF × 4.83 μs = 40.5 sec (11) is used for both the Current Channel A and Current Channel B
accumulation periods. At the end of a line cycle accumulation
Active Energy Line Cycle Accumulation Mode cycle, the AENERGYA and AENERGYB registers are updated,
In active energy line cycle accumulation mode, the energy and the CYCEND flag is set in the IRQSTATA register (Address
accumulation of the ADE7953 is synchronized to the voltage 0x22D and Address 0x32D). If the CYCEND bit in the IRQENA
channel zero crossing so that the active energy can be accumu- register is set, an external interrupt is issued on the IRQ pin. In
lated over an integral number of half line cycles. This feature is this way, the IRQ pin can also be used to signal the completion of
available for both Current Channel A and Current Channel B the line cycle accumulation. Another accumulation cycle begins
active energy. The advantage of summing the active energy over immediately as long as the ALWATT and BLWATT bits in the
an integral number of half line cycles is that the sinusoidal LCYCMODE register remain set.
component of the active energy is reduced to 0 (see Equation 12
to Equation 15). This eliminates any ripple in the energy calcula- The contents of the AENERGYA and AENERGYB registers are
tion. Energy is calculated more accurately and in a shorter time updated synchronous to the CYCEND flag. The AENERGYA and
because the integration period can be shortened. The line cycle AENERGYB registers hold their current values until the end of
accumulation mode can be used for fast calibration and also to the next line cycle period, when the contents are replaced with
obtain the average power over a specified time period. Using the new reading. If the read-with-reset bit (RSTREAD) in the
Equation 6, the following description of the energy accumulation LCYCMODE register (Address 0x004) is set, the contents of the
can be derived: AENERGYA and AENERGYB registers are cleared after a read
and remain at 0 until the end of the next line cycle period.
P(t) = VI – [LPF] × cos(2ωt) (12)
If a new value is written to the LINECYC register (Address 0x101)
nT nT
midway through a line cycle accumulation, the new value is not
E(t )   VIdt  [LPF ]   cos(2ωt )dt (13)
internally loaded until the end of a line cycle period. When the
0 0

where: LINECYC register is updated mid-reading, the current energy

n is an integer. accumulation cycle is completed, and the new value is then
T is the line cycle period. programmed, ready for the next cycle. This prevents any invalid
readings due to changes to the LINECYC register (see Figure 47).
Because the sinusoidal component is integrated over an integer
number of line cycles, its value is always 0. Therefore,
nT
AENERGYx REGISTER
E(t)   VIdt  0 (14)
0

E = VInt (15)
CYCEND IRQ

LINECYC REGISTER
09320-017

NEW LINE CYCLE INTERNAL LINE CYCLE

VALUE PROGRAMMED UPDATED

Figure 47. Changing the LINECYC Register

Rev. C | Page 26 of 72
Data Sheet ADE7953
xWGAIN xWATTOS

48 0
+
OUTPUT FROM + INTERNAL
LPF2 ACCUMULATION

FIXED INTERNAL
THRESHOLD

OUTPUT FROM ZERO-CROSSING CALIBRATION

VOLTAGE CHANNEL DETECTION CONTROL
ADC LPF1
23 0
AENERGYx

09320-016
15 0
LINECYC

Figure 48. Active Energy Line Cycle Accumulation

Note that when line cycle accumulation mode is first enabled, the If enabled, the positive-only accumulation mode affects both
reading after the first CYCEND flag should be ignored because energy accumulation registers, AENERGYA and AENERGYB,
it may be inaccurate. This is because the line cycle accumulation as well as the CF output pins (see the Energy-to-Frequency
mode is not synchronized to the zero crossing and, therefore, Conversion section). Note that when the positive-only accumu-
the first reading may not be over a complete number of half line lation mode is enabled on a current channel, the reverse power
cycles. After the first line cycle accumulation is complete, all feature is not available on that current channel (see the Reverse
successive readings will be correct. Power section).
ACTIVE ENERGY ACCUMULATION MODES Absolute Accumulation Mode
Signed Accumulation Mode The ADE7953 includes an absolute energy accumulation mode
The default active energy accumulation mode for the ADE7953 is for Current Channel A and Current Channel B active energy. In
a signed accumulation based on the active power information. absolute accumulation mode, the energy accumulation is done
using the absolute active power, ignoring any occurrences of
Positive-Only Accumulation Mode energy below the no-load threshold (see Figure 50).
The ADE7953 includes a positive-only accumulation mode
option for Current Channel A and Current Channel B active
energy. In positive-only accumulation mode, the energy
accumulation is done only for positive power, ignoring any
occurrence of negative power above or below the no-load
threshold (see Figure 49).
AENERGYx

NO-LOAD
THRESHOLD

ACTIVE POWER
AENERGYx
NO-LOAD
THRESHOLD
09320-119

NO-LOAD Figure 50. Active Energy Absolute Accumulation Mode

THRESHOLD
The absolute accumulation mode is disabled by default and can
ACTIVE POWER
be enabled on Current Channel A and Current Channel B by
NO-LOAD setting the AWATTACC and BWATTACC bits to 10 in the
09320-018

THRESHOLD
ACCMODE register (Address 0x201 and Address 0x301).
Figure 49. Positive-Only Accumulation Mode If enabled, the absolute accumulation mode affects both energy
The positive-only accumulation mode is disabled by default and accumulation registers, AENERGYA and AENERGYB, as well
can be enabled on Current Channel A and Current Channel B as the CF output pins (see the Energy-to-Frequency Conversion
by setting the AWATTACC and BWATTACC bits to 01 in the section). Note that when the absolute accumulation mode is
ACCMODE register (Address 0x201 and Address 0x301). enabled on a current channel, the reverse power feature is not
available on that current channel (see the Reverse Power section).

Rev. C | Page 27 of 72
ADE7953 Data Sheet

REACTIVE POWER CALCULATION

Reactive power is defined as the product of the voltage and The ADE7953 reactive power measurement is stable over the
current waveforms when one of these signals is phase shifted full frequency range. The dc component of the instantaneous
by 90°. The resulting waveform is called the instantaneous reactive power signal is then extracted by a low-pass filter to
reactive power signal. obtain the reactive power information.
Equation 16 provides an expression for the instantaneous The frequency response of the LPFs in the reactive power signal
reactive power signal in an ac system when the phase of the paths is identical to the frequency response of the LPFs used in
current channel is shifted by +90°. the active power calculation. Because the LPF does not have an
RP(t) = V(t) × I’(t) (16) ideal “brick wall” frequency response, the reactive power signal
has some ripple associated with it. This ripple is sinusoidal and
RP(t) = VI × sin(θ) + VI × sin(2ωt + θ) (17) has a frequency equal to twice the line frequency. Because the
V(t)  2  V  sin(ωt  θ ) (18) ripple is sinusoidal in nature, it is removed when the reactive
power signal is integrated to compute the reactive energy (see
I(t)  2  I  sin(ωt ) (19) the Reactive Energy Calculation section).
 The ADE7953 computes the reactive power simultaneously
I’(t) = 2  I  sin ωt   (20) on Current Channel A and Current Channel B and stores the
 2
resulting measurements in the AVAR (Address 0x214 and
where: Address 0x314) and BVAR (Address 0x215 and Address 0x315)
V is the rms voltage. registers, respectively. With full-scale inputs, the expected
I is the rms current. reading in the AVAR and BVAR registers is approximately
θ is the phase difference between the voltage and current channel. 4862401 LSBs (decimal).
The average reactive power over an integral number of line The reactive power registers are updated at a rate of 6.99 kHz
cycles (n) is given by the expression in Equation 21. and can be read using the waveform sampling mode (see the
1 nT Instantaneous Powers and Waveform Sampling section).
RP   RP(t )dt  VI  sin(θ ) (21)
nT 0 SIGN OF REACTIVE POWER CALCULATION
where: The reactive power measurement in the ADE7953 is a signed
RP is the reactive power. calculation. If the current waveform is leading the voltage wave-
T is the line cycle period. form, the reactive power is negative. Negative reactive power
The reactive power is equal to the dc component of the indicates a capacitive load. If the current waveform is lagging
instantaneous reactive power signal (RP(t) in Equation 16). the voltage waveform, the reactive power is positive. Positive
This relationship is used to calculate reactive power in the reactive power indicates an inductive load. The ACCMODE
ADE7953. The signal chain for the reactive power and energy register (Address 0x201 and Address 0x301) includes two sign
calculations in the ADE7953 is shown in Figure 51. indication bits that show the sign of the reactive power of
Current Channel A (VARSIGN_A) and Current Channel B
The instantaneous reactive power signal RP(t) is generated by (VARSIGN_B). See the Sign Indication section for more
multiplying the current signal and the voltage signal. Simulta- information.
neous calculations are performed using Current Channel A and
Current Channel B. The multiplication is performed over the full
1.23 kHz bandwidth and results in a reactive power measurement
that includes all harmonics included in this range.

xVARGAIN
CURRENT
CHANNEL 48 0
A OR B REACTIVE INTERNAL RENERGYx
POWER ACCUMULATION 23 0
ALGORITHM + +
VOLTAGE
CHANNEL FIXED INTERNAL
THRESHOLD
09320-120

REACTIVE xVAROS
POWER
SIGNAL

Figure 51. Reactive Energy Signal Chain

Rev. C | Page 28 of 72
Data Sheet ADE7953
REACTIVE ENERGY CALCULATION Reactive Energy Integration Time Under Steady Load
The ADE7953 achieves the integration of the reactive power The discrete time sample period (T) for the accumulation registers
signal in two stages. In the first stage, the reactive power signals is 4.83 μs (1/206.9 kHz). With full-scale sinusoidal signals on
are accumulated in an internal 48-bit register every 143 μs the analog inputs and a phase shift of 90°, a pulse is generated
(6.99 kHz) until an internal fixed threshold is reached. When and added to the RENERGYA and RENERGYB registers every
this threshold is reached, a pulse is generated and is accumu- 4.83 μs, assuming that the AVARGAIN and BVARGAIN
lated in 24-bit, user-accessible accumulation registers. The registers are set to 0x00. The maximum positive value that can
internal threshold results in a maximum accumulation rate be stored in the 24-bit RENERGYA and RENERGYB registers is
of approximately 206.9 kHz with full-scale inputs. This process 0x7FFFFF before the register overflows. The integration time
occurs simultaneously on Current Channel A and Current under these conditions can be calculated as follows:
Channel B, and the resulting readings can be read in the Time = 0x7FFFFF × 4.83 μs = 40.5 sec (22)
24-bit RENERGYA (Address 0x220 and Address 0x320) and
Reactive Energy Line Cycle Accumulation Mode
RENERGYB (Address 0x221 and Address 0x321) registers.
Both stages of the accumulation are signed and, therefore, In reactive energy line cycle accumulation mode, the energy
negative energy is subtracted from positive energy. accumulation of the ADE7953 is synchronized to the voltage
channel zero crossing so that the reactive energy on Current
Note that the reactive energy register contents roll over to full-
Channel A and Current Channel B can be accumulated over
scale negative (0x800000) and continue to increase in value
an integral number of half line cycles. Line cycle accumulation
when the power or energy flow is positive. Conversely, if the
mode is disabled by default and can be enabled on Current
power is negative, the energy register underflows to full-scale
Channel A and Current Channel B by setting the ALVAR and
positive (0x7FFFFF) and continues to decrease in value.
BLVAR bits to 1 in the LCYCMODE register (Address 0x004).
RENERGYA and RENERGYB are read-with-reset registers
The accumulation time should be written to the LINECYC
by default. This means that the contents of these registers are
register (Address 0x101) in the unit of number of half line cycles.
reset to 0 after a read operation. This feature can be disabled
The number of half line cycles written to the LINECYC register
by clearing Bit 6 (RSTREAD) of the LCYCMODE register
is used for both the Current Channel A and Current Channel B
(Address 0x004).
accumulation periods. The ADE7953 can accumulate reactive
The ADE7953 includes two sets of interrupts that are triggered energy for up to 65,535 half line cycles. This equates to an accu-
when the reactive energy register is half full (positive or negative) mulation period of approximately 655 sec with 50 Hz inputs
or when an overflow or underflow condition occurs. The first set and 546 sec with 60 Hz inputs.
of interrupts is associated with the Current Channel A reactive
At the end of a line cycle accumulation cycle, the RENERGYA and
energy, and the second set of interrupts is associated with the
RENERGYB registers are updated, and the CYCEND flag in the
Current Channel B reactive energy. These interrupts are disabled
IRQSTATA register (Address 0x22D and Address 0x32D) is set.
by default and can be enabled by setting the VAREHFA and
If the CYCEND bit in the IRQENA register is set, an external
VAREOFA bits in the IRQENA register (Address 0x22C and
interrupt is issued on the IRQ pin. In this way, the IRQ pin can
Address 0x32C) for Current Channel A, and the VAREHFB and
also be used to signal the completion of the line cycle accumula-
VAREOFB bits in the IRQENB register (Address 0x22F and
tion. Another accumulation cycle begins immediately as long as the
Address 0x32F) for Current Channel B.
ALVAR and BLVAR bits in the LCYCMODE register remain set.

xVARGAIN xVAROS

48 0
+
OUTPUT FROM + INTERNAL
LPF2 ACCUMULATION

FIXED INTERNAL
THRESHOLD

OUTPUT FROM ZERO-CROSSING CALIBRATION

VOLTAGE CHANNEL DETECTION CONTROL
ADC LPF1
23 0
RENERGYx
09320-021

15 0
LINECYC

Figure 52. Reactive Energy Line Cycle Accumulation

Rev. C | Page 29 of 72
ADE7953 Data Sheet
The contents of the RENERGYA and RENERGYB registers are
updated synchronous to the CYCEND flag. The RENERGYA
and RENERGYB registers hold their current values until the
end of the next line cycle period, when the contents are replaced
with the new reading. If the read-with-reset bit (RSTREAD) in RENERGYx
the LCYCMODE register (Address 0x004) is set, the contents of
the RENERGYA and RENERGYB registers are cleared after a
NO-LOAD
read and remain at 0 until the end of the next line cycle period. THRESHOLD

If a new value is written to the LINECYC register (Address 0x101)

REACTIVE POWER
midway through a line cycle accumulation, the new value is not
internally loaded until the end of a line cycle period. When the NO-LOAD
THRESHOLD
LINECYC register is updated mid-reading, the current energy
accumulation cycle is completed, and the new value is then
programmed, ready for the next cycle. This prevents any invalid
readings due to changes to the LINECYC register (see Figure 47). NO-LOAD
THRESHOLD
Note that when line cycle accumulation mode is first enabled, the
reading after the first CYCEND flag should be ignored because ACTIVE POWER

it may be inaccurate. This is because the line cycle accumulation NO-LOAD

09320-022
THRESHOLD
mode is not synchronized to the zero crossing and, therefore,
the first reading may not be over a complete number of half line Figure 53. Reactive Energy Accumulation in Antitamper Accumulation Mode
cycles. After the first line cycle accumulation is complete, all
successive readings will be correct. Absolute Accumulation Mode
REACTIVE ENERGY ACCUMULATION MODES The ADE7953 includes an absolute energy accumulation mode
for Current Channel A and Current Channel B reactive energy.
Signed Accumulation Mode
In absolute accumulation mode, the energy accumulation is done
The default reactive energy accumulation mode for the ADE7953 is using the absolute reactive power, ignoring any occurrences of
a signed accumulation based on the reactive power information. energy below the no-load threshold (see Figure 54).
Antitamper Accumulation Mode
The ADE7953 includes an antitamper accumulation mode that
accumulates reactive energy depending on the sign of the active
power. When the active power is positive, the reactive power is
added to the reactive energy accumulation register. When the
active power is negative, the reactive power is subtracted from RENERGYx
the reactive energy accumulation register (see Figure 53).
Antitamper accumulation mode is disabled by default and can
be enabled on Current Channel A and Current Channel B by NO-LOAD
THRESHOLD
setting the AVARACC and BVARACC bits to 01 in the ACCMODE
register (Address 0x201 and Address 0x301). If enabled, the REACTIVE POWER
antitamper accumulation mode affects both reactive energy NO-LOAD
accumulation registers, RENERGYA and RENERGYB, as well THRESHOLD
09320-023

as the CF output pins (see the Energy-to-Frequency Conversion

section). Figure 54. Reactive Energy Absolute Accumulation Mode

The absolute accumulation mode is disabled by default and

can be enabled on Current Channel A and Current Channel B
by setting the AVARACC and BVARACC bits to 10 in the
ACCMODE register (Address 0x201 and Address 0x301).
If enabled, the absolute accumulation mode affects both energy
accumulation registers, RENERGYA and RENERGYB, as well
as the CF output pins (see the Energy-to-Frequency Conversion
section).

Rev. C | Page 30 of 72
Data Sheet ADE7953

APPARENT POWER CALCULATION

Apparent power is defined as the maximum power that can be This process occurs simultaneously on Current Channel A and
delivered to a load. VRMS and IRMS are the effective voltage Current Channel B, and the resulting readings can be read in the
and current delivered to the load, respectively. The apparent 24-bit APENERGYA (Address 0x222 and Address 0x322) and
power can, therefore, be defined as the product of VRMS and APENERGYB (Address 0x223 and Address 0x323) registers.
IRMS. This relationship is independent of the phase angle Note that the apparent energy register contents roll over to full-
between the voltage and current. scale negative (0x800000) and continue to increase in value
Equation 26 provides an expression for the instantaneous when the power or energy flow is positive. Conversely, if the
apparent power signal in an ac signal. power is negative, the energy register underflows to full-scale
positive (0x7FFFFF) and continues to decrease in value.
V(t)  2  VRMS  sin(ωt ) (23)
APENERGYA and APENERGYB are read-with-reset registers
I(t)  2  IRMS  sin(ωt  θ ) (24) by default. This means that the contents of these registers are
reset to 0 after a read operation. This feature can be disabled
P(t) = V(t) × I(t) (25)
by clearing Bit 6 (RSTREAD) of the LCYCMODE register
P(t) = VRMS × IRMS × cos(θ) − (26) (Address 0x004).
VRMS × IRMS × cos(2ωt + θ)
The ADE7953 includes two sets of interrupts that are triggered
The ADE7953 computes the apparent power simultaneously when the apparent energy register is half full (positive or
on Current Channel A and Current Channel B and stores negative) or when an overflow or underflow condition occurs.
the resulting measurements in the AVA (Address 0x210 and The first set of interrupts is associated with the Current
Address 0x310) and BVA (Address 0x211 and Address 0x311) Channel A apparent energy, and the second set of interrupts
registers, respectively. is associated with the Current Channel B apparent energy.
The apparent power measurement is taken over a bandwidth These interrupts are disabled by default and can be enabled by
of 1.23 kHz and includes the effects of any harmonics within setting the VAEHFA and VAEOFA bits in the IRQENA register
that range. The apparent power registers are updated at a rate of (Address 0x22C and Address 0x32C) for Current Channel A,
6.99 kHz and can be read using the waveform sampling mode and the VAEHFB and VAEOFB bits in the IRQENB register
(see the Instantaneous Powers and Waveform Sampling section). (Address 0x22F and Address 0x32F) for Current Channel B.
APPARENT ENERGY CALCULATION Apparent Energy Integration Time Under Steady Load
The apparent energy is given as the integral of the apparent The discrete time sample period (T) for the accumulation
power. registers is 4.83 μs (1/206.9 kHz). With full-scale sinusoidal
signals on the analog inputs, a pulse is generated and added
Apparent Energy   Apparent Power(t)dt (27)
to the APENERGYA and APENERGYB registers every 4.83 μs,
The ADE7953 achieves the integration of the apparent power assuming that the AVAGAIN and BVAGAIN registers are set
signal in two stages. In the first stage, the apparent power to 0x00. The maximum positive value that can be stored in the
signals are accumulated in an internal 48-bit register every 24-bit APENERGYA and APENERGYB registers is 0x7FFFFF
143 μs (6.99 kHz) until an internal fixed threshold is reached. before the register overflows. The integration time under these
When this threshold is reached, a pulse is generated and is conditions can be calculated as follows:
accumulated in 24-bit, user accessible accumulation registers. Time = 0x7FFFFF × 4.83 μs = 40.5 sec (28)
The internal threshold results in a maximum accumulation rate
of approximately 206.9 kHz with full-scale inputs.

xVAGAIN
CURRENT RMS
CHANNEL 48 0
A OR B
INTERNAL APENERGYx
ACCUMULATION 23 0
+
VOLTAGE +
RMS FIXED INTERNAL
THRESHOLD
APPARENT xVAOS
09320-024

POWER
SIGNAL

Figure 55. Apparent Energy Accumulation Signal Chain

Rev. C | Page 31 of 72
ADE7953 Data Sheet
xVAGAIN xVAOS

48 0
APPARENT +
+ INTERNAL
POWER ACCUMULATION
SIGNAL

FIXED INTERNAL
THRESHOLD

OUTPUT FROM ZERO-CROSSING CALIBRATION

VOLTAGE CHANNEL DETECTION CONTROL
ADC LPF1
23 0
APENERGYx

09320-125
15 0
LINECYC

Figure 56. Apparent Energy Line Cycle Accumulation

Apparent Energy Line Cycle Accumulation Mode If a new value is written to the LINECYC register (Address 0x101)
In apparent energy line cycle accumulation mode, the energy midway through a line cycle accumulation, the new value is not
accumulation of the ADE7953 is synchronized to the voltage internally loaded until the end of a line cycle period. When the
channel zero crossing so that the apparent energy on Current LINECYC register is updated mid-reading, the current energy
Channel A and Current Channel B can be accumulated over accumulation cycle is completed, and the new value is then
an integral number of half line cycles. Line cycle accumulation programmed, ready for the next cycle. This prevents any invalid
mode is disabled by default and can be enabled on Current readings due to changes to the LINECYC register (see Figure 47).
Channel A and Current Channel B by setting the ALVA and Note that when line cycle accumulation mode is first enabled, the
BLVA bits to 1 in the LCYCMODE register (Address 0x004). reading after the first CYCEND flag should be ignored because
The accumulation time should be written to the LINECYC it may be inaccurate. This is because the line cycle accumulation
register (Address 0x101) in the unit of number of half line cycles. mode is not synchronized to the zero crossing and, therefore,
The number of half line cycles written to the LINECYC register the first reading may not be over a complete number of half line
is used for both the Current Channel A and Current Channel B cycles. After the first line cycle accumulation is complete, all
accumulation periods. The ADE7953 can accumulate apparent successive readings will be correct.
energy for up to 65,535 half line cycles. This equates to an accu- AMPERE-HOUR ACCUMULATION
mulation period of approximately 655 sec with 50 Hz inputs
In a tampering situation where no voltage is available to the energy
and 546 sec with 60 Hz inputs.
meter, the ADE7953 can accumulate the ampere-hour measure-
At the end of a line cycle accumulation cycle, the APENERGYA ment instead of the apparent power in the APENERGYA and
and APENERGYB registers are updated, and the CYCEND flag APENERGYB registers. If enabled, the Current Channel A and
in the IRQSTATA register (Address 0x22D and Address 0x32D) Current Channel B IRMS measurements are continually accu-
is set. If the CYCEND bit in the IRQENA register is set, an external mulated instead of the apparent power. If enabled, the apparent
interrupt is issued on the IRQ pin. In this way, the IRQ pin can power CF output pin also reflects the ampere-hour measurement
also be used to signal the completion of the line cycle accumula- (see the Energy-to-Frequency Conversion section). All the signal
tion. Another accumulation cycle begins immediately, as long as processing and calibration registers available for the apparent
the ALVA and BLVA bits in the LCYCMODE register remain set. power and apparent energy accumulation remain active when
The contents of the APENERGYA and APENERGYB registers the ampere-hour accumulation mode is enabled. This includes
are updated synchronous to the CYCEND flag. The APENERGYA the apparent energy no-load feature (see the Apparent Energy
and APENERGYB registers hold their current values until the No-Load section). Recalibration is required in this mode due
end of the next line cycle period, when the contents are replaced to internal scaling differences between the IRMS and apparent
with the new reading. If the read-with-reset bit (RSTREAD) in signals.
the LCYCMODE register (Address 0x004) is set, the contents of
the APENERGYA and APENERGYB registers are cleared after
a read and remain at 0 until the end of the next line cycle period.

Rev. C | Page 32 of 72
Data Sheet ADE7953

ENERGY-TO-FREQUENCY CONVERSION
The ADE7953 provides two energy-to-frequency conversions for The CF1 and CF2 pins can be configured to output a signal that
calibration purposes. After initial calibration at manufacturing, is proportional to the active power, reactive power, apparent
the manufacturer or end customer is often required to verify the power, or IRMS on Current Channel A or Current Channel B.
meter accuracy. One convenient way to do this is to provide an In addition, it is possible to configure CF1 and CF2 to output a
output frequency that is proportional to the active, reactive, or signal that is proportional to the sum of the Current Channel A
apparent power, or to the current rms under steady load condi- IRMS and the Current Channel B IRMS, or, alternatively, propor-
tions. This output frequency provides a simple single-wire tional to the sum of the active power on Current Channel A and
interface that can be optically isolated to interface to external the active power on Current Channel B. Recalibration is required
calibration equipment. The ADE7953 includes two fully in this configuration because the actual CF output equals the sum
programmable calibration frequency output pins: CF1 (Pin 23) of the active power on Current Channel A and the active power
and CF2 (Pin 24). The energy-to-frequency conversion is on Current Channel B, divided by 2. The CF1 and CF2 output
illustrated in Figure 57. pins are programmed by setting the CF1SEL and CF2SEL bits
CFxSEL BITS in the CFMODE register (Address 0x107).
IN CFMODE REGISTER
1 Both pulse outputs (CF1 and CF2) are disabled by default
VA
IRMS and can be enabled by clearing the CF1DIS and CF2DIS bits,
VAR CFx PULSE
WATT
DFC ÷
OUTPUT respectively, in the CFMODE register (Address 0x107).
IRMSA + IRMSB
PULSE OUTPUT CHARACTERISTICS
09320-026

AWATT + BWATT
CFxDEN

Figure 57. Energy-to-Frequency Conversion

The pulse outputs for both DFCs stay low for 80 ms if the pulse
period is longer than 160 ms (6.25 Hz). If the pulse period is
Two digital-to-frequency converters (DFCs) are used to generate shorter than 160 ms, the duty cycle of the pulse outputs is 50%.
the pulse outputs. The DFC generates a pulse each time ±1 LSB The pulse outputs are active low. The maximum output frequency
is accumulated in the energy register. An output pulse is gener- with ac inputs at full scale and with CFxDEN = 0x00 is approxi-
ated when CFxDEN number of pulses is generated at the DFC mately 206.9 kHz.
output.
The ADE7953 includes two unsigned 16-bit registers, CF1DEN
(Address 0x103) and CF2DEN (Address 0x104) that control the
CF output frequency on the CF1 and CF2 pins, respectively. The
16-bit frequency scaling registers can scale the output frequency
by 1/(216 – 1) to 1 with a step of 1/(216 – 1). Note that when
modifying the CF1DEN and CF2DEN registers, two sequential
write operations must be performed to ensure that the write is
successful.

Rev. C | Page 33 of 72
ADE7953 Data Sheet

ENERGY CALIBRATION
GAIN CALIBRATION Current Channel Gain Adjustment
The active, reactive, and apparent power measurements can A gain calibration register is also provided on Current Channel B.
be calibrated on Current Channel A and Current Channel B This register can be used to match Current Channel B to Current
separately. This allows meter-to-meter gain variation to be Channel A for simple calibration and computation. The Current
compensated for. Channel B gain calibration is performed using the BIGAIN register
(Address 0x28C and Address 0x38C). Equation 32 shows the
The AWGAIN register (Address 0x282 and Address 0x382)
relationship between the gain adjustment and the IRMSB register.
controls the active power gain calibration on Current Channel A,
and the BWGAIN register (Address 0x28E and Address 0x38E) IRMSB Expected = (32)
controls the active power gain calibration on Current Channel B.  BIGAIN 
The default value of the xWGAIN registers is 0x400000, which IRMSB INITIAL ×  
 0x400000 
corresponds to no gain calibration. The minimum value that can be  
written to the xWGAIN registers is 0x200000, which represents a Similar registers are available for the voltage channel and for
gain adjustment of −50%. The maximum value that can be Current Channel A: the AVGAIN register (Address 0x281 and
written to the xWGAIN registers is 0x600000, which represents Address 0x381) and BVGAIN register (Address 0x28D and
a gain adjustment of +50%. Equation 29 shows the relationship Address 0x38D). Only the AVGAIN register affects the RMS
between the gain adjustment and the xWGAIN registers. reading but to avoid discrepancies in other registers if AVGAIN
Output Power (W) = (29) is set then BVGAIN should be set to the same value. The
AIGAIN register (Address 0x280 and Address 0x380) provides
 xWGAIN  the calibration adjustment and function in the same way as the
Active Power ×  
 0x400000  BIGAIN register.
 
Similar gain calibration registers are available for the reactive PHASE CALIBRATION
power and the apparent power. The reactive power on Current The ADE7953 is designed to function with a variety of current
Channel A and Current Channel B can be gain calibrated using transducers, including those that induce inherent phase errors.
the AVARGAIN (Address 0x283 and Address 0x383) and A phase error of 0.1° to 0.3° is not uncommon for a current
BVARGAIN (Address 0x28F and Address 0x38F) registers, transformer (CT). These phase errors can vary from part to
respectively. The apparent power on Current Channel A and part, and they must be corrected to achieve accurate power
Current Channel B can be gain calibrated using the AVAGAIN readings. The errors associated with phase mismatch are
(Address 0x284 and Address 0x384) and BVAGAIN particularly noticeable at low power factors. The ADE7953
(Address 0x290 and Address 0x390) registers, respectively. provides a means of digitally calibrating these small phase
The xVARGAIN and xVAGAIN registers affect the reactive and errors by introducing a time delay or a time advance.
apparent powers in the same way that the xWGAIN registers
affect the active power. Equation 29 can therefore be modified Because different sensors can be used on Current Channel A
to represent the gain calibration of the reactive and apparent and Current Channel B, separate phase calibration registers are
powers, as shown in Equation 30 and Equation 31. included on each channel. The PHCALA register (Address 0x108)
can be used to correct phase errors on Current Channel A, and
Output Power (VAR) = (30) the PHCALB register (Address 0x109) can be used to correct
 xVARGAIN  phase errors on Current Channel B. Both registers are in 10-bit
Reactive Power ×  
  sign magnitude format, with the MSB indicating whether a time
 0x400000 
delay or a time advance is added to the corresponding current
channel. Writing a 0 to the MSB of the PHCALx register intro-
Output Power (VA) = (31)
duces a time delay to the current channel. Writing a 1 to the
 xVAGAIN  MSB of the PHCALx register introduces a time advance.
Apparent Power ×  
 0x400000 
  The maximum range that can be written to PHCALx[8:0] is
383 (decimal). One LSB of the PHCALx register is equivalent to
a time delay or time advance of 1.117 µs (CLKIN/4). With a line
frequency of 50 Hz, the resolution is 0.02°/LSB ((360 × 50 Hz)/
895 kHz), which provides a total correction of 7.66° in either
direction. With a line frequency of 60 Hz, the resolution is
0.024°/LSB ((360 × 60 Hz)/895 kHz), which provides a total
correction of 9.192° in either direction.

Rev. C | Page 34 of 72
Data Sheet ADE7953
OFFSET CALIBRATION RMS Offsets
Power Offsets The ADE7953 includes offset calibration registers to allow offset
The ADE7953 includes offset calibration registers for the active, in the rms measurements to be corrected. Offset calibration
reactive, and apparent powers on Current Channel A and Current registers are available for the IRMS measurements on Current
Channel B. Offsets can exist in the power calculations due to Channel A and Current Channel B, as well as for the VRMS
crosstalk between channels on the PCB and in the ADE7953. measurement. Offset can exist in the rms calculation due to
The offset calibration allows these offsets to be removed to input noise that is integrated in the dc component of V2(t). The
increase the accuracy of the measurement at low input levels. offset calibration allows these offsets to be removed to increase
the accuracy of the measurement at low input levels.
The active power offset can be corrected on Current Channel A
and Current Channel B by adjusting the AWATTOS (Address The voltage rms offset can be corrected by adjusting the VRMSOS
0x289 and Address 0x389) and BWATTOS (Address 0x295 and register (Address 0x288 and Address 0x388). This 24-bit, signed
Address 0x395) registers, respectively. The xWATTOS registers twos complement register has a default value of 0, indicating
are 24-bit, signed twos complement registers with default that no offset is added. The VRMSOS value is applied prior to
values of 0. One LSB in the xWATTOS register is equivalent the square root function. Equation 33 shows the effect of the
to 0.001953 LSBs in the active power measurement. The VRMSOS register on the VRMS measurement.
xWATTOS value is, therefore, applied to the xWATT register, VRMS = VRMS0 2 + VRMSOS × 212 (33)
shifted by nine bits, as shown in Figure 58.
23 9 0 where VRMS 0 is the initial VRMS reading prior to offset
xWATTOS calibration.
The current rms offset is calibrated in a similar way. The AIRMSOS
09320-027

xWATT
23 0
register (Address 0x286 and Address 0x386) compensates for
offsets in the IRMSA measurement, and the BIRMSOS register
Figure 58. xWATTOS and xWATT Registers
(Address 0x292 and Address 0x392) compensates for offsets in
With full-scale inputs on the voltage and current channels, the the IRMSB measurement. Both registers are 24-bit, signed twos
expected power reading is approximately 4862401 LSBs (deci- complement registers. The xIRMSOS registers affect the IRMS
mal). At −60 dB (1000:1) on Current Channel A and Current measurements in the same way that the VRMSOS register
Channel B, the expected readings in the AWATT and BWATT affects the VRMS measurement. Equation 33 can therefore be
registers, respectively, are approximately 4862 (decimal). One modified to represent the offset calibration on the IRMS, as
LSB of the xWATT register, therefore, corresponds to shown in Equation 34 and Equation 35.
0.000039% at −60 dB.
IRMSA = IRMSA0 2 + AIRMSOS × 212 (34)
The reactive power offset can be corrected on Current Channel A
and Current Channel B by adjusting the AVAROS (Address IRMSB = IRMSB0 2 + BIRMSOS × 212 (35)
0x28A and Address 0x38A) and BVAROS (Address 0x296 and
Address 0x396) registers, respectively. The xVAROS registers Refer to the AN-1118 Application Note, Calibrating a Single-
affect the reactive power in the same way that the xWATTOS Phase Energy Meter Based on the ADE7953, for a more detailed
registers affect the active power. explanation on how to calibrate an energy meter based on the
The apparent power offset can be corrected on Current ADE7953.
Channel A and Current Channel B by adjusting the AVAOS
(Address 0x28B and Address 0x38B) and BVAOS (Address 0x297
and Address 0x397) registers, respectively. The xVAOS registers
affect the apparent power in the same way that the xWATTOS
registers affect the active power.

Rev. C | Page 35 of 72
ADE7953 Data Sheet

PERIOD MEASUREMENT
The ADE7953 provides a period measurement of the voltage The value of the period register for a 50 Hz network is approxi-
channel. This measurement is provided in the 16-bit, unsigned mately 4475 in decimal (223.75 kHz/50 Hz) and 3729 in
period register (Address 0x10E). The period register is updated decimal (223.75 kHz/60 Hz) for a 60 Hz network. The period
once every line period and has a settling time of 30 ms to 40 ms register is stable at ±1 LSB when the line is established and the
associated with it before the period measurement is stable. measurement does not change.
The period measurement has a resolution of 4.47 µs/LSB The following equation can be used to compute the line period
(223.75 kHz clock), which represents 0.02235% when the line and frequency using the period register:
frequency is 50 Hz and 0.02682% when the line frequency PERIOD[15:0] + 1
is 60 Hz. TL = sec (36)
223.75 kHz

Rev. C | Page 36 of 72
Data Sheet ADE7953

INSTANTANEOUS POWERS AND WAVEFORM SAMPLING

The ADE7953 provides access to the current and voltage Table 7. Waveform Sampling Registers
channel waveform data, along with the instantaneous active, Address
reactive, and apparent powers. This information allows the Measurement Register 24-Bit 32-Bit
instantaneous data to be analyzed in more detail, including Active power AWATT 0x212 0x312
reconstruction of the current and voltage input for harmonic (Current Channel A)
analyses. These measurements are available from a set of Active power BWATT 0x213 0x313
24-bit/32-bit signed registers (see Table 7). (Current Channel B)
Reactive power AVAR 0x214 0x314
All measurements are updated at a rate of 6.99 kHz (CLKIN/512).
(Current Channel A)
The ADE7953 provides an interrupt status bit, WSMP, that is
Reactive power BVAR 0x215 0x315
triggered at a rate of 6.99 kHz, allowing measurements to be (Current Channel B)
synchronized with the instantaneous signal update rate. This Apparent power AVA 0x210 0x310
status bit is available in the IRQSTATA register (Address 0x22D (Current Channel A)
and Address 0x32D). This signal can also be configured to Apparent power BVA 0x211 0x311
trigger an interrupt on the external IRQ pin by setting the (Current Channel B)
WSMP bit (Bit 17) in the IRQENA register (Address 0x22C Current IA 0x216 0x316
and Address 0x32C). (Current Channel A)
Current IB 0x217 0x317
The ADE7953 also provides the option of issuing an unlatched, (Current Channel B)
data-ready signal at the same rate of 6.99 kHz. This signal provides Voltage V 0x218 0x318
the same information as the WSMP interrupt, but it is unlatched (voltage channel)
and, therefore, does not need to be serviced each time that new
data is available. The data-ready signal goes high for a period of
280 ns before automatically returning low. The data-ready signal
is disabled by default and can be output on the REVP, ZX, and
ZX_I pins by setting the REVP_ALT, ZX_ALT, and ZXI_ALT
bits to 1001 in the ALT_OUTPUT register (Address 0x110).

Rev. C | Page 37 of 72
ADE7953 Data Sheet

POWER FACTOR
The ADE7953 provides a direct power factor measurement By default, the instantaneous active and apparent power
simultaneously on Current Channel A and Current Channel B. readings are used to calculate the power factor, and the register
Power factor in an ac circuit is defined as the ratio of the active is updated at a rate of 6.99 kHz. The sign bit is taken from the
power flowing to the load to the apparent power. The power instantaneous reactive energy measurement on each channel.
factor measurement is defined in terms of “leading” or “lagging,”
USING THE LINE CYCLE ACCUMULATION MODE
referring to whether the current waveform is leading or lagging
TO DETERMINE THE POWER FACTOR
the voltage waveform.
If a power factor measurement with more averaging is required,
When the current waveform is leading the voltage waveform,
the ADE7953 can use the line cycle accumulation measurement
the load is capacitive and is defined as a negative power factor.
on the active and apparent energies to determine the power factor
When the current waveform is lagging the voltage waveform, (see the Active Energy Line Cycle Accumulation Mode section
the load is inductive and is defined as a positive power factor. and the Apparent Energy Line Cycle Accumulation Mode
The relationship of the current waveform to the voltage wave- section). This option provides a more stable power factor
form is illustrated in Figure 59. reading.
ACTIVE (–)
REACTIVE (–)
ACTIVE (+)
REACTIVE (–)
To use the line cycle accumulation mode to determine the power
I
CAPACITIVE LOAD:
factor, the ADE7953 must be configured as follows:
CURRENT LEADS
VOLTAGE • The PFMODE bit (Bit 3) must be set to 1 in the CONFIG
+60° = θ; PF = –0.5
V register (Address 0x102).
–60° = θ; PF = +0.5
• The line cycle accumulation mode must be enabled on
both the active and apparent energies by setting the
INDUCTIVE LOAD:
CURRENT LAGS xLWATT and xLVA bits to 1 in the LCYCMODE register
I VOLTAGE (Address 0x004).
09320-028

ACTIVE (–) ACTIVE (+)

REACTIVE (+) REACTIVE (+)
When using line cycle accumulation to determine the power
Figure 59. Capacitive and Inductive Loads
factor, the update rate of the power factor measurement is an
As shown in Figure 59, the reactive power measurement is integral number of half line cycles. The number of half line cycles
negative when the load is capacitive and positive when the is programmed in the LINECYC register (Address 0x101). For
load is inductive. The sign of the reactive power can therefore complete information about setting up the line cycle accumula-
be used to reflect the sign of the power factor. tion mode, see the Active Energy Line Cycle Accumulation
The mathematical definition of power factor is shown in Mode section and the Apparent Energy Line Cycle
Equation 37. Accumulation Mode section.

Power Factor = (Sign of Reactive Power ) ×

| Active Power | (37) POWER FACTOR WITH NO-LOAD DETECTION
Apparent Power
The power factor measurement is affected by the no-load
The absolute value of active power is used. condition if no-load detection is enabled (see the No-Load
The power factor measurement includes the effect of all Detection section). The following considerations apply only
harmonics over the 1.23 kHz bandwidth. when no-load detection is enabled and a no-load condition
occurs:
The power factor readings are stored in two 16-bit, signed
registers: PFA (Address 0x10A) for Current Channel A and • If the apparent energy no-load condition is true, the power
PFB (Address 0x10B) for Current Channel B. These registers are factor measurement is set to 1 because it is assumed that
signed, twos complement registers with the MSB indicating the there is no active or reactive power.
polarity of the power factor. Each LSB of the PFx register equates • If the active energy no-load condition is true, the power
to a weight of 2−15; therefore, the maximum register value of factor measurement is set to 0 because it is assumed that
0x7FFF corresponds to a power factor value of 1. The minimum the load is purely capacitive or inductive.
register value of 0x8000 corresponds to a power factor of −1. • If the reactive energy no-load condition is true, the sign of
the power factor is based on the sign of the active power.

Rev. C | Page 38 of 72
Data Sheet ADE7953
ANGLE MEASUREMENT The time delay between the current and voltage inputs can be
The ADE7953 can measure the time delay between the current used to characterize how balanced the load is. The delays between
and voltage inputs. This feature is available on both Current phase voltages and currents can be used to compute the power
Channel A and Current Channel B. The negative-to-positive factor on Current Channel A and Current Channel B, respec-
transitions identified by the zero-crossing detection circuit are tively, as shown in Equation 38.
used as a start and stop for the measurement (see Figure 60).  360   f LINE 
cos  x  cos  ANGLE _ x   (38)
PHASE A  223 kHz 
VOLTAGE 
PHASE A
CURRENT where:
x = A or B.
fLINE is 50 Hz or 60 Hz.
This method of determining the power factor does not take into

09320-031
ANGLE_x account the effect of any harmonics. Therefore, it may not be
Figure 60. Current-to-Voltage Time Delay equal to the true definition of power factor shown in Equation 37.

The ADE7953 provides a time delay measurement on Current

Channel A and Current Channel B simultaneously. The result-
ing measurements are available in the 16-bit, signed registers
ANGLE_A (Address 0x10C) and ANGLE_B (Address 0x10D).
One LSB of the ANGLE_A or ANGLE_B register corresponds
to 4.47 μs (223 kHz clock). This results in a resolution of
0.0807° at 50 Hz ((360 × 50)/223 kHz) and 0.0969° at 60 Hz
((360 × 60)/223 kHz).

Rev. C | Page 39 of 72
ADE7953 Data Sheet

NO-LOAD DETECTION
The ADE7953 includes a no-load detection feature that eliminates ACTIVE ENERGY NO-LOAD DETECTION
“meter creep.” Meter creep is defined as excess energy that is Active energy no-load detection can be used in conjunction with
accumulated by the meter when there is no load attached. The reactive energy no-load detection to establish a “true” no-load
ADE7953 warns of this condition and stops energy accumula- feature. If both the active and reactive energy fall below the
tion if the energy falls below a programmable threshold. The no-load threshold, there is no resistive, inductive, or capacitive
ADE7953 includes a no-load feature on the active, reactive, and load. The active energy no-load feature can also be used to
apparent energy measurements. This allows a true no-load prevent creep of the active energy when there is an inductive
condition to be detected and also prevents creep in purely or capacitive load present.
resistive, inductive, or capacitive load conditions. The no-load
feature is enabled by default. It is guaranteed that the CF pulses If the active energy on either Current Channel A (phase)
and the energy register will remain in sync even after a no-load or Current Channel B (neutral) falls below the programmed
condition. threshold, the active energy on that channel ceases to accumu-
late in the AENERGYA and AENERGYB registers, respectively.
SETTING THE NO-LOAD THRESHOLDS If either the CF1 or CF2 pin is programmed to output active
Three separate 24-/32-bit registers are available to set the energy, the CF output is disabled and held high (see the Energy-
no-load threshold on the active, reactive, and apparent to-Frequency Conversion section). If enabled, the active reverse
energies: AP_NOLOAD (Address 0x203 and Address 0x303), power indication (REVP) holds its current state while in the no-
VAR_NOLOAD (Address 0x204 and Address 0x304), and load condition (see the Reverse Power section). The Current
VA_NOLOAD (Address 0x205 and Address 0x305). The active, Channel A active energy no-load condition is indicated by the
reactive, and apparent energy no-load thresholds are completely AP_NOLOADA bit (Bit 6) in the IRQSTATA register (Address
independent and, therefore, all three thresholds are required. 0x22D and Address 0x32D). The Current Channel B active energy
The no-load thresholds for all three measurements can be set no-load condition is indicated by the AP_NOLOADB bit (Bit 6)
based on Equation 39. in the IRQSTATB register (Address 0x230 and Address 0x330).
Y Current Channel A and Current Channel B are independent
X_NOLOAD = 65,536 − (39)
1. 4 and, therefore, a no-load condition on Current Channel A
where: affects only the energy accumulation, CF output, and reverse
X is AP, VAR, or VA. power of Current Channel A, and vice versa.
Y is the required threshold amplitude with reference to The active energy no-load feature is enabled by default and
full-scale energy (for example 20,000:1). can be disabled by setting Bit 0 in the DISNOLOAD register
As shown in Equation 39, the no-load threshold can be config- (Address 0x001) to 1.
ured based on the required level with respect to full scale. For Active Energy No-Load Interrupt
example, if a no-load threshold of 10,000:1 of the full-scale Two interrupts are associated with the active energy no-load
current channel is required and the voltage channel is set up to feature: one for Current Channel A (phase) and one for Current
operate at ±250 mV (50% of full scale), then a value of 20,000 is Channel B (neutral). If enabled, these interrupts are triggered
required for Y. A default value of 58,393 (decimal) is programmed when the active energy falls below the programmed threshold.
into the AP_NOLOAD and VAR_NOLOAD registers, setting
the initial no-load threshold to approximately 10,000:1. The The Current Channel A active energy no-load interrupt can be
VA_NOLOAD register has a default value of 0x00. enabled by setting the AP_NOLOADA bit (Bit 6) in the IRQENA
register (Address 0x22C and Address 0x32C). When this bit is set,
The no-load thresholds AP_NOLOAD, VAR_NOLOAD, and an active energy no-load event on Current Channel A causes
VA_NOLOAD must be written before enabling the no-load the IRQ pin (Pin 22) to fall to 0 (see the Primary Interrupts
feature. The no-load feature is enabled using the DISNOLOAD
(Voltage Channel and Current Channel A) section).
register (Address 0x001). If the threshold requires modification,
disable the no-load detection, modify the threshold, and then The Current Channel B active energy no-load interrupt can be
reenable the feature using the DISNOLOAD register. enabled by setting the AP_NOLOADB bit (Bit 6) in the IRQENB
register (Address 0x22F and Address 0x32F). When this bit is set,
Although separate no-load interrupts are available for Current an active energy no-load event on Current Channel B triggers
Channel A and Current Channel B (phase and neutral current),
the IRQ alternative output (see the Current Channel B Interrupts
the same no-load level is used for both. For example, if the
section).
VAR_NOLOAD level is set to 0.05% of full scale, this value is
the reactive power no-load threshold used for both Current
Channel A (phase) and Current Channel B (neutral).

Rev. C | Page 40 of 72
Data Sheet ADE7953
Active Energy No-Load Status Bits The Current Channel B reactive energy no-load interrupt can be
In addition to the active energy no-load interrupt, the ADE7953 enabled by setting the VAR_NOLOADB bit (Bit 7) in the IRQENB
includes two unlatched status bits that continually monitor the register (Address 0x22F and Address 0x32F). When this bit is set, a
no-load status of Current Channel A and Current Channel B. reactive power no-load event on Current Channel B triggers the
The ACTNLOAD_A and ACTNLOAD_B bits are located in the IRQ alternative output (see the Current Channel B Interrupts
ACCMODE register (Address 0x201 and Address 0x301). These section).
bits differ from the interrupt status bits in that they are unlatched Reactive Energy No-Load Status Bits
and can, therefore, be used to drive an LED.
In addition to the reactive energy no-load interrupt, the
REACTIVE ENERGY NO-LOAD DETECTION ADE7953 includes two unlatched status bits that continually
Reactive energy no-load detection can be used in conjunction monitor the no-load status of Current Channel A and Current
with active energy no-load detection to establish a “true” no-load Channel B. The VARNLOAD_A and VARNLOAD_B bits are
feature. If both the reactive and active energy fall below the no-load located in the ACCMODE register (Address 0x201 and Address
threshold, there is no resistive, inductive, or capacitive load. The 0x301). These bits differ from the interrupt status bits in that
reactive energy no-load feature can also be used to prevent creep they are unlatched and can, therefore, be used to drive an LED.
of the reactive energy when there is a resistive load present. APPARENT ENERGY NO-LOAD DETECTION
If the reactive energy on either Current Channel A (phase) or Apparent energy no-load detection can be used to determine
Current Channel B (neutral) falls below the programmed thresh- whether the total consumed energy is below the no-load thresh-
old, the reactive energy on that channel ceases to accumulate in old. If the apparent energy on either Current Channel A (phase)
the RENERGYA and RENERGYB registers, respectively. If either or Current Channel B (neutral) falls below the programmed
the CF1 or CF2 pin is programmed to output reactive energy, the threshold, the apparent energy on that channel ceases to
CF output is disabled and held high (see the Energy-to-Frequency accumulate in the APENERGYA and APENERGYB registers,
Conversion section). If enabled, the reactive reverse power indi- respectively. If either the CF1 or CF2 pin is programmed to
cation holds its current state while in the no-load condition (see output apparent energy, the CF output is disabled and held high
the Reverse Power section). The Current Channel A reactive (see the Energy-to-Frequency Conversion section). The Current
energy no-load condition is indicated by the VAR_NOLOADA Channel A apparent energy no-load condition is indicated by the
bit (Bit 7) in the IRQSTATA register (Address 0x22D and VA_NOLOADA bit (Bit 8) in the IRQSTATA register (Address
Address 0x32D). The Current Channel B reactive energy no- 0x22D and Address 0x32D). The Current Channel B apparent
load condition is indicated by the VAR_NOLOADB bit (Bit 7) energy no-load condition is indicated by the VA_NOLOADB
in the IRQSTATB register (Address 0x230 and Address 0x330). bit (Bit 8) in the IRQSTATB register (Address 0x230 and
Current Channel A and Current Channel B are independent Address 0x330).
and, therefore, a no-load condition on Current Channel A Current Channel A and Current Channel B are independent
affects only the energy accumulation, CF output, and reverse and, therefore, a no-load condition on Current Channel A
power of Current Channel A, and vice versa. affects only the energy accumulation and CF output of Current
The reactive energy no-load feature is enabled by default and Channel A, and vice versa.
can be disabled by setting Bit 1 in the DISNOLOAD register The apparent energy no-load feature is enabled by default and
(Address 0x001) to 1. can be disabled by setting Bit 2 in the DISNOLOAD register
Reactive Energy No-Load Interrupt (Address 0x001) to 1.
Two interrupts are associated with the reactive energy no-load
feature: one for Current Channel A (phase) and one for Current
Channel B (neutral). If enabled, these interrupts are triggered
when the reactive energy falls below the programmed threshold.
The Current Channel A reactive energy no-load interrupt can be
enabled by setting the VAR_NOLOADA bit (Bit 7) in the IRQENA
register (Address 0x22C and Address 0x32C). When this bit is set,
a reactive energy no-load event on Current Channel A causes
the IRQ pin (Pin 22) to fall to 0 (see the Primary Interrupts
(Voltage Channel and Current Channel A) section).

Rev. C | Page 41 of 72
ADE7953 Data Sheet
Apparent Energy No-Load Interrupt The Current Channel B apparent energy no-load interrupt
Two interrupts are associated with the apparent energy no-load can be enabled by setting the VA_NOLOADB bit (Bit 8) in the
feature: one for Current Channel A (phase) and one for Current IRQBENB register (Address 0x22F and Address 0x32F). When
Channel B (neutral). If enabled, these interrupts are triggered when this bit is set, an apparent energy no-load event on Current
the apparent energy falls below the programmed threshold. Channel B triggers the IRQ alternative output (see the Current
Channel B Interrupts section).
The Current Channel A apparent energy no-load interrupt can be
enabled by setting the VA_NOLOADA bit (Bit 8) in the IRQENA Apparent Energy No-Load Status Bits
register (Address 0x22C and Address 0x32C). When this bit is set, In addition to the apparent energy no-load interrupt, the ADE7953
an apparent energy no-load event on Current Channel A causes includes two unlatched status bits that continually monitor the
the IRQ pin (Pin 22) to fall to 0 (see the Primary Interrupts no-load status of Current Channel A and Current Channel B.
(Voltage Channel and Current Channel A) section). The VANLOAD_A and VANLOAD_B bits are located in the
ACCMODE register (Address 0x201 and Address 0x301). These
bits differ from the interrupt status bits in that they are unlatched
and can, therefore, be used to drive an LED.

Rev. C | Page 42 of 72
Data Sheet ADE7953

ZERO-CROSSING DETECTION
The ADE7953 includes a zero-crossing (ZX) detection feature As shown in Figure 62, the ZX output pin goes high on the
on all three input channels. Zero-crossing detection allows positive-going edge of the voltage channel zero crossing and
measurements to be synchronized to the frequency of the low on the negative-going edge of the zero crossing. A delay
incoming waveforms. of approximately 2.2 ms should be expected on this pin due to
Zero-crossing detection is performed at the output of LPF1 to the time delay of LPF1.
ensure that no harmonics or distortion affect the accuracy of the Current Channel Zero Crossing
zero-crossing measurement. LPF1 is a single-pole filter with a The current channel zero-crossing indicator is output on Pin 21
−3 dB cutoff of 80 Hz and is clocked at 223 kHz. The phase shift (ZX_I) by default. The ZX_I pin operates in a similar way to the
of this filter therefore results in a time delay of approximately ZX pin (see Figure 62). The ZX_I pin goes high on the positive-
2.2 ms (39.6°) at 50 Hz. To assure good resolution of the ZX going edge of the current channel zero crossing and low on the
detection, LPF1 cannot be disabled. Figure 61 shows how the negative-going edge of the current channel zero crossing. By
zero-crossing signal is detected. default, the ZX_I pin is triggered based on Current Channel A.
DSP The ZX_I pin can be configured to trigger based on Current
REFERENCE
GAIN[23:0] HPFEN BIT Channel B by setting the ZX_I bit (Bit 11) of the CONFIG
IA, IB,
OR V ZX register (Address 0x102) to 1.
DETECTION
PGA ADC
HPF LPF1 ZERO-CROSSING INTERRUPTS
Three interrupts are associated with zero-crossing detection, one
39.6° OR 2.2ms @ 50Hz for each input channel: Current Channel A, Current Channel B,
and the voltage channel. The zero-crossing condition occurs
ZX
when either a positive or a negative zero-crossing transition
0V
ZX ZX ZX takes place. If this transition occurs on the voltage channel, the
09320-127

IA, IB, OR V LPF1 OUTPUT

ZXV bit (Bit 15) of the IRQSTATA register (Address 0x22D and
Address 0x32D) is set to 1. If this transition occurs on Current
Figure 61. Zero-Crossing Detection
Channel A, the ZXIA bit (Bit 12) of the IRQSTATA register is
The error in the ZX detection is 0.08° for 50 Hz systems and set to 1. If this transition occurs on Current Channel B, the
0.09° for 60 Hz systems. The zero-crossing information is ZXIB bit (Bit 12) of the IRQSTATB register (Address 0x230 and
available on both an output pin or via an interrupt. Address 0x330) is set to 1. Figure 63 shows the operation of the
voltage channel zero-crossing interrupt.
ZERO-CROSSING OUTPUT PINS
By default, the voltage and current channel ZX information V
is configured to be output on Pin 1 (ZX) and Pin 21 (ZX_I), ZXV (BIT 15) OF
IRQSTATA REGISTER
respectively. These dedicated output pins provide an unlatched
ZX indicator (see the Alternative Output Functions section).
Voltage Channel Zero Crossing
The voltage channel zero-crossing indicator is output on Pin 1
(ZX) by default. Figure 62 shows the operation of the ZX output.
09320-032
V

2.2ms @ 50Hz Figure 63. Zero-Crossing Interrupt

As shown by the dotted line in Figure 63, the ADE7953 can be

configured to trigger a zero-crossing event on only the positive-
ZX
going or the negative-going zero crossing. The ZX_EDGE bits
(Bits[13:12]) of the CONFIG register (Address 0x102) set the
edge that triggers the zero-crossing event. These bits default to
00 (the zero-crossing event is triggered on both the positive-
going and negative-going edges). Changing the ZX_EDGE bits
09320-131

affects the zero-crossing event on all three channels. Note that

Figure 62. Voltage Channel ZX Output changing the ZX_EDGE bits affects only the ZX status bits and
interrupts; the function of the ZX pin (Pin 1) and the ZX_I pin
(Pin 21) is not affected.

Rev. C | Page 43 of 72
ADE7953 Data Sheet
A zero-crossing event on any of the three input channels can be ZXTOUT
ADDRESS 0x100
configured to trigger an external interrupt. All zero-crossing
external interrupts are disabled by default. The voltage channel
zero-crossing interrupt is enabled by setting the ZXV bit (Bit 15)
in the IRQENA register (Address 0x22C and Address 0x32C). If
this bit is set, a voltage channel zero-crossing event causes the IRQ
pin to go low. The Current Channel A zero-crossing interrupt is
INPUT
enabled by setting the ZXIA bit (Bit 12) in the IRQENA register SIGNAL
(Address 0x22C and Address 0x32C). If this bit is set, a Current
Channel A zero-crossing event causes the IRQ pin to go low. The

09320-033
Current Channel B zero-crossing interrupt is enabled by setting
ZXTO_x
the ZXIB bit (Bit 12) in the IRQENB register (Address 0x22F
Figure 64. Zero-Crossing Timeout
and Address 0x32F). If this bit is set, a Current Channel B zero-
crossing event causes the IRQ pin to go low (see the ADE7953 Three interrupts are associated with the zero-crossing timeout
Interrupts section). feature. If enabled, a zero-crossing timeout event causes the
external IRQ pin to go low. The interrupt associated with the
ZERO-CROSSING TIMEOUT
voltage channel zero-crossing timeout can be enabled by setting
The ADE7953 includes a zero-crossing timeout feature that is the ZXTO bit (Bit 14) of the IRQENA register (Address 0x22C
designed to detect when no zero crossings are obtained over a and Address 0x32C). The Current Channel A interrupt can be
programmable time period. This feature is available on both enabled by setting the ZXTO_IA bit (Bit 11) of the IRQENA
current channels and the voltage channel and can be used to register (Address 0x22C and Address 0x32C), and the Current
detect when the input signal has dropped out. The duration of Channel B interrupt can be enabled by setting the ZXTO_IB bit
the zero-crossing timeout is programmed in the 16-bit ZXTOUT (Bit 11) of the IRQENB register (Address 0x22F and Address
register (Address 0x100). The same timeout duration is used for 0x32F). All three interrupts are disabled by default (see the
all three channels. The value in the ZXTOUT register is decre- ADE7953 Interrupts section).
mented by 1 LSB every 14 kHz (CLKIN/256). If a zero crossing
is obtained, the ZXTOUT register is reloaded. If the ZXTOUT
ZERO-CROSSING THRESHOLD
register reaches 0, a zero-crossing timeout event is issued. The To prevent spurious zero crossings when a very small input is
ZXTOUT register has a resolution of 0.07 ms (1/14 kHz); there- present, an internal threshold is included on all channels of the
fore, the maximum programmable timeout period is 4.58 seconds. ADE7953. This fixed threshold is set to a range of 1250:1 of the
input full scale. If any input signal falls below this level, no zero-
As shown in Figure 64, a zero-crossing event causes one of the
crossing signals are produced by the ADE7953 because they can
zero-crossing timeout bits—ZXTO, ZXTO_IA, or ZXTO_IB—
be assumed to be noise. This threshold affects both the external
to be set to 1. The ZXTO and ZXTO_IA bits are located in the
zero-crossing pins, ZX (Pin 1) and ZX_I (Pin 21), as well as the
IRQSTATA register (Address 0x22D and Address 0x32D) and
zero-crossing interrupt function. At inputs of lower than 1250:1
are set when a zero-crossing timeout event occurs on the voltage
of the full scale, the zero-crossing timeout signal continues to
channel or on Current Channel A, respectively. The ZXTO_IB
function and issues an event according to the time duration
bit is located in the IRQSTATB register (Address 0x230 and
programmed in the ZXTOUT register (Address 0x100).
Address 0x330) and is set when a zero-crossing timeout event
occurs on Current Channel B.

Rev. C | Page 44 of 72
Data Sheet ADE7953

VOLTAGE SAG DETECTION

The ADE7953 includes a sag detection feature that warns the If the SAGCYC value is modified after the feature is enabled,
user when the absolute value of the line voltage falls below the the new SAGCYC period is effective immediately. Therefore, it
programmable threshold for a programmable number of line is possible for a sag event to be caused by a combination of sag
cycles. This feature can provide an early warning signal that the cycle periods. To prevent any overlap, the SAGLVL register
line voltage is dropping out. The voltage sag feature is controlled should be reset to 0 to effectively disable the feature before
by two registers: SAGCYC (Address 0x000) and SAGLVL the new cycle value is written to the SAGCYC register.
(Address 0x200 and Address 0x300). These registers control
SETTING THE SAGLVL REGISTER
the sag period and the sag voltage threshold, respectively.
The 24-bit/32-bit SAGLVL register contains the amplitude that
Sag detection is disabled by default and can be enabled by
the voltage channel must fall below before a sag event occurs.
writing a nonzero value to both the SAGCYC and SAGLVL Each LSB of this register maps exactly to the voltage channel
registers. If either register is set to 0, the sag feature is disabled. peak register; therefore, the amplitude can be set based on the
If a voltage sag condition occurs, the sag bit (Bit 19) in the peak reading of the voltage channel. To set the SAGLVL register,
IRQSTATA register (Address 0x22D and Address 0x32D) and nominal voltage should be applied and a reading taken from the
in the RSTIRQSTATA register (Address 0x22E and Address RSTVPEAK register (Address 0x227 and Address 0x327) to reset
0x32E) is set to 1.
the peak level reading. After a wait period of a few line cycles,
SETTING THE SAGCYC REGISTER the VPEAK register (Address 0x226 and Address 0x326) should
The 8-bit, unsigned SAGCYC register contains the program- be read to determine the voltage input. This reading should
mable sag period. The sag period is the number of half line then be scaled to the amplitude required for sag detection.
cycles below which the voltage channel must remain before For example, if a sag threshold of 80% of the nominal voltage is
a sag condition occurs. Each LSB of the SAGCYC register required, the peak reading should be taken and a value of 80%
corresponds to one half line cycle period. The SAGCYC of this reading should be written to the SAGLVL register. This
register holds a maximum value of 255. method ensures that an accurate SAGLVL value is obtained for
At 50 Hz, the maximum sag cycle time is 2.55 seconds. the particular design.

 1 ÷ 2  × 255 = 2.55 sec

VOLTAGE SAG INTERRUPT
  The ADE7953 includes an interrupt that is associated with
 50 
the voltage sag detection feature. If this interrupt is enabled,
At 60 Hz, the maximum sag cycle time is 2.125 seconds.
a voltage sag event causes the external IRQ pin to go low. This
 1 ÷ 2  × 255 = 2.125 sec interrupt is disabled by default and can be enabled by setting
 
 60  the sag bit (Bit 19) in the IRQENA register (Address 0x22C
and Address 0x32C). See the ADE7953 Interrupts section.

Rev. C | Page 45 of 72
ADE7953 Data Sheet

PEAK DETECTION
The ADE7953 includes a peak detection feature on both These three registers are updated every time that the absolute
Current Channel A (phase) and Current Channel B (neutral) value of the waveform exceeds the current value stored in the
and on the voltage channel. This feature continuously records IAPEAK, IBPEAK, and VPEAK registers. No time period is
the maximum value of the voltage and current waveforms. associated with this measurement.
Peak detection can be used with overvoltage and overcurrent Three additional registers contain the same peak information,
detection to provide a complete swell detection function (see but cause the corresponding peak measurements to be reset
the Overcurrent and Overvoltage Detection section). after they are read. The three read-with-reset peak registers are
Peak detection is an instantaneous measurement taken from RSTIAPEAK (Address 0x229 and Address 0x329), RSTIBPEAK
the absolute value of the current and voltage ADC output (Address 0x22B and Address 0x32B), and RSTVPEAK (Address
waveforms and stored in three 24-bit/32-bit registers. The 0x227 and Address 0x327). Reading these registers clears the
three registers that record the peak values on Current Channel contents of the corresponding xPEAK register.
A, Current Channel B, and the voltage channel, respectively,
are IAPEAK (Address 0x228 and Address 0x328), IBPEAK
(Address 0x22A and Address 0x32A), and VPEAK (Address
0x226 and Address 0x326).

Rev. C | Page 46 of 72
Data Sheet ADE7953

INDICATION OF POWER DIRECTION

The ADE7953 includes sign indication on the active and reactive This pulse has a 50% duty cycle. Similar to normal mode, this
energy measurements. Sign indication allows positive and nega- mode is also unlatched, and the REVP output returns high when
tive energy to be identified and billed separately if required. It the reverse polarity is no longer true. To enable the REVP pulse
also helps detect a miswiring condition. This feature is available mode, the REVP_PULSE bit in the CONFIG register (Address
on both Current Channel A and Current Channel B. Power 0x102) should be set to 1.
direction information is available on both a dedicated output
The REVP output pin is disabled in the corresponding no-load
pin (REVP) and via a set of internal registers and interrupts (see
condition. For example, if the reverse polarity information for
the Reverse Power section and the Sign Indication section).
Current Channel A active power is present on the REVP pin and
REVERSE POWER the active energy on Current Channel A is in the no-load condi-
The REVP pin (Pin 20) on the ADE7953 provides a reverse tion, the REVP output is disabled and held in its current state.
power indicator. This pin can be configured to provide polarity SIGN INDICATION
information about the active or reactive power on Current
The ADE7953 includes four sign indication bits that indicate the
Channel A or Current Channel B. The REVP output is high by
polarity of the active power on Current Channel A (APSIGN_A),
default and goes low if the angle between the voltage and current
the active power on Current Channel B (APSIGN_B), the
input is greater than 90°. REVP is unlatched and, therefore,
reactive power on Current Channel A (VARSIGN_A), and the
returns high when the reverse power condition is no longer
reactive power on Current Channel B (VARSIGN_B). These bits
true. Changes to the REVP output pin occur synchronously are located in the ACCMODE register (Address 0x201 and
to the falling edge of the CF1 pin by default (see Figure 65). Address 0x301). All four bits are unlatched and read only. A low
The measurement and channel indicated by the REVP pin are reading (0) on any of these bits indicates that the corresponding
selected by the configuration of the CF output. By default, the power reading is positive; a high reading (1) indicates that the
REVP pin is configured to output synchronous to CF1 and corresponding power reading is negative. These bits are enabled
represents the measurement selected on CF1 using the CF1SEL by default and are disabled in the corresponding no-load
bits in the CFMODE register (Address 0x107). By default, this condition.
measurement is the active power on Current Channel A. If the In addition to the sign indication bits, the ADE7953 also includes
CF1SEL bits are set to 0x0001, the REVP pin indicates the polarity four sign indication interrupts. If enabled, these interrupts cause
of the reactive power on Current Channel A. The REVP indicator the IRQ pin to go low when the polarity of the power changes.
can be configured to output based on CF2 by setting the REVP_CF The interrupts are triggered on both positive-to-negative and
bit in the CONFIG register (Address 0x102). In this configura- negative-to-positive polarity changes. These interrupts are dis-
tion, the CF2SEL bits in the CFMODE register determine the abled by default and can be enabled by setting the APSIGN_A
measurement represented on the REVP output. If the selected and VARSIGN_A bits in the IRQENA register (Address 0x22C
CF pin is configured to output another measurement, such as and Address 0x32C), and the APSIGN_B and VARSIGN_B bits
apparent power or IRMS, the REVP output is disabled. in the IRQENB register (Address 0x22F and Address 0x32F).
See the ADE7953 Interrupts section.
To improve the visibility of a reverse polarity condition if an
LED light is used, a 1 Hz pulse mode is available on the REVP Note that in absolute or positive-only accumulation mode, these
pin. In this mode, the REVP output pin is low by default and bits are fixed at 0. See the Active Energy Accumulation Modes
outputs a 1 Hz pulse if the reverse polarity condition is true. section and the Reactive Energy Accumulation Modes section.

REVP
ENTER LOW EXIT
REVERSE REVERSE REVP
CONDITION CONDITION HIGH

CF1

CURRENT AND
VOLTAGE
INPUTS
09320-034

REVP

Figure 65. REVP Output

Rev. C | Page 47 of 72
ADE7953 Data Sheet

OVERCURRENT AND OVERVOLTAGE DETECTION

The ADE7953 provides an overcurrent and overvoltage feature As shown in Figure 67, if an overcurrent condition is detected
that detects whether the absolute value of the current or voltage on Current Channel A, the OIA bit (Bit 13) of the IRQSTATA
waveform exceeds a programmable threshold. This feature uses register is set to 1. This bit can be cleared by reading from the
the instantaneous voltage and current signals. The two registers RSTIRQSTATA register. If an overcurrent condition is detected
associated with this feature, OVLVL (Address 0x224 and on Current Channel B, the OIB bit (Bit 13) of the IRQSTATB
Address 0x324) and OILVL (Address 0x225 and Address 0x325), register (Address 0x230 and Address 0x330) is set to 1. This bit
are used to set the voltage and current channel thresholds, respec- can be cleared by reading from the RSTIRQSTATB register
tively. The OILVL threshold register determines the threshold (Address 0x231 and Address 0x331).
for both the Current Channel A and Current Channel B over-
current features. The same threshold must therefore be used for SETTING THE OVLVL AND OILVL REGISTERS
both Current Channel A and Current Channel B. The default The 24-bit/32-bit unsigned OVLVL and OILVL registers map
value of the OVLVL and OILVL registers is 0xFFFFFF, which directly to the VPEAK (Address 0x226 and Address 0x326)
effectively disables the feature. Figure 66 shows the operation of and IAPEAK (Address 0x228 and Address 0x328) registers,
the overvoltage detection feature. respectively (see the Peak Detection section). Note that after
V gain calibration, Current Channel A and Current Channel B are
OVLVL matched and, therefore, the IAPEAK and IBPEAK registers are
matched with common inputs. The settings of the OVLVL and
OILVL registers should be based on the VPEAK and IAPEAK
readings with full-scale inputs.
To set the OVLVL register, the maximum voltage input should
OV RESET
be applied and a reading taken from the RSTVPEAK register
LOW WHEN (Address 0x227 and Address 0x327). This resets the voltage peak
RSTIRQSTATA
reading. After a wait period of a few line cycles, the VPEAK
09320-035

REGISTER
OV (BIT 16) OF IS READ
IRQSTATA REGISTER register (Address 0x226 and Address 0x326) should be read to
Figure 66. Overvoltage Detection determine the voltage peak. This reading should then be scaled
As shown in Figure 66, if the ADE7953 detects an overvoltage to the amplitude required for overvoltage detection. For example,
condition, the OV bit (Bit 16) of the IRQSTATA register if an overvoltage threshold of 120% of the maximum voltage is
(Address 0x22D and Address 0x32D) is set to 1. This bit can be required, the peak reading should be multiplied by 1.2 and the
cleared by reading the RSTIRQSTATA register (Address 0x22E resulting value written to the OVLVL register. This method ensures
and Address 0x32E). The overcurrent detection feature works in that an accurate threshold is set for each individual design.
a similar manner (see Figure 67). OVERVOLTAGE AND OVERCURRENT INTERRUPTS
IA
Three interrupts are associated with the overvoltage and
OILVL
overcurrent features. The first interrupt is associated with the
overvoltage feature; it is enabled by setting the OV bit (Bit 16)
of the IRQENA register (Address 0x22C and Address 0x32C).
When this bit is set, an overvoltage condition causes the
external IRQ pin to be pulled low.
OIA RESET LOW A second interrupt is associated with the overcurrent detection
WHEN RSTIRQSTATA

OIA (BIT 13) OF

REGISTER IS READ feature on Current Channel A. This interrupt is enabled by
IRQSTATA setting the OIA bit (Bit 13) of the IRQENA register. When this
REGISTER
bit is set, an overcurrent condition on Current Channel A
IB causes the external IRQ pin to be pulled low.
OILVL
The third interrupt is associated with the overcurrent detection
feature on Current Channel B. This interrupt is enabled by setting
the OIB bit (Bit 13) of the IRQENB register (Address 0x22F and
Address 0x32F). When this bit is set, an overcurrent condition
on Current Channel B causes the IRQ alternative output to be
OIB RESET LOW triggered, if the alternative output is enabled (see the Current
OIB (BIT 13) OF WHEN RSTIRQSTATB
09320-036

IRQSTATB REGISTER IS READ Channel B Interrupts section).

REGISTER

Figure 67. Overcurrent Detection

Rev. C | Page 48 of 72
Data Sheet ADE7953

ALTERNATIVE OUTPUT FUNCTIONS

The ADE7953 includes three output pins that are configured by Table 8. Alternative Outputs
default to output power quality information. Function See This Section
• Pin 1 (ZX) provides a voltage channel zero-crossing signal, Zero-crossing detection Voltage Channel Zero Crossing
as described in the Voltage Channel Zero Crossing section. (voltage channel)
• Pin 21 (ZX_I) provides a current channel zero-crossing Zero-crossing detection Current Channel Zero Crossing
(current channels)
signal, as described in the Current Channel Zero Crossing
section. Reverse power indication Reverse Power
• Pin 20 (REVP) provides polarity information, as described Voltage sag detection Voltage Sag Detection
Active energy no-load Active Energy No-Load
in the Reverse Power section.
detection (Current Channel A) Detection
To provide flexibility and to accommodate a variety of design Active energy no-load Active Energy No-Load
requirements, the ADE7953 can be configured to output a detection (Current Channel B) Detection
variety of alternative power quality signals on any of these Reactive energy no-load Reactive Energy No-Load
detection (Current Channel A) Detection
three outputs. Alternative functions are configured using the
Reactive energy no-load Reactive Energy No-Load
ALT_OUTPUT register (Address 0x110).
detection (Current Channel B) Detection
Table 8 summarizes the functions that can be output on Pin 1, Waveform sampling, data ready Instantaneous Powers and
Pin 21, and Pin 20. Note that the default functions of ZX, ZX_I, Waveform Sampling
and REVP can be configured to output on any one of Pin 1, Interrupt output (Current Current Channel B Interrupts
Pin 21, or Pin 20. Channel B)

As described in Table 8, the description of each function can be

found in the corresponding section of this data sheet. If an alter-
native output function is enabled on Pin 1, Pin 21, or Pin 20, the
function can be configured and will be performed as described
in the corresponding section. The alternative function will, how-
ever, appear as an unlatched output on Pin 1, Pin 21, or Pin 20.
To enable an alternative function, the ZX_ALT, ZXI_ALT, and
REVP_ALT bits in the ALT_OUTPUT register must be set. The
interrupt enable associated with the alternative output does not
need to be enabled in order for it to be present on Pin 1, Pin 21,
or Pin 20. Enabling an alternative output does not affect the
primary function of the feature.

Rev. C | Page 49 of 72
ADE7953 Data Sheet

ADE7953 INTERRUPTS
The ADE7953 interrupts are separated into two groups. The register, but when the RSTIRQSTATA register is accessed, a read-
first group of interrupts is associated with the voltage channel with-reset command is executed, clearing the status bits. After
and Current Channel A. The second group of interrupts is completion of a read from this register, all status bits are cleared
associated with Current Channel B. See Table 22 and Table 24 to 0 and the IRQ pin returns to Logic 1.
for a list of the interrupts.
CURRENT CHANNEL B INTERRUPTS
All interrupts are disabled by default with the exception of the
The Current Channel B interrupts are events that occur on
RESET interrupt that is located within the group of primary
Current Channel B. Like the primary group of interrupts,
interrupts. This interrupt is enabled by default and signals the
Current Channel B interrupts are handled by a group of three
end of a software or hardware reset. On power-up, this interrupt
registers: the enable register, IRQENB (Address 0x22F and
is triggered to signal that the ADE7953 is ready to receive
Address 0x32F), the status register, IRQSTATB (Address 0x230
communication from the microcontroller. This interrupt should
and Address 0x330), and the reset status register, RSTIRQSTATB
be serviced as described in the Primary Interrupts (Voltage
(Address 0x231 and Address 0x331). The bits in these registers
Channel and Current Channel A) section prior to configuring
are described in Table 24 and Table 25.
the ADE7953.
When an interrupt event occurs, the corresponding bit in
PRIMARY INTERRUPTS (VOLTAGE CHANNEL AND the IRQSTATB register is set to 1. The Current Channel B
CURRENT CHANNEL A) interrupts do not have a dedicated output pin. This function
The primary interrupts are events that occur on the voltage can be configured as an alternative output on Pin 1 (ZX),
channel and Current Channel A. These interrupts are handled Pin 21 (ZX_I), or Pin 20 (REVP) (see the Alternative Output
by a group of three registers: the enable register, IRQENA Functions section). If an output is enabled for interrupt events
(Address 0x22C and Address 0x32C), the status register, on Current Channel B and the interrupt enable bit, located in
IRQSTATA (Address 0x22D and Address 0x32D), and the the IRQENB register, is set to 1, Pin 1, Pin 21, or Pin 20 is
reset status register, RSTIRQSTATA (Address 0x22E and pulled low if an interrupt event occurs on Current Channel B.
Address 0x32E). The bits in these registers are described in The status bits located in the IRQSTATB register are set when
Table 22 and Table 23. an interrupt event occurs, regardless of whether an external
When an interrupt event occurs, the corresponding bit in the interrupt output is enabled.
IRQSTATA register is set to 1. If the enable bit for this interrupt, All interrupts are latched and require servicing to clear. To
located in the IRQENA register, is set to 1, the external IRQ pin service the interrupt, the status bits must be cleared using the
is pulled to Logic 0. The status bits located in the IRQSTATA RSTIRQSTATB register (Address 0x231 and Address 0x331).
register are set when an interrupt event occurs, regardless of The RSTIRQSTATB register contains the same interrupt status
whether the external interrupt is enabled. bits as the IRQSTATB register, but when the RSTIRQSTATB
All interrupts are latched and require servicing to clear. To register is accessed, a read-with-reset command is executed,
service the interrupt and return the IRQ pin to Logic 1, the clearing the status bits. After completion of a read from this
status bits must be cleared using the RSTIRQSTATA register register, all status bits are cleared to 0 and the appropriate
(Address 0x22E and Address 0x32E). The RSTIRQSTATA output pin (if enabled) returns to Logic 1.
register contains the same interrupt status bits as the IRQSTATA

Rev. C | Page 50 of 72
Data Sheet ADE7953

COMMUNICATING WITH THE ADE7953

All ADE7953 features can be accessed via a group of on-chip Therefore, although Pin 25 (SCLK) and Pin 28 (CS) are not
registers. For a detailed list of all the registers, see the ADE7953 required if communicating via I2C or UART, these pins should
Registers section. Three different communication interfaces can be configured in hardware as shown in Table 9 to ensure the
be used to access the on-chip registers. functionality of the autodetection system.
• 4-pin SPI interface LOCKING THE COMMUNICATION INTERFACE
• 2-pin bidirectional I2C interface After the selected communication interface is established, the
• 2-pin UART interface interface should be locked to prevent the communication
All three communication options use the same group of pins method from inadvertently changing. The ADE7953 can be
and, therefore, only one method of communication should be configured to lock automatically after the first successful
used in each design. communication.

COMMUNICATION AUTODETECTION The automatic lock feature is disabled by default and is enabled
by clearing the COMM_LOCK bit (Bit 15) in the CONFIG
The ADE7953 contains a detection system that automatically register (Address 0x102). To successfully establish and lock the
detects which of the three communication interfaces is being communication interface, a write should be issued shortly after
used. This feature allows communication to be quickly estab- power-up to the CONFIG register, clearing the COMM_LOCK
lished with minimal initialization. Autodetection works by bit and thus locking the communication interface. When the
monitoring the status of the four communication pins and communication interface is locked to a specific method (that is,
automatically selecting the communication interface that SPI, I2C, or UART), the communication method cannot be
matches the configuration (see Table 9). changed without resetting the ADE7953.
• The CS pin (Pin 28) is used to determine whether the Note that if using the SPI communication interface to lock
communication method is SPI. The pin must be low the communication mode, the CS pin must be low for a
during the SPI communication for this interface method. minimum of 1.2 µs after the last SCLK. This delay is required
The CS pin is active low and will automatically lock onto only when writing to the COMM_LOCK bit (see the SPI
SPI communication as a result. Interface Timing section).
• The SCLK pin (Pin 25) is used to determine whether the
communication method is I2C or UART. If this pin is held
high, the communication interface is set to I2C; if it is held
low, the communication interface is set to UART.

Table 9. Communication Autodetection

Communication Interface Pin 28 (CS) Pin 25 (SCLK) Pin 27 (MOSI/SCL/Rx) Pin 26 (MISO/SDA/Tx)
SPI 0 Don’t care MOSI MISO
I2C 1 1 SCL SDA
UART 1 0 Rx Tx

Rev. C | Page 51 of 72
ADE7953 Data Sheet
SPI INTERFACE The most significant bit of this byte should be set to 1 for a read
The serial peripheral interface (SPI) uses all four communica- operation and to 0 for a write operation. When the third byte
tion pins: CS, SCLK, MOSI, and MISO. The SPI communication transmission is complete, the register data is either sent from the
operates in slave mode and, therefore, a clock must be provided ADE7953 on the MISO pin (in the case of a read) or is written
on the SCLK pin (MOSI is an input, and MISO is an output). to the ADE7953 MOSI pin by the external microcontroller (in
This clock synchronizes all communications and can operate up the case of a write). All data is sent or received MSB first. The
to a maximum speed of 5 MHz. See the SPI Interface Timing length of the data transfer depends on the width of the register
section for more information about the communication timing being accessed. Registers can be 8, 16, 24, or 32 bits long.
requirements. Figure 68 and Figure 69 show the data transfer sequence for
The MOSI pin is an input to the ADE7953; data is shifted in on an SPI read and an SPI write, respectively. As shown in these
the falling edge of SCLK to be sampled by the ADE7953 on the figures, the CS (chip select) input must be driven low to initialize
rising edge. The MISO pin is an output from the ADE7953; data the communication and driven high at the end of the communi-
is shifted out on the falling edge of SCLK and should be sampled cation. Bringing the CS input high before the completion of a
by the external microcontroller on the rising edge. data transfer ends the communication. In this way, the CS input
performs a reset function on the SPI communication. The CS
The SPI communication packet consists of two initial bytes input allows communication with multiple devices on the same
that contain the address of the register that is to be read from microcontroller SPI port.
or written to. This address should be transmitted MSB first. The
third byte of the communication determines whether a read or
a write is being issued.

CS

SCLK

15 14 1 0

MOSI REGISTER ADDRESS

1 0 0 0 0 0 0 0
31 30 1 0 09320-062

MISO REGISTER VALUE

Figure 68. SPI Read

CS

SCLK

15 14 1 0 31 30 1 0
09320-063

MOSI REGISTER ADDRESS REGISTER VALUE

0 0 0 0 0 0 0 0

Figure 69. SPI Write

Rev. C | Page 52 of 72
Data Sheet ADE7953
I2C INTERFACE I 2C Write Operations
The ADE7953 supports a fully licensed I2C interface. The I2C A write operation on the ADE7953 is initiated when the master
interface operates as a slave and uses two shared pins: SDA and issues a start condition, which consists of the slave address and
SCL. The SDA pin is a bidirectional input/output pin, and the the read/write bit. The start condition is followed by the 16-bit
SCL pin is the serial clock. Both pins are shared with the SPI address of the target register. After each byte is received, the
and UART interfaces. The I2C interface operates at a maximum ADE7953 issues an acknowledge (ACK) to the master.
serial clock frequency of 400 kHz. As soon as the 16-bit address communication is complete, the
The two pins used for data transfer—SDA and SCL—are master sends the register data, MSB first. The length of this data
configured in a wire-AND format that allows arbitration in can be 8, 16, 24, or 32 bits long. After each byte of register data
a multimaster system. Note that the ADE7953 requires a is received, the ADE7953 slave issues an acknowledge (ACK).
minimum delay of 100 ns between the SCL and SDA edges, When transmission of the final byte is complete, the master
see tHD;DAT in Table 3. issues a stop condition, and the bus returns to the idle condition.
The I2C write operation is shown in Figure 70.
Communication via the I2C interface is initiated by the master
device generating a start condition. This consists of the master
transmitting a single byte containing the address of the slave
device and the nature of the operation (read or write).
The address of the ADE7953 is 0111000X. Bit 7 in the address
byte indicates whether a read or a write is required: 0 indicates
a write, and 1 indicates a read. The communication continues as
described in the following sections until the master issues a stop
condition and the bus returns to the idle condition.
START

STOP
15 8 7 0 23 16 15 8 7 0 7 0
S 0 1 1 1 0 0 0 0 P
READ/WRITE

A MSB OF REGISTER ADDRESS A LSB OF REGISTER ADDRESS A A A A A

SLAVE ADDRESS C C C BYTE 3 (MSB) OF REGISTER C BYTE 2 OF REGISTER C BYTE 1 OF REGISTER C BYTE 0 (LSB) OF REGISTER C
K K K K K K K

09320-059
ACK GENERATED BY
ADE7953

Figure 70. I2C Write

Rev. C | Page 53 of 72
ADE7953 Data Sheet
I2C Read Operations The second stage of the read operation begins with the master
2
The I C read operation is performed in two stages. The first generating a new start condition. This start condition consists of
stage sets the pointer to the address of the register to be the same slave address but with the LSB set to 1 to signify that a
accessed. The second stage reads the contents of the register. read is being issued. After this byte is received, the ADE7953
issues an acknowledge (ACK). The ADE7953 then sends the
As shown in Figure 71, the first stage is initiated when the
register contents to the master, which acknowledges the reception
master issues a start condition, which consists of the slave
of each byte. All bytes are sent MSB first. The register contents
address and the read/write bit. Because this first step sets up
can be 8, 16, 24, or 32 bits long. After the final byte of register
the pointer to the address, the LSB of the start byte should be
data is received, the master issues a stop condition in place of
set to 0 (write). The start condition is followed by the 16-bit
the acknowledge to indicate the completion of the communication.
address of the target register. After each byte is received, the
The I2C read operation is shown in Figure 71.
ADE7953 issues an acknowledge (ACK) to the master.
START

15 8 7 0

S 0 1 1 1 0 0 0 0
READ/WRITE

A A A
SLAVE ADDRESS
C MSB OF REGISTER ADDRESS C LSB OF REGISTER ADDRESS C
K K K

ACK GENERATED BY
ADE7953

ACK GENERATED BY
MASTER
START

STOP
A A A
23 16 C 15 8 C 7 0 C 7 0
K K K
S 0 1 1 1 0 0 0 1 P
READ/WRITE

A
C BYTE 3 (MSB) BYTE 0 (LSB)
SLAVE ADDRESS K OF REGISTER BYTE 2 OF REGISTER BYTE 1 OF REGISTER OF REGISTER

09320-060
ACK GENERATED BY
ADE7953

Figure 71. I2C Read

Rev. C | Page 54 of 72
Data Sheet ADE7953
UART INTERFACE Table 10. Frames in the UART Packet
The ADE7953 provides a simple universal asynchronous Frame Function
receiver/transmitter (UART) interface that allows all the functions F1 Read/write
of the ADE7953 to be accessed using only two single-direction F2 Address MSB
pins. The UART interface allows an isolated communication F3 Address LSB
interface to be achieved using only two low cost opto-isolators. F1 determines whether the communication is a read or a write
The UART interface operates at a fixed baud rate of 4800 bps operation, and the following two frames (F2 and F3) select the
and is therefore suitable for low speed designs. register that is to be accessed. Each frame consists of eight data
The UART interface on the ADE7953 is accessed via the Tx pin bits, as shown in Figure 72. A read is issued by writing the value
(Pin 26), which transmits data from the ADE7953, and the Rx 0x35 to F1, and a write is issued by writing the value 0xCA to
pin (Pin 27), which receives data from the microcontroller. A F1. Any other value is interpreted as invalid and results in an
simple master/slave topology is implemented on the UART inter- unsuccessful communication with the ADE7953. The address
face with the ADE7953 acting as the slave. All communication bytes are sent MSB first; therefore, F2 contains the most
is initiated by the sending of a valid frame by the master (the significant portion of the address, and F3 contains the least
microcontroller) to the slave (the ADE7953). The format of the significant portion of the address. The bits within each address
frame is shown in Figure 72. frame are sent LSB first.

As shown in Figure 72, each frame consists of 10 bits. Each bit is The ADE7953 UART interface uses two timeouts, t1 and t2, to
sent at a bit rate of 4800 bps, resulting in a frame time of 2.08 ms synchronize the communication and to prevent the communi-
((1/4800) × 10). A wait period of 6 ms should be added from cation from halting. The first timeout, t1, is the frame-to-frame
when the UART communication mode is established using the delay and is fixed at 4 ms max. The second timeout, t2, is the
CS and SCLK pins to when the first frame is sent. A minimum packet-to-packet delay and is fixed at 6 ms min. These two
wait of 0.2 ms should be included between frames. All frame timeouts act as a reset for the UART function. More informa-
data is sent LSB first. tion about how the timeouts are implemented is provided in
the UART Read section and the UART Write section.
Communication via the UART interface is initiated by the
master sending a packet of three frames (see Table 10). Verification of a successful UART communication can be
achieved by implementing a write/read/verify sequence in the
microcontroller. Successful communications are also recorded
in the LAST_ADD, LAST_RWDATA, and LAST_OP registers,
as described in the Communication Verification section.

t2

SCLK

CS

t1
START

START
STOP

Rx
D0

D1

D2

D3

D4

D5

D6

D7

D0

FRAME
09320-141

t1 = FRAME DELAY: 0.2ms (MIN), 4ms (MAX)

t2 = PACKET DELAY: 6ms (MIN)

Figure 72. UART Frame

Rev. C | Page 55 of 72
ADE7953 Data Sheet
UART Read UART Write
A read from the ADE7953 via the UART interface is initiated A write to the ADE7953 via the UART interface is initiated by
by the master sending a packet of three frames. If the first frame the master sending a packet of three frames. If the first frame
has the value 0x35, a read is being issued. The second and third has the value 0xCA, a write is being issued. The second and
frames contain the address of the register being accessed. When third frames contain the address of the register being accessed.
the ADE7953 receives a legal packet, it decodes the command The next two frames contain the data to be written. When the
(see Figure 73). ADE7953 receives a legal packet, it decodes the command as
The frame time is 2.08 ms. A frame-to-frame delay (t1) of 4 ms follows:
max provides a 50% buffer on the frame time without needlessly  If the number of frames obtained after the initial packet is
slowing the communication. When the read packet is decoded, the same as the size of the register specified by F2 and F3, the
the ADE7953 sends the data from the selected register out on the packet is legal and the corresponding register is written.
Tx pin (see F4 and F5 in Figure 73). This occurs approximately  If the number of frames does not equal the size of the
0.1 ms after the complete frame is received. This data can be 1, specified register, the command is illegal and no further
2, 3, or 4 bytes long, depending on the size of the register that is action is taken.
being accessed. The register data is sent LSB first. After the last
frame of register data is sent from the ADE7953, a packet-to- After the last frame of data is received on the Rx pin, a wait
packet delay (t2) of 6 ms min is required before any incoming period of t2 is required before any incoming data on the Rx pin
data on the Rx pin is accepted. This packet-to-packet timeout is treated as a new packet. This operation is shown in Figure 74.
ensures that no overlap is possible.

t1 t1 t1

F1 F2 F3 F1 F2
Rx
READ/ ADDRESS ADDRESS READ/ ADDRESS
WRITE WRITE
MSB LSB MSB

t1 t1

F4 F5
Tx
DATA DATA

09320-142
LSB MSB
t2

Figure 73. UART Read

t1 t1 t1 t1 t1

F1 F2 F3 F4 F5 F1 F2
Rx
READ/ ADDRESS ADDRESS DATA DATA READ/ ADDRESS
WRITE WRITE
MSB LSB LSB MSB MSB

t2
Tx
09320-143

Figure 74. UART Write

Rev. C | Page 56 of 72
Data Sheet ADE7953

COMMUNICATION VERIFICATION AND SECURITY

The ADE7953 includes three security measures to increase COMMUNICATION VERIFICATION
communication robustness and to help prevent inadvertent The ADE7953 includes a set of three registers that allow any
modifications to its internal registers. The write protection, communication via SPI, I2C, or UART to be verified. The
communication verification, and checksum features can be LAST_OP (Address 0x0FD), LAST_ADD (Address 0x1FE),
used together to help increase the robustness and noise and LAST_RWDATA registers record the type, address, and
immunity of the meter design. data of the last successful communication, respectively. The
WRITE PROTECTION LAST_RWDATA register has four separate addresses, depending
The ADE7953 provides a simple method for protecting the on the length of the successful communication (see Table 11).
internal registers from unexpected write operations. This feature Multiple address locations are included to prevent unnecessarily
helps to prevent noise or EMC conditions from changing the long communications.
required meter configuration. The write protection feature is Table 11. Addresses of the LAST_RWDATA Registers
disabled by default to allow the meter to be configured and can Register Address Length of Read/Write
be enabled by writing to the 8-bit WRITE_PROTECT register
Address 0x0FF 8 bits
(Address 0x040). Only the three LSBs of this register are used.
Address 0x1FF 16 bits
Bit 0 controls the protection on the 8-bit registers; Bit 1 controls
Address 0x2FF 24 bits
the protection on the 16-bit registers; Bit 2 controls the protection
Address 0x3FF 32 bits
on the 24-bit/32-bit registers. All bits are set to 0 by default to
disable the protection. Setting any of these bits to 1 enables
After each successful communication with the ADE7953, the
write protection on the corresponding group of registers. When
address of the last register that was accessed is stored in the
write protection is enabled, any attempted write operation using
16-bit LAST_ADD register (Address 0x1FE). This read-only
the SPI, I2C, or UART interface is ignored. The one exception to
register stores the value until the next successful read or write
this is the WRITE_PROTECT register that can still be modified
is complete.
to disable the write protection feature. Resetting the WRITE_
PROTECT bits to 0 reinstates full access to the register banks. The LAST_OP register (Address 0x0FD) stores the type of the
The WRITE_PROTECT bits are included in the CRC check communication, that is, it indicates whether a read or a write
and set off an interrupt when CRC_ENABLE is set to 1 and the was performed. If the last operation was a write, the LAST_OP
WRITE_PROTECT bit is changed. register stores the value 0xCA. If the last operation was a read,
the LAST_OP register stores the value 0x35.
The LAST_RWDATA register stores the data that was written to
or read from the register. Unsuccessful read and write operations
are not reflected in these registers.

Rev. C | Page 57 of 72
ADE7953 Data Sheet
CHECKSUM REGISTER 1023 0
LFSR

09320-075
ARRAY OF 1024 BITS GENERATOR
The ADE7953 includes a 32-bit checksum register, CRC
(Address 0x37F), which warns the user if any of the important Figure 75. Checksum Register Calculation
configuration, control, or calibration registers are modified. The
checksum register helps to ensure that the meter configuration
is not modified from its desired state during normal operation. g0 g1 g2 g3 g31
FB
Table 12 lists the registers included in the checksum. An
b0 b1 b2 b31
additional eight internal reserved registers are also included in
LFSR
the checksum. The ADE7953 computes the cyclic redundancy

09320-076
check (CRC) based on the IEEE 802.3 standard. The contents a1023, a1022,....,a2, a1, a0

of the registers are introduced one by one into a linear feedback Figure 76. LFSR Generator Used in Checksum Register Calculation
shift register (LFSR) based generator, starting with the least
The CRC is disabled by default and can be enabled by setting
significant bit. The 32-bit result is written to the CRC register.
the CRC_ENABLE bit (Bit 8) of the CONFIG register
Figure 75 shows how the LFSR works. The registers shown in (Address 0x102). When this bit is set, the CRC is computed at
Table 12 and the eight 8-bit reserved internal registers form the a rate of 6.99 kHz. Because the CRC is disabled by default, the
bits [a1023, a1022,…, a0] used by LFSR. Bit a0 is the least significant default value is 0xFFFFFFFF. Once enabled, with all registers at
bit of the first register to enter LFSR; Bit a1023 is the most signifi- their default value, the CRC is 0x48739163.The checksum can
cant bit of the last register to enter LFSR. be used to ensure that the registers included in the checksum
are not inadvertently changed by periodically reading the value
The formulas that govern LFSR are as follows:
in the CRC register (Address 0x37F) after the meter is
bi(0) = 1, i = 0, 1, 2, …, 31, the initial state of the bits that form configured.
the CRC. Bit b0 is the least significant bit, and Bit b31 is the most
If two consecutive readings differ, it can be assumed that one
significant.bi(0) = 1, i = 0, 1, 2, …, 31, the initial state of the bits
of the registers has changed value and, therefore, the configuration
that form the CRC. Bit b0 is the least significant bit, and Bit b31 is
of the ADE7953 has changed. Note that since the CRC updates at
the most significant.
a rate of 6.99 kHz, consecutive reads should be at least 143 µs
g i, i = 0, 1, 2, …, 31 are the coefficients of the generating (1/6.99 kHz) apart. The recommended response is to issue a
polynomial defined by the IEEE802.3 standard as follows: hardware/software reset, which resets all ADE7953 registers,
G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + including reserved registers, to their default values. The
x4 + x2 + x + 1. ADE7953 should then be reconfigured with the design-specific
settings.
g0 = g1 = g2 = g4 = g5 = g7 = 1
An interrupt associated with the checksum feature can provide
g8 = g10 = g11 = g12 = g16 = g22 = g26 = g31 = 1 (50)
an external warning signal on the IRQ pin if the CRC register
All of the other g i coefficients are equal to 0. value changes after initial configuration. This interrupt is dis-
FB(j) = aj – 1 XOR b31(j – 1) (51) abled by default and can be enabled by setting the CRC bit (Bit 21)
in the IRQENA register (Address 0x22C and Address 0x32C).
b0(j) = FB(j) AND g0 (52)
When this interrupt is enabled, an external interrupt is issued
bi(j) = FB(j) AND gi XOR bi − 1(j – 1), i = 1, 2, 3, ..., 31 (53) if the CRC value changes from the value that it held at the time
Equation 51, Equation 52, and Equation 53 must be repeated for that it was enabled.
j = 1, 2, …, 1024. The value written into the Checksum register
contains the Bit bi(1024), i = 0, 1, …, 31.

Rev. C | Page 58 of 72
Data Sheet ADE7953
Table 12. Registers Included in the Checksum
Configuration and Control Registers Calibration Registers
Register Name Address Register Name Address
LCYCMODE 0x004 AIGAIN 0x280 and 0x380
PGA_V 0x007 AVGAIN 0x281 and 0x381
PGA_IA 0x008 AWGAIN 0x282 and 0x382
PGA_IB 0x009 AVARGAIN 0x283 and 0x383
WRITE_PROTECT 0x040 AVAGAIN 0x284 and 0x384
CONFIG 0x102 Reserved 0x285 and 0x385
CF1DEN 0x103 AIRMSOS 0x286 and 0x386
CF2DEN 0x104 Reserved 0x287 and 0x387
CFMODE 0x107 VRMSOS 0x288 and 0x388
PHCALA 0x108 AWATTOS 0x289 and 0x389
PHCALB 0x109 AVAROS 0x28A and 0x38A
ALT_OUTPUT 0x110 AVAOS 0x28B and 0x38B
ACCMODE 0x201 and 0x301 BIGAIN 0x28C and 0x38C
IRQENA 0x22C and 0x32C BVGAIN 0x28D and 0x38D
IRQENB 0x22F and 0x32F BWGAIN 0x28E and 0x38E
BVARGAIN 0x28F and 0x38F
BVAGAIN 0x290 and 0x390
Reserved 0x291 and 0x391
BIRMSOS 0x292 and 0x392
Reserved 0x293 and 0x393
Reserved 0x294 and 0x394
BWATTOS 0x295 and 0x395
BVAROS 0x296 and 0x396
BVAOS 0x297 and 0x397

Rev. C | Page 59 of 72
ADE7953 Data Sheet

ADE7953 REGISTERS
The ADE7953 contains registers that are 8, 16, 24, and 32 bits long. All signed registers are in the twos complement format with the
exception of the PHCALA and PHCALB registers, which are in sign magnitude format. The 24-bit and 32-bit registers contain the same
data but can be accessed in two different register lengths. The 24-bit register option increases communication speed; the 32-bit register
option provides simplicity when coding with the long format. When accessing the 32-bit registers, only the lower 24 bits contain valid
data (the upper 8 bits are sign extended). A write to a 24-bit register changes the value in the corresponding 32-bit register, and vice versa.
Therefore, each 24-bit/32-bit register can be thought of as one memory location that can be accessed via two different paths.
Table 13. 8-Bit Registers
Address Register Name R/W Default Type Register Description
0x000 SAGCYC R/W 0x00 Unsigned Sag line cycles
0x001 DISNOLOAD R/W 0x00 Unsigned No-load detection disable (see Table 16)
0x004 LCYCMODE R/W 0x40 Unsigned Line cycle accumulation mode configuration (see Table 17)
0x007 PGA_V R/W 0x00 Unsigned Voltage channel gain configuration (Bits[2:0])
0x008 PGA_IA R/W 0x00 Unsigned Current Channel A gain configuration (Bits[2:0])
0x009 PGA_IB R/W 0x00 Unsigned Current Channel B gain configuration (Bits[2:0])
0x040 WRITE_PROTECT R/W 0x00 Unsigned Write protection bits (Bits[2:0])
0x0FD LAST_OP R 0x00 Unsigned Contains the type (read or write) of the last successful communication (0x35 =
read; 0xCA = write)
0x0FF LAST_RWDATA R 0x00 Unsigned Contains the data from the last successful 8-bit register communication
0x702 Version R N/A Unsigned Contains the silicon version number
0x800 EX_REF R/W 0x00 Unsigned Reference input configuration: set to 0 for internal; set to 1 for external

Table 14. 16-Bit Registers

Address Register Name R/W Default Type Register Description
0x100 ZXTOUT R/W 0xFFFF Unsigned Zero-crossing timeout
0x101 LINECYC R/W 0x0000 Unsigned Number of half line cycles for line cycle energy accumulation mode
0x102 CONFIG R/W 0x8004 Unsigned Configuration register (see Table 18)
0x103 CF1DEN R/W 0x003F Unsigned CF1 frequency divider denominator. When modifying this register, two
sequential write operations must be performed to ensure that the write is
successful.
0x104 CF2DEN R/W 0x003F Unsigned CF2 frequency divider denominator. When modifying this register, two
sequential write operations must be performed to ensure that the write is
successful.
0x107 CFMODE R/W 0x0300 Unsigned CF output selection (see Table 19)
0x108 PHCALA R/W 0x0000 Signed Phase calibration register (Current Channel A). This register is in sign
magnitude format.
0x109 PHCALB R/W 0x0000 Signed Phase calibration register (Current Channel B). This register is in sign
magnitude format.
0x10A PFA R 0x0000 Signed Power factor (Current Channel A)
0x10B PFB R 0x0000 Signed Power factor (Current Channel B)
0x10C ANGLE_A R 0x0000 Signed Angle between the voltage input and the Current Channel A input
0x10D ANGLE_B R 0x0000 Signed Angle between the voltage input and the Current Channel B input
0x10E Period R 0x0000 Unsigned Period register
0x110 ALT_OUTPUT R/W 0x0000 Unsigned Alternative output functions (see Table 20)
0x1FE LAST_ADD R 0x0000 Unsigned Contains the address of the last successful communication
0x1FF LAST_RWDATA R 0x0000 Unsigned Contains the data from the last successful 16-bit register communication
0x120 Reserved R/W 0x0000 Unsigned This register should be set to 30h to meet the performance specified in
Table 1. To modify this register, it must be unlocked by setting Register
Address 0xFE to 0xAD immediately prior.

Rev. C | Page 60 of 72
Data Sheet ADE7953
Table 15. 24-Bit/32-Bit Registers
Address
24-Bit 32-Bit Register Name R/W Default Type Register Description
0x200 0x300 SAGLVL R/W 0x000000 Unsigned Sag voltage level
0x201 0x301 ACCMODE R/W 0x000000 Unsigned Accumulation mode (see Table 21)
0x203 0x303 AP_NOLOAD R/W 0x00E419 Unsigned Active power no-load level
0x204 0x304 VAR_NOLOAD R/W 0x00E419 Unsigned Reactive power no-load level
0x205 0x305 VA_NOLOAD R/W 0x000000 Unsigned Apparent power no-load level
0x210 0x310 AVA R 0x000000 Signed Instantaneous apparent power (Current Channel A)
0x211 0x311 BVA R 0x000000 Signed Instantaneous apparent power (Current Channel B)
0x212 0x312 AWATT R 0x000000 Signed Instantaneous active power (Current Channel A)
0x213 0x313 BWATT R 0x000000 Signed Instantaneous active power (Current Channel B)
0x214 0x314 AVAR R 0x000000 Signed Instantaneous reactive power (Current Channel A)
0x215 0x315 BVAR R 0x000000 Signed Instantaneous reactive power (Current Channel B)
0x216 0x316 IA R 0x000000 Signed Instantaneous current (Current Channel A)
0x217 0x317 IB R 0x000000 Signed Instantaneous current (Current Channel B)
0x218 0x318 V R 0x000000 Signed Instantaneous voltage (voltage channel)
0x21A 0x31A IRMSA R 0x000000 Unsigned IRMS register (Current Channel A)
0x21B 0x31B IRMSB R 0x000000 Unsigned IRMS register (Current Channel B)
0x21C 0x31C VRMS R 0x000000 Unsigned VRMS register
0x21E 0x31E AENERGYA R 0x000000 Signed Active energy (Current Channel A)
0x21F 0x31F AENERGYB R 0x000000 Signed Active energy (Current Channel B)
0x220 0x320 RENERGYA R 0x000000 Signed Reactive energy (Current Channel A)
0x221 0x321 RENERGYB R 0x000000 Signed Reactive energy (Current Channel B)
0x222 0x322 APENERGYA R 0x000000 Signed Apparent energy (Current Channel A)
0x223 0x323 APENERGYB R 0x000000 Signed Apparent energy (Current Channel B)
0x224 0x324 OVLVL R/W 0xFFFFFF Unsigned Overvoltage level
0x225 0x325 OILVL R/W 0xFFFFFF Unsigned Overcurrent level
0x226 0x326 VPEAK R 0x000000 Unsigned Voltage channel peak
0x227 0x327 RSTVPEAK R 0x000000 Unsigned Read voltage peak with reset
0x228 0x328 IAPEAK R 0x000000 Unsigned Current Channel A peak
0x229 0x329 RSTIAPEAK R 0x000000 Unsigned Read Current Channel A peak with reset
0x22A 0x32A IBPEAK R 0x000000 Unsigned Current Channel B peak
0x22B 0x32B RSTIBPEAK R 0x000000 Unsigned Read Current Channel B peak with reset
0x22C 0x32C IRQENA R/W 0x100000 Unsigned Interrupt enable (Current Channel A, see Table 22)
0x22D 0x32D IRQSTATA R 0x000000 Unsigned Interrupt status (Current Channel A, see Table 23)
0x22E 0x32E RSTIRQSTATA R 0x000000 Unsigned Reset interrupt status (Current Channel A)
0x22F 0x32F IRQENB R/W 0x000000 Unsigned Interrupt enable (Current Channel B, see Table 24)
0x230 0x330 IRQSTATB R 0x000000 Unsigned Interrupt status (Current Channel B, see Table 25)
0x231 0x331 RSTIRQSTATB R 0x000000 Unsigned Reset interrupt status (Current Channel B)
N/A 0x37F CRC R 0xFFFFFFFF Unsigned Checksum
0x280 0x380 AIGAIN R/W 0x400000 Unsigned Current channel gain (Current Channel A)
0x281 0x381 AVGAIN R/W 0x400000 Unsigned Voltage channel gain
0x282 0x382 AWGAIN R/W 0x400000 Unsigned Active power gain (Current Channel A)
0x283 0x383 AVARGAIN R/W 0x400000 Unsigned Reactive power gain (Current Channel A)
0x284 0x384 AVAGAIN R/W 0x400000 Unsigned Apparent power gain (Current Channel A)
0x285 0x385 Reserved R/W 0x000000 Signed This register should not be modified.
0x286 0x386 AIRMSOS R/W 0x000000 Signed IRMS offset (Current Channel A)
0x287 0x387 Reserved R/W 0x000000 Signed This register should not be modified.
0x288 0x388 VRMSOS R/W 0x000000 Signed VRMS offset
0x289 0x389 AWATTOS R/W 0x000000 Signed Active power offset correction (Current Channel A)
0x28A 0x38A AVAROS R/W 0x000000 Signed Reactive power offset correction (Current Channel A)
0x28B 0x38B AVAOS R/W 0x000000 Signed Apparent power offset correction (Current Channel A)

Rev. C | Page 61 of 72
ADE7953 Data Sheet
Address
24-Bit 32-Bit Register Name R/W Default Type Register Description
0x28C 0x38C BIGAIN R/W 0x400000 Unsigned Current channel gain (Current Channel B)
0x28D 0x38D BVGAIN R/W 0x400000 Unsigned This register should not be modified.
0x28E 0x38E BWGAIN R/W 0x400000 Unsigned Active power gain (Current Channel B)
0x28F 0x38F BVARGAIN R/W 0x400000 Unsigned Reactive power gain (Current Channel B)
0x290 0x390 BVAGAIN R/W 0x400000 Unsigned Apparent power gain (Current Channel B)
0x291 0x391 Reserved R/W 0x000000 Signed This register should not be modified.
0x292 0x392 BIRMSOS R/W 0x000000 Signed IRMS offset (Current Channel B)
0x293 0x393 Reserved R/W 0x000000 Unsigned This register should not be modified.
0x294 0x394 Reserved R/W 0x000000 Unsigned This register should not be modified.
0x295 0x395 BWATTOS R/W 0x000000 Signed Active power offset correction (Current Channel B)
0x296 0x396 BVAROS R/W 0x000000 Signed Reactive power offset correction (Current Channel B)
0x297 0x397 BVAOS R/W 0x000000 Signed Apparent power offset correction (Current Channel B)
0x2FF 0x3FF LAST_RWDATA R 0x000000 Unsigned Contains the data from the last successful 24-bit/32-bit
register communication

ADE7953 REGISTER DESCRIPTIONS

Table 16. DISNOLOAD Register (Address 0x001)
Bits Bit Name Default Description
0 DIS_APNLOAD 0 1 = disable the active power no-load feature on Current Channel A and Current Channel B
1 DIS_VARNLOAD 0 1 = disable the reactive power no-load feature on Current Channel A and Current Channel B
2 DIS_VANLOAD 0 1 = disable the apparent power no-load feature on Current Channel A and Current Channel B

Table 17. LCYCMODE Register (Address 0x004)

Bits Bit Name Default Description
0 ALWATT 0 0 = disable active energy line cycle accumulation mode on Current Channel A
1 = enable active energy line cycle accumulation mode on Current Channel A
1 BLWATT 0 0 = disable active energy line cycle accumulation mode on Current Channel B
1 = enable active energy line cycle accumulation mode on Current Channel B
2 ALVAR 0 0 = disable reactive energy line cycle accumulation mode on Current Channel A
1 = enable reactive energy line cycle accumulation mode on Current Channel A
3 BLVAR 0 0 = disable reactive energy line cycle accumulation mode on Current Channel B
1 = enable reactive energy line cycle accumulation mode on Current Channel B
4 ALVA 0 0 = disable apparent energy line cycle accumulation mode on Current Channel A
1 = enable apparent energy line cycle accumulation mode on Current Channel A
5 BLVA 0 0 = disable apparent energy line cycle accumulation mode on Current Channel B
1 = enable apparent energy line cycle accumulation mode on Current Channel B
6 RSTREAD 1 0 = disable read with reset for all registers
1 = enable read with reset for all registers

Table 18. CONFIG Register (Address 0x102)

Bits Bit Name Default Description
0 INTENA 0 1 = integrator enable (Current Channel A)
1 INTENB 0 1 = integrator enable (Current Channel B)
2 HPFEN 1 1 = HPF enable (all channels)
3 PFMODE 0 0 = power factor is based on instantaneous powers
1 = power factor is based on line cycle accumulation mode energies
4 REVP_CF 0 0 = REVP is updated on CF1
1 = REVP is updated on CF2
5 REVP_PULSE 0 0 = REVP is high when reverse polarity is true, low when reverse polarity is false
1 = REVP outputs a 1 Hz pulse when reverse polarity is true and is low when reverse polarity is false
6 ZXLPF 0 0 = ZX LPF is enabled
1 = ZX LPF is disabled
7 SWRST 0 Setting this bit enables a software reset
Rev. C | Page 62 of 72
Data Sheet ADE7953
Bits Bit Name Default Description
8 CRC_ENABLE 0 0 = CRC is disabled
1 = CRC is enabled
[10:9] Reserved 00 Reserved
11 ZX_I 0 0 = ZX_I is based on Current Channel A
1 = ZX_I is based on Current Channel B
[13:12] ZX_EDGE 00 Zero-crossing interrupt edge selection
Setting Edge Selection
00 Interrupt is issued on both positive-going and negative-going zero crossing
01 Interrupt is issued on negative-going zero crossing
10 Interrupt is issued on positive-going zero crossing
11 Interrupt is issued on both positive-going and negative-going zero crossing
14 Reserved 0 Reserved
15 COMM_LOCK 1 0 = communication locking feature is enabled
1 = communication locking feature is disabled

Table 19. CFMODE Register (Address 0x107)

Bits Bit Name Default Description
[3:0] CF1SEL 0000 Configuration of output signal on CF1 pin
Setting CF1 Output Signal Configuration
0000 CF1 is proportional to active power (Current Channel A)
0001 CF1 is proportional to reactive power (Current Channel A)
0010 CF1 is proportional to apparent power (Current Channel A)
0011 CF1 is proportional to IRMS (Current Channel A)
0100 CF1 is proportional to active power (Current Channel B)
0101 CF1 is proportional to reactive power (Current Channel B)
0110 CF1 is proportional to apparent power (Current Channel B)
0111 CF1 is proportional to IRMS (Current Channel B)
1000 CF1 is proportional to IRMS (Current Channel A) + IRMS (Current Channel B)
1001 CF1 is proportional to active power (Current Channel A) + active power
(Current Channel B)
[7:4] CF2SEL 0000 Configuration of output signal on CF2 pin
Setting CF2 Output Signal Configuration
0000 CF2 is proportional to active power (Current Channel A)
0001 CF2 is proportional to reactive power (Current Channel A)
0010 CF2 is proportional to apparent power (Current Channel A)
0011 CF2 is proportional to IRMS (Current Channel A)
0100 CF2 is proportional to active power (Current Channel B)
0101 CF2 is proportional to reactive power (Current Channel B)
0110 CF2 is proportional to apparent power (Current Channel B)
0111 CF2 is proportional to IRMS (Current Channel B)
1000 CF2 is proportional to IRMS (Current Channel A) + IRMS (Current Channel B)
1001 CF2 is proportional to active power (Current Channel A) + active power
(Current Channel B)
8 CF1DIS 1 0 = CF1 output is enabled
1 = CF1 output is disabled
9 CF2DIS 1 0 = CF2 output is enabled
1 = CF2 output is disabled

Rev. C | Page 63 of 72
ADE7953 Data Sheet
Table 20. ALT_OUTPUT Register (Address 0x110)
Bits Bit Name Default Description
[3:0] ZX_ALT 0000 Configuration of ZX pin (Pin 1)
Setting ZX Pin Configuration
0000 ZX detection is output on Pin 1 (default)
0001 Sag detection is output on Pin 1
0010 Reserved
0011 Reserved
0100 Reserved
0101 Active power no-load detection (Current Channel A) is output on Pin 1
0110 Active power no-load detection (Current Channel B) is output on Pin 1
0111 Reactive power no-load detection (Current Channel A) is output on Pin 1
1000 Reactive power no-load detection (Current Channel B) is output on Pin 1
1001 Unlatched waveform sampling signal is output on Pin 1
1010 IRQ signal is output on Pin 1
1011 ZX_I detection is output on Pin 1
1100 REVP detection is output on Pin 1
1101 Reserved (set to default value)
111x Reserved (set to default value)
[7:4] ZXI_ALT 0000 Configuration of ZX_I pin (Pin 21)
Setting ZX_I Pin Configuration
0000 ZX_I detection is output on Pin 21 (default)
0001 Sag detection is output on Pin 21
0010 Reserved
0011 Reserved
0100 Reserved
0101 Active power no-load detection (Current Channel A) is output on Pin 21
0110 Active power no-load detection (Current Channel B) is output on Pin 21
0111 Reactive power no-load detection (Current Channel A) is output on Pin 21
1000 Reactive power no-load detection (Current Channel B) is output on Pin 21
1001 Unlatched waveform sampling signal is output on Pin 21
1010 IRQ signal is output on Pin 21
1011 ZX detection is output on Pin 21
1100 REVP detection is output on Pin 21
1101 Reserved (set to default value)
111x Reserved (set to default value)
[11:8] REVP_ALT 0000 Configuration of REVP pin (Pin 20)
Setting REVP Pin Configuration
0000 REVP detection is output on Pin 20 (default)
0001 Sag detection is output on Pin 20
0010 Reserved
0011 Reserved
0100 Reserved
0101 Active power no-load detection (Current Channel A) is output on Pin 20
0110 Active power no-load detection (Current Channel B) is output on Pin 20
0111 Reactive power no-load detection (Current Channel A) is output on Pin 20
1000 Reactive power no-load detection (Current Channel B) is output on Pin 20
1001 Unlatched waveform sampling signal is output on Pin 20
1010 IRQ signal is output on Pin 20
1011 ZX detection is output on Pin 20
1100 ZX_I detection is output on Pin 20
1101 Reserved (set to default value)
111x Reserved (set to default value)

Rev. C | Page 64 of 72
Data Sheet ADE7953
Table 21. ACCMODE Register (Address 0x201 and Address 0x301)
Bits Bit Name Default Description
[1:0] AWATTACC 00 Current Channel A active energy accumulation mode
Setting Active Energy Accumulation Mode (Current Channel A)
00 Normal mode
01 Positive-only accumulation mode
10 Absolute accumulation mode
11 Reserved
[3:2] BWATTACC 00 Current Channel B active energy accumulation mode
Setting Active Energy Accumulation Mode (Current Channel B)
00 Normal mode
01 Positive-only accumulation mode
10 Absolute accumulation mode
11 Reserved
[5:4] AVARACC 00 Current Channel A reactive energy accumulation mode
Setting Reactive Energy Accumulation Mode (Current Channel A)
00 Normal mode
01 Antitamper accumulation mode
10 Absolute accumulation mode
11 Reserved
[7:6] BVARACC 00 Current Channel B reactive energy accumulation mode
Setting Reactive Energy Accumulation Mode (Current Channel B)
00 Normal mode
01 Antitamper accumulation mode
10 Absolute accumulation mode
11 Reserved
8 AVAACC 0 0 = Current Channel A apparent energy accumulation is in normal mode
1 = Current Channel A apparent energy accumulation is based on IRMSA
9 BVAACC 0 0 = Current Channel B apparent energy accumulation is in normal mode
1 = Current Channel B apparent energy accumulation is based on IRMSB
10 APSIGN_A 0 0 = active power on Current Channel A is positive
1 = active power on Current Channel A is negative
11 APSIGN_B 0 0 = active power on Current Channel B is positive
1 = active power on Current Channel B is negative
12 VARSIGN_A 0 0 = reactive power on Current Channel A is positive
1 = reactive power on Current Channel A is negative
13 VARSIGN_B 0 0 = reactive power on Current Channel B is positive
1 = reactive power on Current Channel B is negative
[15:14] Reserved 00 Reserved
16 ACTNLOAD_A 0 0 = Current Channel A active energy is out of no-load condition
1 = Current Channel A active energy is in no-load condition
17 VANLOAD_A 0 0 = Current Channel A apparent energy is out of no-load condition
1 = Current Channel A apparent energy is in no-load condition
18 VARNLOAD_A 0 0 = Current Channel A reactive energy is out of no-load condition
1 = Current Channel A reactive energy is in no-load condition
19 ACTNLOAD_B 0 0 = Current Channel B active energy is out of no-load condition
1 = Current Channel B active energy is in no-load condition
20 VANLOAD_B 0 0 = Current Channel B apparent energy is out of no-load condition
1 = Current Channel B apparent energy is in no-load condition
21 VARNLOAD_B 0 0 = Current Channel B reactive energy is out of no-load condition
1 = Current Channel B reactive energy is in no-load condition

Rev. C | Page 65 of 72
ADE7953 Data Sheet
Interrupt Enable and Interrupt Status Registers
Current Channel A and Voltage Channel Registers

Table 22. IRQENA Register (Address 0x22C and Address 0x32C)

Bits Bit Name Description
0 AEHFA Set to 1 to enable an interrupt when the active energy is half full (Current Channel A)
1 VAREHFA Set to 1 to enable an interrupt when the reactive energy is half full (Current Channel A)
2 VAEHFA Set to 1 to enable an interrupt when the apparent energy is half full (Current Channel A)
3 AEOFA Set to 1 to enable an interrupt when the active energy has overflowed or underflowed (Current Channel A)
4 VAREOFA Set to 1 to enable an interrupt when the reactive energy has overflowed or underflowed (Current Channel A)
5 VAEOFA Set to 1 to enable an interrupt when the apparent energy has overflowed or underflowed (Current Channel A)
6 AP_NOLOADA Set to 1 to enable an interrupt when the active power no-load condition is detected on Current Channel A
7 VAR_NOLOADA Set to 1 to enable an interrupt when the reactive power no-load condition is detected on Current Channel A
8 VA_NOLOADA Set to 1 to enable an interrupt when the apparent power no-load condition is detected on Current Channel A
9 APSIGN_A Set to 1 to enable an interrupt when the sign of active energy has changed (Current Channel A)
10 VARSIGN_A Set to 1 to enable an interrupt when the sign of reactive energy has changed (Current Channel A)
11 ZXTO_IA Set to 1 to enable an interrupt when the zero crossing has been missing on Current Channel A for the length of
time specified in the ZXTOUT register
12 ZXIA Set to 1 to enable an interrupt when the current Channel A zero crossing occurs
13 OIA Set to 1 to enable an interrupt when the current Channel A peak has exceeded the overcurrent threshold set in the
OILVL register
14 ZXTO Set to 1 to enable an interrupt when a zero crossing has been missing on the voltage channel for the length of
time specified in the ZXTOUT register
15 ZXV Set to 1 to enable an interrupt when the voltage channel zero crossing occurs
16 OV Set to 1 to enable an interrupt when the voltage peak has exceeded the overvoltage threshold set in the OVLVL
register
17 WSMP Set to 1 to enable an interrupt when new waveform data is acquired
18 CYCEND Set to 1 to enable an interrupt when it is the end of a line cycle accumulation period
19 Sag Set to 1 to enable an interrupt when a sag event has occurred
20 Reset This interrupt is always enabled and cannot be disabled
21 CRC Set to 1 to enable an interrupt when the checksum has changed

Table 23. IRQSTATA Register (Address 0x22D and Address 0x32D) and RSTIRQSTATA Register (Address 0x22E and
Address 0x32E)
Bits Bit Name Description
0 AEHFA Set to 1 when the active energy register is half full (Current Channel A)
1 VAREHFA Set to 1 when the reactive energy register is half full (Current Channel A)
2 VAEHFA Set to 1 when the apparent energy register is half full (Current Channel A)
3 AEOFA Set to 1 when the active energy register has overflowed or underflowed (Current Channel A)
4 VAREOFA Set to 1 when the reactive energy register has overflowed or underflowed (Current Channel A)
5 VAEOFA Set to 1 when the apparent energy register has overflowed or underflowed (Current Channel A)
6 AP_NOLOADA Set to 1 when the active power no-load condition is detected Current Channel A
7 VAR_NOLOADA Set to 1 when the reactive power no-load condition is detected Current Channel A
8 VA_NOLOADA Set to 1 when the apparent power no-load condition is detected Current Channel A
9 APSIGN_A Set to 1 when the sign of active energy has changed (Current Channel A)
10 VARSIGN_A Set to 1 when the sign of reactive energy has changed (Current Channel A)
11 ZXTO_IA Set to 1 when a zero crossing has been missing on Current Channel A for the length of time specified in the
ZXTOUT register
12 ZXIA Set to 1 when a current Channel A zero crossing is detected
13 OIA Set to 1 when the current Channel A peak has exceeded the overcurrent threshold set in the OILVL register
14 ZXTO Set to 1 when a zero crossing has been missing on the voltage channel for the length of time specified in the
ZXTOUT register
15 ZXV Set to 1 when the voltage channel zero crossing is detected
16 OV Set to 1 when the voltage peak has exceeded the overvoltage threshold set in the OVLVL register

Rev. C | Page 66 of 72
Data Sheet ADE7953
Bits Bit Name Description
17 WSMP Set to 1 when new waveform data is acquired
18 CYCEND Set to 1 at the end of a line cycle accumulation period
19 Sag Set to 1 when a sag event has occurred
20 Reset Set to 1 at the end of a software or hardware reset
21 CRC Set to 1 when the checksum has changed

Current Channel B Registers

Table 24. IRQENB Register (Address 0x22F and Address 0x32F)

Bits Bit Name Description
0 AEHFB Set to 1 to enable an interrupt when the active energy is half full (Current Channel B)
1 VAREHFB Set to 1 to enable an interrupt when the reactive energy is half full (Current Channel B)
2 VAEHFB Set to 1 to enable an interrupt when the apparent energy is half full (Current Channel B)
3 AEOFB Set to 1 to enable an interrupt when the active energy has overflowed or underflowed (Current Channel B)
4 VAREOFB Set to 1 to enable an interrupt when the reactive energy has overflowed or underflowed (Current Channel B)
5 VAEOFB Set to 1 to enable an interrupt when the apparent energy has overflowed or underflowed (Current Channel B)
6 AP_NOLOADB Set to 1 to enable an interrupt when the active power no-load detection on Current Channel B occurs
7 VAR_NOLOADB Set to 1 to enable an interrupt when the reactive power no-load detection on Current Channel B occurs
8 VA_NOLOADB Set to 1 to enable an interrupt when the apparent power no-load detection on Current Channel B occurs
9 APSIGN_B Set to 1 to enable an interrupt when the sign of active energy has changed (Current Channel B)
10 VARSIGN_B Set to 1 to enable an interrupt when the sign of reactive energy has changed (Current Channel B)
11 ZXTO_IB Set to 1 to enable an interrupt when a zero crossing has been missing on Current Channel B for the length of time
specified in the ZXTOUT register
12 ZXIB Set to 1 to enable an interrupt when the current Channel B zero crossing occurs
13 OIB Set to 1 to enable an interrupt when the current Channel B peak has exceeded the overcurrent threshold set in the
OILVL register

Table 25. IRQSTATB Register (Address 0x230 and Address 0x330) and RSTIRQSTATB Register (Address 0x231 and
Address 0x331)
Bits Bit Name Description
0 AEHFB Set to 1 when the active energy register is half full (Current Channel B)
1 VAREHFB Set to 1 when the reactive energy register is half full (Current Channel B)
2 VAEHFB Set to 1 when the apparent energy register is half full (Current Channel B)
3 AEOFB Set to 1 when the active energy register has overflowed or underflowed (Current Channel B)
4 VAREOFB Set to 1 when the reactive energy register has overflowed or underflowed (Current Channel B)
5 VAEOFB Set to 1 when the apparent energy register has overflowed or underflowed (Current Channel B)
6 AP_NOLOADB Set to 1 when the active power no-load condition is detected on Current Channel B
7 VAR_NOLOADB Set to 1 when the reactive power no-load condition is detected on Current Channel B
8 VA_NOLOADB Set to 1 when the apparent power no-load condition is detected on Current Channel B
9 APSIGN_B Set to 1 when the sign of active energy has changed (Current Channel B)
10 VARSIGN_B Set to 1 when the sign of reactive energy has changed (Current Channel B)
11 ZXTO_IB Set to 1 when a zero crossing has been missing on Current Channel B for the length of time specified in the
ZXTOUT register
12 ZXIB Set to 1 when a current Channel B zero crossing is obtained
13 OIB Set to 1 when current Channel B peak has exceeded the overcurrent threshold set in the OILVL register

Rev. C | Page 67 of 72
ADE7953 Data Sheet

LAYOUT GUIDELINES
Figure 78 presents a basic schematic of the ADE7953 together
with its surrounding circuitry, decoupling capacitors at pins
VDD, VINTA, VINTD, and REF, and the 3.58 MHz crystal and
its load capacitors. The rest of the pins are dependent on the
particular application and are not shown here.
Figure 77 presents a proposed layout of a printed circuit board
(PCB) with two layers that have the components placed only on
the top of the board. Following these layout guidelines will help
in creating a low noise design with higher immunity to EMC
influences.
The VDD, VINTA, VINTD, and REF pins each have two
decoupling capacitors, one of μF order and a ceramic one of
220 nF or 100 nF. These ceramic capacitors need to be placed
closest to the ADE7953 as they decouple high frequency noises,
while the μF ones need to be place in close proximity.
The exposed pad of the ADE7953 is soldered to an equivalent
pad on the PCB. The AGND, DGND, and PULL_LOW pins
traces of the ADE7953 are then routed directly in to the PCB
pad.

09320-178
The bottom layer is composed mainly of a ground plane
surrounding as much as possible the through hole crystal pins. Figure 77. ADE7953 Top Layer Printed Circuit Board

C6 C5
0.1µF 10µF
C3
7 8 17 0.1µF
PULL_HIGH

PULL_HIGH

VDD

2 RESET ZX 1 C4
4.7µF
5 IAP VINTD 3
6 IAN C1
9 IBP VINTA 15 0.1µF
C7 10 IBN
20pF CLKOUT 19
2

Y1 U1 C2
11 VN 4.7µF
3.58MHz IRQ 22
C8 ADE7953
1

20pF 12 VP
ZX_I 21
18 CLKIN
REVP 20
25 SCLK
27 MOSI/SCL/Rx CF1 23

28 CS CF2 24
C9 13 REF MISO/SDA/Tx 26
0.1µF
PULL_LOW

C10
DGND

AGND

4.7µF
PAD

4 16 14
09320-177

Figure 78. ADE7953 Crystal and Capacitors Connections

Rev. C | Page 68 of 72
Data Sheet ADE7953

OUTLINE DIMENSIONS
5.10 0.30
5.00 SQ 0.25
PIN 1 4.90 0.20
INDICATOR PIN 1
22 28 INDICATOR
0.50 21 1

BSC
3.24
EXPOSED
PAD 3.14 SQ
3.04

15 7

0.58 14 8
0.20 MIN
TOP VIEW BOTTOM VIEW
0.53
0.48
0.80
0.75
0.05 MAX
0.70
0.02 NOM
COPLANARITY
SEATING 0.08
PLANE 0.203 REF

03-29-2016-A
PKG-005090

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-1.

Figure 79. 28-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body and 0.75 mm Package Height
(CP-28-10)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
ADE7953ACPZ −40°C to +85°C 28-Lead LFCSP_WQ CP-28-10
ADE7953ACPZ-RL −40°C to +85°C 28-Lead LFCSP_WQ, 13” Tape and Reel CP-28-10
EVAL-ADE7953EBZ Evaluation Board
1 Z = RoHS Compliant Part.

Rev. C | Page 69 of 72
ADE7953 Data Sheet

NOTES

Rev. C | Page 70 of 72
Data Sheet ADE7953

NOTES

Rev. C | Page 71 of 72
ADE7953 Data Sheet

NOTES

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

©2011–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D09320-0-12/16(C)

Rev. C | Page 72 of 72