MSP430

Architecture
 Microcontroller characteristics
this is one of the first at 16 bit

Integration: Able to implement a whole design onto a single

chip.

Cost: Are usually low-cost devices (a few $ each);

Clock frequency: Compared with other devices

(microprocessors and DSPs), MCUs use a low clock frequency:
MCUs today run up to 100 MHz/100 MIPS (Million
Instructions Per Second).

Power consumption: Low power (battery operation);

Bits: 4 bits (older devices) to 32 bits devices;

Memory: Limited available memory, usually less than 1 MByte;

Input/Output (I/O): Low to high (8 to 150) pin-out count.

2
 MSP430 main characteristics (1/3)

Low power consumption: this microcontroller

⇒ made winner

0.1 A for RAM data retention; It can be alineted with tiff .

it to start up
voltages and is
fast
0.8 A for real-time clock mode operation;
very

250 A/MIPS during active operation.

Low operation voltage (from 1.8 V to 3.6 V);

< 1 s clock start-up; off and on quite immediately

< 50 nA port leakage;

Zero-power Brown-Out Reset (BOR).

3
 MSP430 main characteristics (2/3)

On-chip analogue features:

10/12/16-bit Analogue-to-Digital Converter (ADC);
12-bit dual Digital-to-Analogue Converter (DAC);
Comparator-gated timers;
Operational Amplifiers (Op Amps);
Supply Voltage Supervisor (SVS).
If we want ,
we can create a filter ,
using
resistance and capacitor to analog pot

16 bit RISC CPU:

Compact core design reduces power consumption and cost;
16-bit data bus;
27 core instructions;
7 addressing modes;
Extensive vectored-interrupt capability.
↳they are extremely asgnoenous

4
 MSP430 main characteristics (3/3)

Flexibility:
Up to 256 kByte Flash; ⇒ keep
the code
used to near ran

memory

Up to 100 pins;
USART, I2C, Timers;
LCD driver;
Embedded emulation; for floating
→
point

And many more peripherals modules…

Microcontroller performance:
Instruction processing on either bits, bytes or words
Reduced instructions set;
Compiler efficient;
Wide range of peripherals;
Flexible clock system.

5
 MSP430 Architecture
16 Bit

Block diagram: 0 00
This Von Neumann all
ojpppp }
is because to
.

bus
.

we have connected some 8%4%9

ADDRESSES

Address bus is

} flash tniuueeaoifddendateauabuess
position
in those

| RAM

; diff type .

of memory
do

not
overlap
And also some peripheral
are connected and
be configured can
ex .
for a timer

*
at
software level
there is no difference ,

It charge where
only
we willread
Y
MAPPING
MEMORY
Also the peripheral
are

peripheral
mapped as
they are

6
 MSP430 architecture

peripheral oriented do net need

Peripherals using
the BUS some are byte →
16 bit
To save
space
use 8 bit bus
and uses
only
the lower
part of original

signed

for serial
communication
needa small
Clock

simulation :
debugging
if He red hardware check dock by deck the
stag and also see what happen before and after an operation
we use ,
we can
using
,
,
 MSP430X16X Architecture

ALU ADC
DAC I/O Port

Registers

Interrupts

HW Multiplier DMA USARTx

TIMERs
 Address Space

Mapped into a single, contiguous address space:

All memory, including RAM, Flash/ROM, information
memory, special function registers (SFRs), and peripheral
registers.
Memory Address Description Access
End: 0FFFFh Interrupt Vector Table ⇒ interrupt manager
Word/Byte

Memory Map:
Start: 0FFE0h volatile
memory
non

End: 0FFDFh
Flash/ROM
Word/Byte ⇒ when finished an
0F800h
for each component have documentation and Start *:
01100h
application we use prom
, and a

firmware to set
, we
write a

need to check what need how use register

only
we
,
010FFh
and how to End *:
manage memory 0107Fh Information Memory Word/Byte
obd data
It can happens also
that we can
have holes Start: 01000h (Flash devices only) tree to use for program }
in the that cause segmentation errors End: 0FFFh Boot Memory
can
Word/Byte
memory
,

Start: 0C00h (Flash devices only)

↳
departing
on
flash
we will have differences here
09FFh first part :
if
boot needed
End *: system →

027Fh RAM Word/Byte bad motion

program
Start: 0200h
End: 01FFh
16-bit Peripheral modules Word ⇒
2nd set of registers
Start: 0100h
End: 00FFh
8-bit Peripheral modules Byte ⇒ first set of registers
Start: 0010h
End: 000Fh bytes
Special Function Registers Byte first 16
Start: 0000h

9
 Interrupt vector table

Mapped at the very end of memory space (upper 16

words of Flash/ROM): 0FFE0h - 0FFFEh (4xx devices);
Priority of the interrupt vector increases with the word
address.

10
 Central Processing Unit (MSP430 CPU) (1/7)

RISC (Reduced Instructions Set Computing)

architecture:
Instructions are reduced to the basic ones (short set):
• 27 physical instructions;
• 24 emulated instructions.

This provides simpler and faster instruction decoding;

Interconnect by a using a common memory address bus

PROGRAM
(MAB) and memory data bus (MDB) - Von Neumann
N
architecture:
SAVE
AND
IN

TEST
RAM
• Makes use of only one storage structure for data and
: instructions sets.
Good
,
SAVE
IN FASN

• The separation of the storage processing unit is implicit;

• Instructions are treated as data (programmable).

11
 Central Processing Unit (MSP430 CPU) (2/7)

RISC (Reduced Instructions Set Computing) type

architecture:
Uses a 3-stage instruction pipeline containing:
• Instruction decoding;
• 16 bit ALU;
• 4 dedicated-use registers; ⇒ for specific operations program
counter Ro ⇒
,
the
copy of code

• 12 working registers. copied

atIt
instruction register
is

is
in

used
the

instruction
any

Address bus has 16 bit so it can address 65 kB (including

RAM + Flash + Registers);

Arithmetic Logic Unit (ALU):

Addition, subtraction, comparison and logical (AND, OR,
XOR) operations;
Operations can affect the overflow, zero, negative, and carry
flags of the SR (Status Register).
12
 Central Processing Unit (MSP430 CPU) (3/7)

Incorporates sixteen 16-bit registers:

• 4 registers (R0, R1, R2 and R3) have dedicated functions;
• 12 register are working registers (R4 to R15) for general
use.
R0: Program Counter (PC):
Points to the next instruction to be read from memory and
executed by the CPU.
Stack : Incremental decremented LIFO
memory
or

R1: Stack Pointer (SP): Will point red data the RAM ( the stack )
in area need a
pointer

9
1st: stack can be used by user to store data for later use can

only
move

up or
dow

(instructions: store by PUSH, retrieve by POP); order 9

sequential
STACK ⇒

HEAP ⇒ whoever we want

can
go
←
share the decide
they memory ,
we

how much

2nd: stack can be used by user or by compiler for subroutine

parameters (PUSH, POP in calling routine; addressed via offset
calculation on stack pointer (SP) in called subroutine);

13
 Central Processing Unit (MSP430 CPU) (4/7)

R1: Stack Pointer (SP) (continued):

3rd: used by subroutine calls to store the program counter
value for return at subroutine's end (RET);

4th: used by interrupt - system stores the actual PC value

first, then the actual status register content (on top of stack)
on return from interrupt (RETI) the system get the same
status as just before the interrupt happened (as long as none
has changed the value on TOS) and the same program
counter value from stack.
( the )
dimension
50% of stack used to external data
acquisition to not know priori
Usually memory
is in
, heap is we a

14
 Central Processing Unit (MSP430 CPU) (5/7)

R2: Status Register (SR): important event also changing

⇒
bit andchange the some we can

behaviour of CPU the Clock power consumption and

Stores status and control bits;

ex
,

System flags are changed automatically by the CPU;

Reserved bits are used to support the constant generator.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved for CG1 V SCG1 SCG0 OSCOFF CPUOFF GIE N Z C

Bit Description
8 V Overflow bit. V = 1 Result of an arithmetic operation overflows the signed-variable range.

7 SCG1 System clock generator 0. SCG1 = 1 DCO generator is turned off – if not used for MCLK or SMCLK

6 SCG0 System clock generator 1. SCG0 = 1 FLL+ loop control is turned off
5 OSCOFF Oscillator Off. OSCOFF = 1 turns off LFXT1 when it is not used for MCLK or SMCLK

4 CPUOFF CPU off. CPUOFF = 1 disable CPU core.

3 GIE General interrupt enable. GIE = 1 enables maskable interrupts.

2 N Negative flag. N = 1 result of a byte or word operation is negative.

1 Z Zero flag. Z = 1 result of a byte or word operation is 0.

0 C Carry flag. C = 1 result of a byte or word operation produced a carry.

15
 Central Processing Unit (MSP430 CPU) (6/7)

R2/R3: Constant Generator Registers (CG1/CG2):

Depending of the source-register addressing modes (As)
value, six constants can be generated without code word or
code memory access to retrieve them.
Program counter is word oriented 2
Byte , 340
@ make change of instruction
faster)

This is a very powerful feature which allows the

implementation of emulated instructions, for example,
instead of implement a core instruction for an increment the
constant generator is used.
Register As Constant Remarks
R2 00 - Register mode
R2 01 (0) Absolute mode
R2 10 00004h +4, bit processing
R2 11 00008h +8, bit processing
R3 00 00000h 0, word processing
R3 01 00001h +1

{
generate constants
R3 10 00002h +2, bit processing
R3 11 0FFFFh -1, word processing

16
 Central Processing Unit (MSP430 CPU) (7/7)

R4 - R15: General–Purpose
Registers:
These general-purpose registers are
adequate to store data registers,
address pointers, or index values
and can be accessed with byte or
word instructions.
All the bit the
registers are 16 and
first 4 are reserved

17
Central Processing Unit (MSP430X CPU) (1/9)
→
extension of the standard MSPGZO

Main features of the MSP430X CPU architecture:

The MSP430X CPU extends the addressing capabilities of the
MSP430 family beyond 64 kB to 1 MB;

To achieve this, some changes have been made to the

addressing modes and two new types of instructions have
been added;

One instruction type allows access to the entire address

space, and the other is designed for address calculations;

The MSP430X CPU address bus has 20 bits, although the

data bus still has 16 bits. Memory accesses to 8-bit, 16-bit
and 20-bit data are supported;

Despite these changes, the MSP430X CPU remains

compatible with the MSP430 CPU, having a similar number
of registers.

18
Central Processing Unit (MSP430X CPU) (2/9)

Organization of the MSP430X CPU:

Although the MSP430X CPU structure is
similar to that of the MSP430 CPU, there
are some differences that will now be
highlighted;

With the exception of the status register

SR, all MSP430X registers are 20 bits;

The CPU can now process 20-bit or 16-

bit data.

19
Central Processing Unit (MSP430X CPU) (3/9)

The MSP430X CPU has 16 registers, some of which have

special use:

R0 (PC) Program Counter:

Has the same function as the MSP430 CPU, although now it
has 20 bits.

R1 (SP) Stack Pointer:

Has the same function as the MSP430 CPU, although now it
has 20 bits.

R2 (SR) Status Register:

Has the same function as the MSP430 CPU, but it still has 16
bits.

20
Central Processing Unit (MSP430X CPU) (4/9)

R2 (SR) Status Register:

Description of the SR bits:

21
Central Processing Unit (MSP430X CPU) (5/9)

R2 (SR/CG1) and R3 (CG2) Constant Generators:

Registers R2 and R3 can be used to generate six different
constants commonly used in programming, without adding
an additional 16-bit word to the instruction;

The constants are fixed and are selected by the (As) bits of
the instruction. (As) selects the addressing mode.

Values of constants
generated:

22
Central Processing Unit (MSP430X CPU) (6/9)

R2 (SR/CG1) and R3 (CG2) Constant Generators:

Whenever the operand is one of the six constants, the
registers are selected automatically;
Therefore, when used in constant mode, registers R2 and R3
cannot be used as source registers.

R4-R15 – General-purpose registers:

Have the same function as in the MSP430 CPU, although
they now have 20 bits;

These registers can process 8-bit, 16-bit or 20-bit data;

If a byte is written to one of these registers it takes bits 7:0,

the bits 19:8 are filled with zeroes. If a word is written to
one of these registers it takes bits 15:0, the bits 19:16 are
filled with zeroes.

23
Addressing Summary
 Instruction set

If is a RISC architecture

27 core instructions;
emulated with than 1 instructions
by the compiler → more
'

e. s are
mapped

24 emulated instructions;

z
instruction is orthogonal to the other everyone
The instruction set is orthogonal; every
=

has specific function to

only a
,
ex sum
,
access
memory , ...

The core instructions have unique opcodes decoded by

the CPU, while the emulated ones need assemblers and
compilers for their mnemonics;

There are three core-instruction formats:

Double operand;
Single operand;
Program flow control - Jump.

48
Core Instructions
Total Instructions
 The MSP430
CPU
Memory Address Register Program Counter Status Register
L
Memory

to change

.w
a

the instruction
fast Destination Operand
-
with a
constant generated

the multiple er
by Source Operand Memory
Multiplexer Mapped I/O

Bus Driver Port 1 Output

16 16-bit
Registers

Instruction Register Arithmetic Logic Unit Lots of Gates

Condition Codes
 Fetching an Instruction

Basic finite state machine MSP 430

PC program
counter

=
single we an
load
,

data only
only
on

instructions
Device Systems and
Operating Modes

System Reset
 System reset (1/5)
restart the
of
type the last to microcontroller
Is present in
any
microprocessor ,
and is
way

The MSP430 families make use of two independent reset

signals:
Hardware reset signal - POR (Power On Reset);
Software reset signal – PUC (Power Up Clear).

Different events determine which one of the reset

signals is generated;

Sources that can generate a POR:

Initial device power up; want known state set bit to ⇒ we
every
peripheral in a =) all zero

Low signal at the reset pin (RST/NMI) when this is

configured in reset mode; to ⇒ or so this set 0 the peripheral

Low signal at the supervisory voltage system (SVS) when

the register bit PORON is high.
 System reset (2/5)

Sources that can generate a PUC:

Active POR signal;
Watchdog timer (WDT) expired when it is configured in
supervision mode;
Flash memory access control registers security key violation.
an the to generate a reset : →
way
.
P IN CONTROL

Louynibn voltage = > leave the capability

to to last instruction store
,
ex
something , .

Nordmare
-
errors
Clock
errors
.
timers

watchdog timer

Hardware
flash
ever
from
memory
 System reset (3/5)

Conditions:

Hardware reset signal (POR) is active then:

• SR is reset;
• PC is loaded with the address in location 0FFFEh;
• Peripheral registers all enter their power up state.

Software reset signal (PUC) is active then:

• SR is reset; only peripheral
some are vetted

• PC is loaded with either the reset vector (0FFFEh), or the

PUC source interrupt vector;
• Only some peripheral registers are reset by PUC.
 System reset (4/5)

All 2xx and 4xx MSP430 devices possess a reset circuit

by power source disturbance identified by Brown Out
Reset (BOR);

This circuit is an enhanced POR system:

Includes a hysteresis circuit;
Device stays in reset mode until voltage is higher than the
upper threshold (VB_IT+):
• BOR takes 2 msec to be inactive and allow the program
execution by CPU;
When voltage falls below the lower threshold (VB_IT-):
• BOR circuit will generate a reset signal;
• Suspends processor operation until the voltage rises up
above the lower threshold inferior value.
 System reset (5/5)

Brownout timing:
power supply qggottatsupplyist.MY
befoeadnatethe
oockiimwefietinoffttoeoe g tinetotefasfogions
rn -
Device Systems and
Operating Modes

System Clocks
 System clocks (1/16)

Allows the CPU and peripherals to operate from different

clock sources; peripherals not all
most need
the clock
generate
,
clock
have same dock
,
we need
cap .
to more

The system clocks depend on the device in the MSP430

family:
UP To THREE Checks

MSP430x2xx:
• The Basic Clock Module+ (BCM+);
– One or two oscillators (depending on the device);
– Capable of working with external crystals or
resonators;
– Internal digitally controlled oscillator (DCO);
– Working frequency to up 16 MHz;
– Lower power consumption;
– Lower internal oscillator start-up time.
 System clocks (2/16)

MSP430x2xx:
• Basic Clock+:
external with digital
dock is generated oscillator , and be intend or a .
put
by as can ,

k
and
#
components

alternate
( low speed )

o@ Town

using the capacitor

.YFk¥U
,

the three not create

_' out

mq→.→aD clock
.

master
a

small
A =

( standard )
signal
create
of the

faster
oscillator
dock
,
we can use the
delay
+0
fleeing
:p
the
more
chip is
.

good is usually
reliable than the oscillator
that
.

can have error on

mounting , ...

this type of oscillator

is
Problems ⇒
not need
oscillators and
regular , we
Crystal
must be external add cost
component and
⇒ intend oxillator for sane peripherals that
ex , dense
resistancechange , goes at master dock or
faster
clock
 System clocks (3/16)

MSP430x4xx:
• Frequency Locked Loop (FLL+):

– One or two oscillators (depending on the device);

– Capable of working with external crystals or

resonators;

– Internal digitally controlled oscillator (DCO), adjusted

and controlled by hardware;

– Synchronized to a high-frequency internal clock from

a low frequency external oscillator.
 System clocks (4/16)

MSP430x4xx:
• FLL+:
datasheet and manual can better how the dock works
Controlling ,
we see
 System clocks (5/16)

The clock sources from these oscillators can be selected to

generate different clock signals:

Master clock (MCLK):

• Generated by DCO (but can also be fed by the crystal
oscillator);
• Activate and stable in less than 6 sec;
• Used by the CPU and high-speed peripherals.

Subsystem main clock (SMCLK):

• Used as alternative clock source for peripherals.

Auxiliary clock (ACLK):

• RTC self wake-up function from low power modes (32.768
kHz);
• Always fed by the crystal oscillator.

Each clock can be internally divided by a factor of 1, 2, 4 or 8.

 System clocks (6/16)

Low/High frequency oscillator (LFXT1):

Implemented in all MSP430 devices;

Used with either:

• Low-frequency 32.768 kHz watch crystals (RTC);
• Standard crystals, resonators, or external clock sources
in range 450 kHz to 8 MHz (16 MHz in 2xx family).

The operating mode selection (one bit):

• (=0) -> LF clock;
• (=1) -> HF clock.

• XTS: located at the BCSCTL1 register (2xx family);

• XTS_FLL: located at the FLL_CTL0 register (4xx family).
 System clocks (7/16)
Second crystal oscillator (XT2):
Sources of XT2CLK and its characteristics are identical to
LFXT1 in HF mode (range 450 kHz to 8 MHz, or 16 MHz in
the 2xx family);

Load capacitance for the high frequency crystal or

resonator must be provided externally;

This oscillator can be disabled by the XT2OFF bit:

• BCSCTL1 register in 2xx family;
• FLL_CTL1 register in 4xx family (if XT2CLK is unused
for source the MCLK and SMCLK clock signals).
 System clocks (8/16)

Digitally-controlled oscillator (DCO):

Integrated ring oscillator with RC-type characteristics;

Provide a wide, software-controllable frequency range;

DCO frequency is synchronized to the FLL;

Frequency modulation method provided by FLL

functionality:

• 2xx family:
– Does not have full FLL functionality;
– The DCO generates an internal signal (DCOCLK):
» Programmed internally or externally (DCOR bit);
» Controlled by a resistor connected to the ROSC
and VCC pins.
 System clocks (9/16)

• 2xx family:
– The DCO control bits:
» RSELx: fDCO range selection;
» DCOx: fDCO defined by the RSEL bits. The step size
is defined by the parameter SDCO;
» MODx: Modulation bits select how often
fDCO(RSEL, DCO+1) is used within the period of 32
DCOCLK cycles.
» The frequency fDCO(RSEL, DCO) is used for the
remaining cycles.

– Specific frequency ranges and values vary by device:

32 fDCO(RSEL,DCO) fDCO(RSEL,DCO 1)
f avg
MOD fDCO(RSEL,DCO) 32 MOD fDCO(RSEL,DCO 1)
 System clocks (10/16)

• 2xx family:
– Basic Clock Module+ (BCM+) registers configuration:
» DCOCTL: DCO Control Register
7 6 5 4 3 2 1 0

DCOx MODx

Bit Description
7-5 DCOx Discrete DCO frequency selection step (depends on RSELx bits).
4-0 MODx Modulator selection.
 System clocks (11/16)
msp 430 has Standard 1MHz deck
,
if we want to change , we use He first tire of code with some specific bits

• 2xx family:
,

– Basic Clock Module+ (BCM+) registers configuration:

» BCSCTL1: Basic Clock System Control Reg. 1
7 6 5 4 3 2 1 0

XT2OF XTS DIVAx RSELx

Bit Description

7 XT2OF XT2 oscillator fault:

XT2OF = 0 XT2 normal operation
XT2OF = 1 XT2 fault condition
6 XTS LFXT1 oscillator operating mode:
XTS = 0 LF mode (low frequency)
XTS = 1 HF mode (high frequency)
bit for every
bit division
5-4 DIVAx ACLK frequency divider: of
L type there also
,
word for MSP 430
are key
DIVA1 DIVA0 = 0 0 /1
DIVA1 DIVA0 = 0 1 /2
DIVA1 DIVA0 = 1 0 /4
DIVA1 DIVA0 = 1 1 /8
3-0 RSELx Range select. Sixteen different frequency ranges are available.
 System clocks (12/16)

• 2xx family:
– Basic Clock Module+ (BCM+) registers configuration:
» BCSCTL2: Basic Clock System Control Reg. 2
7 6 5 4 3 2 1 0
SELMx DIVMx SELS DIVSx DCOR
Bit Description
7-6 SELMx MCLK source: SELM1 SELM0 = 0 0 DCO
SELM1 SELM0 = 0 1 DCO
SELM1 SELM0 = 1 0 XT2
SELM1 SELM0 = 1 1 LFXT1
5-4 DIVMx MCLK frequency divider: DIVM1 DIVM0 = 0 0 /1
DIVM1 DIVM0 = 0 1 /2
DIVM1 DIVM0 = 1 0 /4
DIVM1 DIVM0 = 1 1 /8
3 SELS SMCLK source: SELS = 0 DCO
SELS = 1 XT2

2-1 DIVSx SMCLK frequency divider: DIVS1 DIVS0 = 0 0 /1

DIVS1 DIVS0 = 0 1 /2
DIVS1 DIVS0 = 1 0 /4
DIVS1 DIVS0 = 1 1 /8
0 DCOR DCO resistor selector DCOR = 0 Internal resistor
DCOR = 1 External resistor
 System clocks (13/16)

• 2xx family:
– Basic Clock Module+ (BCM+) registers configuration:
» BCSCTL3: Basic Clock System Control Reg. 3
7 6 5 4 3 2 1 0
XT2Sx LFXT1Sx XCAPx XT2OFF LFXT1OF
Bit Description
7-6 XT2Sx XT2 range select: XT2S1 XT2S0 = 0 0 0.4 – 1 MHz
XT2S1 XT2S0 = 0 1 1– 3 MHz
XT2S1 XT2S0 = 1 0 3– 16 MHz
XT2S1 XT2S0 = 1 1 0.4 – 16-MHz (Digital external)
5-4 LFXT1Sx Low-frequency clock select and LFXT1 range select: XTS=0: XTS=1:
LFXT1S1 LFXT1S0 = 0 0 32768 Hz 0.4 - 1-MHz
LFXT1S1 LFXT1S0 = 0 1 Reserved 1 - 3-MHz
LFXT1S1 LFXT1S0 = 1 0 VLOCLK 3 - 16-MHz
LFXT1S1 LFXT1S0 = 1 1 External 0.4 - 16-MHz
3-2 XCAPx Oscillator capacitor selection: XCAP1 XCAP0 = 0 0 ~1 pF
XCAP1 XCAP0 = 0 1 ~6 pF
XCAP1 XCAP0 = 1 0 ~10 pF
XCAP1 XCAP0 = 1 1 ~12.5 pF
1 XT2OFF XT2 oscillator fault: XT2OFF = 0 No fault condition
XT2OFF = 1 Fault condition

0 LFXT1OF LFXT1OF oscillator fault: LFXT1OF = 0 No fault condition

LFXT1OF = 1 Fault condition
 System clocks (14/16)

Internal clock signals:

In 2xx family clock system = the basic clock module+:
• Support for a 32768 Hz watch crystal oscillator;
• Internal very-low-power low-frequency oscillator;
• Internal digitally-controlled oscillator (DCO) stable <1 μs.

The BCM+ provides the following clock signals:

– Auxiliary clock (ACLK), sourced either from:
» 32768 Hz watch crystal;
» Internal oscillator LFXT1CLK in LF mode with an
internal load capacitance of 6 pF.
– Main clock (MCLK), the system clock used by the CPU;
– Sub-Main clock (SMCLK), the sub-system clock used
by the peripheral modules.
 System clocks (15/16)

Internal clock signals:

Both MCLK and SMCLK are sourced from DCOCLK at
~1.1 MHz but can be sourced up to 16 MHz;

2xx DCO calibration data (in flash info memory segment A).
to
keywords change
y frequency

DCO frequency Calibration register Size Address

CALBC1_1MHZ Byte 010FFh
1 MHz
CALBC0_1MHZ Byte 010FEh
CALBC1_8MHZ Byte 010FDh
8 MHz
CALBC0_8MHZ Byte 010FCh
CALBC1_12MHZ Byte 010FBh
12 MHz
CALBC0_12MHZ Byte 010FAh
CALBC1_16MHZ Byte 010F9h
16 MHz
CALBC0_16MHZ Byte 010F8h
 System clocks (16/16)

Internal clock signals: Increment of psvmptin

power
In
Psacftt inventing fog will invent
,
so

power consumption
.

and reduce voltage

Electrical characteristics vary over the recommended supplyh

,

supply

voltage range of between 2.2 V and 3.6 V. Higher DCO signal must to be

frequencies require higher supply voltages. very fast

Typical characteristics in active mode supply current for they

(2xx family): Larsen
.to?Esoitw0
.

minmqngisffffestienvbeaseswithfeg

µ cannot increase more

•
 Device Systems and
Operating Modes

Watchdog and
Supervisory Voltage System
 Watchdog timer (WDT and WDT+) (1/4)
to
Next week we will se what is a
timer it has some dedicated function , ex if there is an infinite
loop stop
if there
,

The 16-bit WDT module can be used in: cheek

periodically
the
it resets
CPU and

It is not
is
Something wrong
.

intelligent it just timer

Supervision mode:
so is a
,

f.
GO red
• Ensure the correct working of the software application;

f⇒fIg÷¥e
W
• Perform a PUC;
reset

de
need to select
• Generate an interrupt request after the counter
some periodic check
reset the counter and make
overflows.
that

if correctly working it is not resettle ⇒ If Everything its ok it can last forever

the men 's continue so ,

Interval timer:
,
,

• Independent interval timer to perform a “standard”

interrupt upon counter overflow periodically;
• Upper counter (WDTCNT) is not directly accessible by
software;
• Control and the interval time selecting WDTCTL register;
• WDTCNT: clock signal ACLK or SMCLK (WDTSSEL bit).
 Watchdog timer (WDT and WDT+) (2/4)

The WDT control is performed through the:

WDTCTL, Watchdog Timer Control Register, WDTCTL

• Eight MSBs (WDTPW): Password function, read as

0x69h, write as 0x5Ah unless the user want to force a
15
PUC from software. 8
Read with the value 0x69h, WDTPW write with the value 0x5Ah
 Watchdog timer (WDT and WDT+) (3/4)

The WDT control is performed through the:

WDTCTL, Watchdog Timer Control Register, WDTCTL
we can
select a
lot of functionalities like passwords and so on

it work in

• Eight LSBs: WDT configuration

we can also avoid to make supervision
doesn't grade reset but normal interrupt
↳ it
a
a
, ,

be recorded as
simple timer
7 6 5 4 3 2 1 0
on can

WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTIS1 WDTIS0

Bit Description
7 WDTHOLD WDT hold when WDTHOLD = 1. Useful for energy economy.
6 WDTNMIES Select the NMI interrupt edge when WDTNMI = 1 WDTNMIES = 0 NMI on rising edge
WDTNMIES = 1 NMI on falling edge

5 WDTNMI Select the RST/NMI pin function WDTNMI = 0 Reset function

WDTNMI = 1 NMI function

4 WDTTMSEL Select the WDT mode: WDTTMSEL = 0 Supervision mode

WDTTMSEL = 1 Interval timer mode

3 WDTCNTCL WDT counter clear: WDTCNTCL = 0 No action

WDTCNTCL = 1 Counter initialization at 0x0000h

2 WDTSSEL Select the WDT clock signal: WDTSSEL = 0 SMCLK

WDTSSEL = 1 ACLK

1-0 WDTISx Select the WDT timer interval: WDTIS1 WDTIS0 = 0 0 Clock signal / 32768
WDTIS1 WDTIS0 = 0 1 Clock signal / 8192
WDTIS1 WDTIS0 = 1 0 Clock signal / 512
WDTIS1 WDTIS0 = 1 1 Clock signal / 64
 Watchdog timer (WDT and WDT+) (4/4)

The WDT uses two bits in the Special Function Registers

(SFRs) for interrupt control:
• WDTIE: WDT interrupt enable (IE1.0):
– Enables the WDTIFG interrupt for interval timer mode
when WDTIE=1.

• WDTIFG: WDT interrupt flag (IFG1.0):

– Supervision mode:
» WDTIFG sources a reset vector interrupt.
» If WDTIFG=1, the WDT initiates the reset
condition (detectable reset source).

– Interval mode:
» WDTIFG set after the selected time interval and
requests a WDT interval timer interrupt;
» WDTIE and GIE bits set;
» WDTIFG reset automatically (also can be reset by
software).
 Supervisory Voltage System (SVS) (1/2)

Used to monitor:
AVCC supply voltage;
External voltage (located at the SVSIN input).

When AVCC or SVSIN drops below selected threshold:

Sets a flag generating an interrupt;
Generates a system reset (POR).

Is disabled after a BOR to conserve current consumption;

SVS features:
• Output of SVS comparator accessible by software;
• Low-voltage condition latched (accessible by software);
• 14 selectable threshold levels;
• External channel to monitor external voltage.
 Supervisory Voltage System (SVS) (2/2)

SVS control performed by:

SVSCTL, SVS Control Register
7 6 5 4 3 2 1 0
VLDx PORON SVSON SVSOP SVSFG

Bit Description
7-4 VLDx Voltage level detect. VLD3 VLD2 VLD1 VLD0 = 0000 SVS is off
VLD3 VLD2 VLD1 VLD0 = 0001 1.9 V
VLD3 VLD2 VLD1 VLD0 = 0010 2.1 V
.
.
.

VLD3 VLD2 VLD1 VLD0 = 1101 3.5 V

VLD3 VLD2 VLD1 VLD0 = 1110 3.7 V
VLD3 VLD2 VLD1 VLD0 = 1111 SVSIN to 1.25V
3 PORON When PORON = 1 enables the SVSFG flag to cause a POR device reset
2 SVSON This bit reflects the status of SVS operation, being set (SVSON=1) when the SVS is on
1 SVSOP This bit reflects the output value of the SVS comparator:
SVSOP = 0 SVS comparator output is low
SVSOP = 1 SVS comparator output is high
0 SVSFG When SVSFG=1 a low voltage condition occurs
SCRIBD =t anti PDF

Device Systems and

Operating Modes

Interrupts
 Interrupt management

handle events that happen

Interrupts: combinatory circuit very complex that asynchronous
way
can in

Are events applied to the application program that force a

detour in program flow;
whk waiting
ex :
if we are
waiting for a

key
bad input we can use an interrupt to save
power waiting
or
prepare
operations

⇒ we can handing exceptions or

waiting events

Cause CPU subprogram execution (ISR);

Be@
When Interrupt Service Routine (ISR) ends, the program flow
±
=L -

-
yes
=) execute
returns to the previous state.
a script if called by
We
an
have MASKABLE
extend event
interrupt

and
can

non MASKABLE EVENT

⇒
the
and
to

cpu
we
not
can

dot
happen
also

There are three classes of interrupts:

that
event arrive

anyway
to the CPU we have or
not
can

• Reset;
,

a routine
for then
of the
.

hardware
They are dated terror
• Interrupts not maskable by GIE; If we do not have a routine the
pagan
will
,

continue
creating failures
• Interrupts maskable by GIE.
,
more

84
 Interrupt management

Execution of a program proceeds predictably, with

interrupts being the exception
Interrupts are usually generated by hardware
Processor stops with it is doing,
Stores enough information to later resume,
Executes an interrupt service routine (ISR),
Restores saved information,
Resumes execution.
An interrupt is an asynchronous signal indicating the
need for attention
 Interrupt management

A way to respond to an external event (i.e., flag being set)

without polling
How it works:
H/W senses flag being set
Automatically transfers control to s/w that “services” the interrupt
When done, H/W returns control to wherever it left off

Main Prog
Advantages: ISR
:
Transparent to user :
cleaner code :
:
μC doesn’t waste time polling RETI
 Interrupt Flags
Each interrupt has a flag that is raised (set) when the

inat#upt
mask it with
interrupt occurs.
AND
Now to mask
an
is boolean value and
interrupt
an a we can

any
,
,

Giessen
Switch
interrupt enable only
off all
,
Bit that
one
[email protected]
in flag set to O He is will ⇒ source signal never arrive

Each interrupt flag has a corresponding enable bit –

at the end

setting this bit allows a hardware module to request

an interrupt. do not want that useless it add execution
do not have something
configured and modify
switch interrupt off if signal
we on
on is good we

Most interrupts are

maskable, which means
they can only interrupt if
1) enabled and
2) the general interrupt
enable (GIE) bit is set in
the status register (SR). GIE
 Importance of the Status Register

Status Register (SR):

Stores status and control bits;
System flags are changed automatically by the CPU;
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved for CG1 V SCG1 SCG0 OSCOFF CPUOFF GIE N Z C

Bit Description
8 V Overflow bit. V = 1 Result of an arithmetic operation overflows the signed-variable range.

7 SCG1 System clock generator 0. SCG1 = 1 DCO generator is turned off – if not used for MCLK or SMCLK

6 SCG0 System clock generator 1. SCG0 = 1 FLL+ loop control is turned off
5 OSCOFF Oscillator Off. OSCOFF = 1 turns off LFXT1 when it is not used for MCLK or SMCLK

4 CPUOFF CPU off. CPUOFF = 1 disable CPU core.

3 GIE General interrupt enable. GIE = 1 enables maskable interrupts.

2 N Negative flag. N = 1 result of a byte or word operation is negative.

1 Z Zero flag. Z = 1 result of a byte or word operation is 0.

0 C Carry flag. C = 1 result of a byte or word operation produced a carry.

88
 Interrupt management

Interrupts preempt normal code execution

Interrupt code runs in the foreground
Normal (e.g. main()) code runs in the background
Interrupts can be enabled and disabled
Globally
Individually on a per-peripheral basis
Non-Maskable Interrupt (NMI)
The occurrence of each interrupt is unpredictable
When an interrupt occurs
Where an interrupt occurs
Interrupts are associated with a variety of on-chip and off-
chip peripherals.
Timers, Watchdog, D/A, Accelerometer
NMI, change-on-pin (Switch)
 Interrupt management

usually not all the routines have the same importance ,

so
, if in the same time arrive
more
than a
signal
will be execute the more important first
Interrupts commonly used for
,

Urgent tasks w/higher priority than main code

Infrequent tasks to save polling overhead
Waking the CPU from sleep
Call to an operating system (software interrupt).

Event-driven programming
The flow of the program is determined by events—i.e.,
sensor outputs or user actions (mouse clicks, key presses)
or messages from other programs or threads.
The application has a main loop with event detection and
event handlers.
 Interrupt management

The interrupts are used to:

Allow a CPU fast response to a specific event;
Avoiding continuous polling for rare events;
Minimal disruption to the processing of other tasks.

In GIE-maskable interrupts, if both peripheral interrupt

enable bit and GIE are set, when an interrupt is
requested, it calls the ISR;

The interrupt latency time:

t between the event beginning and the ISR execution;
Interrupt latency time starts with acceptance of IR and
counting until starting of first instruction of ISR.

91
 Interrupt management
In the
memory
I will have the main code and some
good routines for the

During an interrupt event: interrupt the

common

with an
operations
P.C.tothe routine and then
stone
I want
in the
to none
stack counter of the
come back

PC of the next instruction and the SR are pushed onto the

we have so to the pro San main code
memory
and then
load the

stack; completed The ⇒ restore of counter the routine

ROUTINE and address need also to
Program ,
and we save

transparent routine of resister it for the state CPU status reset

After
register To The save we
status so now I an ,

Afterwards, the SR is cleared with exception of SCG0, along

,
the routine

with the appropriate interrupt, disabling interrupts (reset

the GIE flag); MAIN PREBLEM Find the address of the stored in interrupt vector
'

: ⇒ If routine is

Other ISRs will not be called. table at the end of bit for each of the table kbytd
,
memory
⇒ 16 line

the table The position in is related to He

priority

The RETI instruction at the end of the ISR will return to

the original program flow, automatically popping the SR
and PC;

Ensure that:
The ISR processing time is less than the interrupt’s request
time interval;
To avoid stack overflow -> application program collapse.
 Interrupt management

Types of interrupts (internal and external):

Reset;
Interrupts not maskable by GIE: (non)-maskable interrupts
(NMI);
Interrupts maskable by GIE.
Interrupts priority (The nearer a module is to the
CPU/NMIRS, the higher the priority).
 Interrupt management

Types of interrupts (internal and external):

Main differences between non-maskable and maskable

interrupts:
• Non-maskable interrupts cannot be disabled by the GIE
bit of the SR. Used for high priority events e.g.
emergency shutdown;

• Maskable interrupts are recognized by the CPU’s

interrupt control, so the GIE bit must be set. Can be
switched off by software.

The system reset interrupts (Oscillator/Flash and the Hard

Reset) are treated as highest priority non-maskable
interrupts, with their own interrupt vectors.
 Interrupt management

Types of interrupts (internal and external):

Non Maskable Interrupts:
• Not masked by GIE;
• Enabled by individual interrupt enable bits;

• Depend on the event source:

– NMIIE: Non-Maskable Interrupts Interrupt Enable:
» RST/NMI is configured in NMI mode;
» WDTNMIES bit generates an NMI;
» The RST/NMI flag NMIIFG is also set.

– ACCVIE: ACCess Violation to the flash memory

Interrupt Enable:
» The flash ACCVIFG flag is set.

– OFIE: Oscillator Fault Interrupt Enable:

» This signal can be triggered by a PUC signal.
 Interrupt management (example)

Types of interrupts (internal and external):

Non Maskable Interrupts:
• Example: ACCVIE (2xx family).
ACCV=1 ACCVIFG=1
ACCVIFG=1 and ACCVIE=1 (set by software) NMIRS=1
 Interrupt management

Types of interrupts (internal and external):

(by GIE) Maskable Interrupts:

• Peripherals with interrupt capability or the watchdog

timer overflow in interval timer mode;

• Individual enable/disable flag, located in peripheral

registers or in the individual module;

• Can be disabled by resetting the GIE bit in SR, either by

software or by hardware/interrupt.
 Interrupt Vectors

The CPU must know where to fetch the next

instruction following an interrupt.

The address of an ISR is defined in an interrupt

vector.

The MSP430 uses vectored interrupts where each ISR

has its own vector stored in a vector table located at
the end of program memory.

Note: The vector table is at a fixed location (defined

by the processor data sheet), but the ISRs can be
located anywhere in memory.
 Interrupt vector table

Mapped at the very end of memory space (upper 16

words of Flash/ROM): 0FFE0h - 0FFFEh (4xx devices);
Priority of the interrupt vector increases with the word
address. vector table

In those address
←
the address
we
find
for the ROUTINE

99
 Processing an Interrupt…

1) Current instruction completed

OR
2) MCLK started if CPU was off
3) Processor pushes program counter on stack
4) Processor pushes status register on stack
5) Interrupt w/highest priority is selected
6) Interrupt request flag cleared if single sourced
7) Status register is cleared
Disables further maskable interrupts (GIE cleared)
Terminates low-power mode
8) Processor fetches interrupt vector and stores it in the
program counter
9) User ISR must do the rest!
Interrupt Stack

return from a
normal routine or from
an
interrupt is quite the some it
,
only changes
the last line ⇒ restore also the state
 Interrupt Service Routines

Look superficially like a subroutine.

However, unlike subroutines
ISR’s can execute at unpredictable times.
Must carry out action and thoroughly clean up.
Must be concerned with shared variables.
Must return using reti rather than ret.
ISR must handle interrupt in such a way that the
interrupted code can be resumed without error
Copies of all registers used in the ISR must be saved
(preferably on the stack)
 Interrupt Service Routines
If we
have a lot of signal for same interrupt:
we have only one bit → will be accepted
only one

Well-written ISRs: If must be settd back to 0

if it is from same

resettle
source
and

yet
If not
-
when the routine is executed the was

If
,
it
interruption will have
Should be short and fast erupt
an
a routine ,
we

nested routines lot

problem need
of
→
,
a PC and SR
of
.

all step if actuation

previous not controlled
, is I can
full
Should affect the rest of the system as little as possible fast stack
,

the
very
and
out
run
of memory
Require a balance between doing very little – thereby t
leaving the background code with lots of processing – If wait the I
routine
of end

and doing a lot and leaving the background code with begin Herat
a

to ,

and
nothing to do
I have seq .
routine

not have problems of 1

stack

Applications that use interrupts should: MSP 430 → dear the status register ,

mask the routines and work

GIE
putty =D →

Disable interrupts as little as possible sequentially and ,

then it is restored at Head
of the routine
Respond to interrupts as quickly as possible
 Interrupt Service Routines

Interrupt-related runtime problems can be

exceptionally hard to debug

Common interrupt-related errors include:

Failing to protect global variables
Forgetting to actually include the ISR - no linker error!
Not testing or validating thoroughly
Stack overflow
Running out of CPU horsepower
Interrupting critical code
Trying to outsmart the compiler
 Returning from ISR

MSP430 requires 6 clock cycles before the ISR

begins executing
The time between the interrupt request and the start of
the ISR is called latency

An ISR always finishes with the return from

interrupt instruction (reti) requiring 5 cycles
The SR is popped from the stack
• Re-enables maskable interrupts
• Restores previous low-power mode of operation
The PC is popped from the stack
Note: if waking up the processor with an ISR, the new
power mode must be set in the stack saved SR
Interrupts in C

….
your code
….
Device Systems and
Operating Modes

Low Power Modes

 Low power operating modes (1/11)

One of the main features of the MSP430 families:

Low power consumption (about 1 mW/MIPS or less);

Important in battery operated embedded systems.

Low power consumption is only accomplished:

Using low power operating modes design;

Depends on several factors such as:

• Clock frequency;
• Ambient temperature;
• Supply voltage;
• Peripheral selection;
• Input/output usage;
• Memory type;
• ...
 Low power operating modes (2/11)

Low power modes (LPM):

6 operating modes;
Configured by the SR bits: CPUOFF, OSCOFF, SCG1, SCG0.

Active mode (AM) - highest power consumption:

• Configured by disabling the SR bits described above;
• CPU is active;
• All enabled clocks are active;
• Current consumption: 250 A.

Software selection up to 5 LPM of operation;

Operation:
• An interrupt event can wake up the CPU from any LPM;
• Service the interrupt request;
• Restore back to the LPM.
 Low power operating modes (3/11)

Low power modes (LPM):

Example: Typical current consumption (41x family).
 Low power operating modes (4/11)

Low power modes (LPM):

Mode Current SR bits configuration Clock signals Oscillator
DC
[ A] CPUOFF OSCOFF SCG1 SCG0 ACLK SMCLK MCLK DCO
gen.
Low-power mode 0
35 1 0 0 0 1 1 0 1 1
(LPM0)
Low-power mode 1
44 1 0 0 1 1 1 0 1 1*
(LPM1)
Low-power mode 2
19 1 0 1 0 1 0 0 0 1
(LPM2)
Low-power mode 3
0.8 1 0 1 1 1 0 0 0 0
(LPM3)
Low-power mode 4
0.1 1 1 1 1 0 0 0 0 0
(LPM4)

*DCO’s DC generator is enabled if it is used by peripherals.

 Low power operating modes (5/11)

Low power modes (LPM) characteristics:

LPM0 to LPM3:
• Periodic processing based on a timer interrupt;
• LPM0: Both DCO source signal and DCO’s DC gen.;
• LPM0 and LPM1: Main difference between them is the
condition of enable/disable the DCO’s DC generator;
• LPM2: DCO’s DC generator is active and DCO is
disabled;
• LPM3: Only the ACLK is active (< 2 μA).

LPM4:
• Externally generated interrupts;
• No clocks are active and available for peripherals.
• Reduced current consumption (0.1 μA).
 Low power operating modes (6/11)

Program flow steps:

Enter Low-power mode:

• Enable/disable CPUOFF, OSCOFF, SCG0, SCG1 bits in
SR;

• LPM is active after writing to SR;

• CPU will suspend the program execution;

• Disabled peripherals:
– Operating with any disabled clock;
– Individual control register settings.

• All I/O port pins and RAM/registers are unchanged;

• Wake up is possible through any enabled interrupt.

 Low power operating modes (7/11)

Program flow steps:

An enabled interrupt event wakes the MSP430;

Enter ISR:
• The operating mode is saved on the stack during ISR;
• The PC and SR are stored on the stack;
• Interrupt vector is moved to the PC;
• The CPUOFF, SCG1, and OSCOFF bits are automatically
reset, enabling normal CPU operation;
• IFG flag cleared on single source flags.

Returning from the ISR:

• The original SR is popped from the stack, restoring the
previous operating mode;
• The SR bits stored in the stack are modified returning to
a different operating mode after RETI instruction.
 Low power operating modes (8/11)

Examples of applications development using the MSP430

with and without low power modes consideration:
Example Without low power mode With low power mode
Toggling the bit 0 of port 1 (P1.0) Endless loop LPM0
periodically (100 % CPU load) Watchdog timer interrupt
UART to transmit the received Polling UART receive UART receive interrupt
message at a 9600 baud rate (100 % CPU load) (0.1 % CPU load)
Set/reset during a time interval,
periodically, of the peripheral Endless loop Setup output unit
connected to the bit 2 of port 1 (100 % CPU load) (Zero CPU load)
(P1.2)
Shutdown the Op-Amp between data
Power manage external devices like Putting the OPA Quiescent
acquisition
Op-Amp (Average current: 1 A)
(Average current: 0.06 A)
Power manage internal devices like Always active Disable Comparator A between data
Comparator A (Average typical current: 35 A) acquisition
Using LPMs while the LED is switch
off:
LPM3: 1.4 A
Respond to button-press interrupt in Endless loop
LPM4: 0.3 A
P1.0 and toggle LED on P2.1 (100 % CPU load)
Configure unused ports in output
direction
P1 interrupt service routine
 Low power operating modes (9/11)

Rules of thumb for the configuration of LP applications:

Extended ultra-low power standby mode. Maximize LPM3;

Minimum active duty cycle;

Performance on-demand;

Use interrupts to control program flow;

Replace software with on chip peripherals;

Manage the power of external devices;

Configure unused pins properly, setting them as outputs to

avoid floating gate current.
 Low power operating modes (10/11)

Rules of thumb for LP applications configuration:

Low-power efficient coding techniques:

• Optimize program flow;
• Use CPU registers for calculations and dedicated
variables;
• Same code size for word or byte;
• Use word operations whenever possible;
• Use the optimizer to reduce code size and cycles;
• Use local variable (CPU registers) instead of global
variables (RAM);
• Use bit mask instead of bit fields;
 Low power operating modes (11/11)

Rules of thumb for LP applications configuration:

Low-power efficient coding techniques:

• Use unsigned data types where possible;
• Use pointers to access structures and unions;
• Use “static const” class to avoid run-time copying of
structures, unions, and arrays;
• Avoid modulo;
• Avoid floating point operations;
• Count down “for” loops;
• Use short ISRs.
 Device Systems and
Operating Modes

Direct Memory Access (DMA)

 DMA capability (1/3)

The MSP430 has been designed for applications

requiring low power;

When the application requires data-handling, the direct

memory access (DMA) capability included in some
devices is useful:
5xxx; FG4xx(x); F261x; F16x(x) and F15x;
Among these: MSP430FG4618 (Experimenter’s board).

DMA automatically handles data;

DMA does not require CPU intervention;

DMA helps reduce the power consumption (CPU remains

sleeping).

120
 DMA capability (2/3)

Concept of DMA: move functionality to peripherals:

Peripherals use less current than the CPU;
Delegating control to peripherals allows the CPU to shut
down (saves power);
“Intelligent” peripherals are more capable, providing a
better opportunity for CPU shutoff;
DMA can be enabled for repetitive data handling, increasing
the throughput of peripheral modules;
Minimal software requirements and CPU cycles.

121
 DMA capability (3/3)

The following TI Application Reports cover the use of the

DMA controller for different applications, with the aim of
lowering power consumption:

• Streamlining the mixed-signal path with the signal-chain-

on-chip MSP430F169 <slyt078.pdf>

• Interfacing the MSP430 with MMC/SD Flash Memory

Cards <slaa281b.pdf>

• Digital FIR Filter Design Using the MSP430F16x

<slaa228.pdf>

• Using the USCI I2C Master <slaa382.pdf>

122
 DMA configuration and operation (1/6)

Block diagram:

123
 DMA configuration and operation (2/6)

DMA controller features:

Three independent transfer channels;

Configurable (ROUNDROBIN bit) DMA channel priorities:

• Default: DMA0−DMA1−DMA2;

DMA Transfer cycle time:

• Requires only two MCLK clock cycles per transfer;
• Each byte/word transfer requires:
– 2 MCLK cycles after synchronization;
– 1 MCKL cycle of wait time after transfer.

124
 DMA configuration and operation (3/6)

DMA controller features:

Block sizes up to 65535 bytes or words;

Configurable edge/level-triggered transfer (DMALEVEL bit).

Byte or word and mixed byte/word transfer capability:

• Byte-to-byte;
• Word-to-word;
• Byte-to-word (upper byte of the destination word is
cleared);
• Word-to-byte (lower byte of the source word is
transferred).

125
 DMA configuration and operation (4/6)

DMA controller features:

Four addressing modes for each DMA channel are independently
configurable (DMASRCINCRx and DMADSTINCRx control bits):
• Fixed address to fixed address;
• Fixed address to block of addresses;
• Block of addresses to fixed address;
• Block of addresses to block of addresses.

126
 DMA configuration and operation (5/6)

DMA controller features:

Six transfer modes (each channel is individually configurable
by the DMADTx bits):

DMADTx Transfer mode Description DMAEN after

transfer
000 Single transfer Each transfer requires a trigger 0
A complete block is transferred
001 Block transfer 0
with one trigger
CPU activity is interleaved with a
010, 011 Burst-block transfer 0
block transfer
Repeated single
100 Each transfer requires a trigger 1
transfer
Repeated block A complete block is transferred
101 1
transfer with one trigger
Repeated burst-block CPU activity is interleaved with a
110, 111 1
transfer block transfer

127
 DMA configuration and operation (6/6)

DMA transfer example

DMA with flash memory:

• Automatically moves data to the Flash memory;
• Performs the data move data word/byte to the Flash;
• The write timing control is done by the Flash controller;
• Write transfers to the Flash memory succeed if the Flash
controller set-up is done before the DMA transfer and if
the Flash is not busy.

All DMA transfers:

• Occur without CPU intervention;
• Operate independently of any low-power modes;
• Increase throughput of modules.

128