1648 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO.

8, AUGUST 2006

A 95-dB Linear Low-Power Variable Gain Amplifier

Quoc-Hoang Duong, Student Member, IEEE, Quan Le, Student Member, IEEE,
Chang-Wan Kim, Student Member, IEEE, and Sang-Gug Lee, Member, IEEE

Abstract—An all-CMOS variable gain amplifier (VGA) that

adopts a new approximated exponential equation is presented. The
proposed VGA is characterized by a wide range of gain variation,
temperature-independence gain characteristic, low-power con-
sumption, small chip size, and controllable dynamic gain range.
The two-stage VGA is fabricated in 0.18- m CMOS technology
and shows the maximum gain variation of more than 95 dB and a
90-dB linear range with linearity error of less than 1 dB. The
range of gain variation can be controlled from 68 to 95 dB. The
P1dB varies from 48 to 17 dBm, and the 3-dB bandwidth
is from 32 MHz (at maximum gain of 43 dB) to 1.05 GHz (at
minimum gain of 52 dB). The VGA dissipates less than 3.6 mA
from 1.8-V supply while occupying 0.4 mm2 of chip area excluding Fig. 1. Example of digital- and analog-controlled VGAs. (a) Digital-controlled
bondpads. VGA. (b) Analog-controlled VGAs.
Index Terms—Amplifier, analog, automatic gain control (AGC),
transceiver, variable gain amplifier (VGA). to discontinuous signal phases that can cause problems in many
systems.
In order to reduce the amount of jumps, a large number of con-
I. INTRODUCTION trol bits are required with digitally controlled VGAs. Therefore,
for applications that require smooth gain transitions, the VGAs
ARIABLE gain amplifiers (VGAs) can be found in many controlled by analog signal are preferred. The VGAs controlled
V applications and are used to maximize the dynamic range
of overall systems in medical equipments, telecommunication
by analog signals typically adopt variable transconductance or
resistance stages for gain variation as shown in Fig. 1(b). With
systems, hearing aids, disk drives, and others [1]–[5]. In disk these topologies, the gains can be controlled continuously, but
drives and CCD imaging equipments, the VGAs play the impor- obtaining a wide exponential gain variation as a function of
tant role of stabilizing the amplitude of the output signal under control voltage is a big issue, especially in CMOS technology.
various conditions and supply a constant-amplitude signal to In recent CMOS-based analog VGA designs, decibel linear
the detector and filter sections of the read channel. The VGA gain variation characteristics are realized by the circuit imple-
for these applications requires a gain variation range of more mentations of pseudo-exponential [1]–[4] and Taylor series ap-
than 30 dB. In communication systems, the VGA is normally proximation functions [5]. The CMOS-based VGAs that adopt
employed in a feedback loop to implement an automatic gain these functions offer less than 15 dB of gain variation with a
control (AGC) amplifier. The AGC amplifier is a circuit that au- linearity error of less than 0.5 dB [1]–[5]. Another analog
tomatically controls its gain in response to the amplitude of the VGA that adopts the signal-summing technique using the Gibert
input signal, leading to a constant-amplitude output. The gain cell is reported in [6]–[8], which offers high-frequency opera-
as an exponential function of control voltage, which is not an tion, low noise, and low distortion. However, the amount of gain
easily obtainable characteristic in CMOS technology, is desir- variation for this technique is limited to less than 20 dB, and
able for minimizing the settling time of the AGC loops. More- the linearity error is significant [6], [7]. An effective solution
over, code-division multiple-access (CDMA) systems require to achieve a wide exponential gain variation is adopting bipolar
VGAs with high linearity and wide range of gain variation. transistors [9], but this requires a higher amount of power dis-
As an all-CMOS implementation, there are two approaches sipation and is not compatible with standard CMOS technology
used to realize VGAs depending on whether the control signal [9]. The VGAs can be implemented in BiCMOS technology, but
is digital or analog. The digitally controlled VGAs use a series of it is not a cost-effective solution.
switchable resistors or switched-capacitor techniques to control In cellular wireless communication systems, the amplitude
gain as shown in Fig. 1(a). In digitally controlled VGAs, gain of the receiver and transmitter signals varies greatly. For this
varies as a discrete function of the control signal, which can lead reason, for example, in a CDMA system, the transceiver requires
at least 80 dB of dynamic gain variation and splits into RF and
Manuscript received July 21, 2005; revised February 13, 2006. This work
IF/baseband stages. In a typical receiver, most of the gain varia-
was supported in part by MOST/KOSEF (Intelligent Radio Engineering Center)
under the SRC/ERC Program. This paper was recommended by Associate Ed- tion is assigned to the baseband stage. Therefore, to cover such a
itor J. S. Chang. wide dynamic range, conventional CMOS-based VGAs require
The authors are with the School of Engineering, RFME Laboratory, In- at least 4 or 5 gain-varying stages. The multiple gain-varying
formation and Communications University, Daejeon 305-714, Korea (e-mail:
[email protected]; [email protected]; [email protected]; [email protected]). stages lead to a higher amount of power dissipation, larger chip
Digital Object Identifier 10.1109/TCSI.2006.879058 area, and higher cost.
1057-7122/$20.00 © 2006 IEEE

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 DUONG et al.: A 95-DB LINEAR LOW-POWER VGA 1649

Fig. 2. Decibel scale plots of (1), (2), and the ideal exponential function. Fig. 3. Decibel scale plots of (3) for various values of k .

This paper reports a new analog VGA topology that can pro-
vide a very wide gain variation. The paper is outlined as fol-
lows. Section II describes the limitations of conventional decibel
linear functions and compares them with the new function pro-
posed by the authors in [10]. Section III introduces the circuit
implementation of the VGA that adopts the new approximated
exponential function. Section IV describes the measurement re-
sults of the proposed VGA, and Section V concludes.

II. DECIBEL LINEAR FUNCTIONS

The pseudo-exponential and Taylor series approximation
functions used for VGA designs are given, respectively, by [3] Fig. 4. Circuit schematic of the control stage.

(1)
the decibel linear range of (3) extends to more than 60 dB with
a linearity error of less than 0.5 dB for (solid line),
which is a significant improvement compared to (1) and (2).
Since the long-channel CMOS transistors provide a
(2)
square-law characteristic in the saturation region, and the
where is a constant and an independent variable. The plots of numerator and denominator of (3) are all second-order func-
(1), (2), and the ideal exponential function in decibel scale as a tions, (3) can easily be implemented in CMOS technology.
function of are shown in Fig. 2. Equations (1) and (2) approx- Therefore, considering the amount of decibel linear range, the
imate the exponential function when . Otherwise, (1) VGA that adopts (3) can achieve more than 60 dB of gain
and (2) deviate significantly from the ideal exponential function. variation in one stage, leading to the reduction of the gain
As can be seen in Fig. 2, (1) and (2) provide less than 15- and stages while still satisfying the required dynamic gain range.
12-dB linear range with a linearity error of less than 0.5 dB. Consequently, the lower power dissipation and smaller chip
Therefore, the decibel linear gain variations of the VGAs which size (or cost) characteristics are obtained.
adopt (1) and (2) are limited by the same extents [1]–[5]. Due
to the wider range of decibel linear variation, the pseudo-expo-
III. VGA DESIGN
nential function is more frequently adopted for VGA designs
[1]–[4].
Compared to (1) and (2), the new approximated exponential A. Control Circuit Block
function, proposed by the authors in [10], is given by
Fig. 4 shows a control circuit that generates the numerator
and the denominator of (3), where all transistors are assumed
to operate in saturation mode. In Fig. 4, the body terminals of
(3) pMOS and nMOS transistors are tied to supply voltages
and , respectively, and the lengths of transistors and
where is a constant. The numerator and denominator of (3) are chosen long enough that the channel length modulation can
are squaring functions of the variable . For less than unity, be neglected. In Fig. 4, to guarantee the saturation-mode opera-
the decibel linear range of (3) extends drastically and reaches its tion of transistors and , the control voltage must stay
maximum value at around . As can be seen in Fig. 3, within a range of ( , where

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 1650 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 8, AUGUST 2006

and are the threshold voltages of nMOS and pMOS tran-

sistors, respectively. The drain currents of transistors and
in Fig. 4 can be given as
(4)
(5)
where and are constants and
]. In Fig. 4, since the currents and
are and , respectively, the resulting currents
and , after some mathematical manipulations, can be
given by

(6)
Fig. 5. Circuit schematic of the I generator.

is shown in Fig. 5 [11]. From Fig. 5, the bias current is

(7) given as [11]

Assuming , and (9)

, from (6) and (7), the ratio of , can be
given by
where represents the multiplication factor in Fig. 5. As can
be seen in (9), is a strong function of the external resistor .
(8)

B. Amplifier Block
As can be seen from (8), the current ratio , which is a
function of the control voltage , is equivalent to (3) by sub- Fig. 6 shows the circuit schematic of the amplifying block that
stituting and . is adopted for the proposed VGA, including the common-mode
Therefore, if one can develop a circuit that utilizes the ratio of feedback circuit. In Fig. 6, the amplifier consists of an input
currents and in Fig. 4, a VGA that provides a very wide source-coupled pair ( and ) and diode-connected loads
decibel linear gain variation can be obtained. ( and ). The sizes of and are equal to
Equation (8) is obtained by assuming , while and , respectively. In Fig. 6, the two currents and
stays within the range of . from the control block in Fig. 4 are mirrored to and .
For the case when , if and Therefore, the differential gain of the VGA shown in Fig. 6 can
are shifted by and become and be expressed as
0 V, respectively, then the control voltage stays between
and . In this case, the relation between
and shown in (8) is still maintained. The proposed (10)
control circuit shown in Fig. 4 is compact, leading to low power
consumption. It requires only one control signal , which is a where is the transconductance of the input transistors
preferred choice for simple operation of VGAs. ( and ) and the transconductance of the diode
The VGA that adopts (8) shows a wide range of gain varia- connected transistors ( and ), respectively. Note that the
tion; however, the required dynamic gain range for different ap- decibel linear characteristic of in (10) is nearly
plications is not equal; therefore, if the VGA provides a wider equal to that of due to the approximated exponential
range of gain variation than the requirement, then the range of behavior of (8). From (8) and (10), the differential gain as a
the control signal is reduced. Consequently, in order to maxi- function of the control voltage is given by
mize the range of control signal, the gain variation range of the
VGA should be controllable. In (8), varying the bias current
or the transistor size has the effect of varying the constant
in (3), which leads to different ranges of gain variation. In this
paper, is chosen as it is easier to control by an external com-
ponent, for example, a resistor. The bias circuit for generating (11)

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 DUONG et al.: A 95-DB LINEAR LOW-POWER VGA 1651

Fig. 6. Circuit schematic of the amplifying stage. Fig. 7. Block diagram of the proposed two-stage VGA.

From (11), by adjusting the bias current , the amplifying block input capacitance and resistance. Due to the Miller effect, the
in Fig. 6 can provide more than 60 dB of gain variation, which input capacitance is proportional to the amplifier gain; therefore,
corresponds to the case of in (3). As discussed pre- the bandwidth is reduced at higher gain settings. The output
viously, the in (11) can be adjusted by varying the external pole is proportional to the output capacitance and resistance.
resistance , which is equivalent to change in of (3). Conse- Since the resistance from the inter-stage node to the ac ground
quently, the amount of gain variation of the proposed VGA can is dominated by the diode-connected transistors and ,
be controlled by adjusting . which vary as a function of gain, the bandwidth of the amplifier
From Fig. 6, the amplifier gain can be varied by controlling varies accordingly. At higher gains, the current flowing through
the current through transistors and . Since the ampli- the diode-connected transistors is reduced leading to narrower
fier adopts current sources as active loads, the currents through bandwidths. Since the currents flowing through and
transistors and must also vary accordingly. From (8), are squaring functions of the control voltage, the bandwidth of
the sum of the currents through and is given as the proposed VGA varies significantly from low- to high-gain
modes.
The P1dB of the proposed VGA shown in Fig. 6 is now taken
(12) into account. In Fig. 6, the dc bias voltage to the gates of tran-
sistors is fixed, and the common-mode feedback circuit
forces the output dc voltage of the VGA to be , which is con-
which is a second-order polynomial of the control voltage . stant. The drain currents of the transistors , which
As a result, the drain currents through transistors and are bias currents of transistors , are functions of the
vary as a function of gain variation. Therefore, the strong control voltage . Therefore, the gate–source voltages of the
common-mode feedback circuit shown in Fig. 6 is required in transistors and in Fig. 6 are also functions of the
order to prevent any of the transistors from entering linear mode control voltage and respectively given as
operation and to maintain a specific dc value for the biasing of
the next stage.
Fig. 7 shows a block diagram of the overall VGA. The VGA
adopts two amplifying blocks in cascade so that more than 120
dB of gain variation can be achieved. In Fig. 7, the first and and
second VGAs use the same circuit shown in Fig. 6, and the
control stage uses the circuit shown in Fig. 4. The buffer in
Fig. 7 is added for the convenience of measurements, providing
high-input and 50- output impedances. Therefore, the buffer is Since the peak-to-peak (the swing) value of the input and output
designed as a differential source follower, in which the gates of signals in Fig. 6 is limited by the condition of saturation-mode
the input different transistors are differential inputs of the buffer operation of transistors , the allowable input swing
with high impedance while the output impedance can be ad- is dependent on the gain of the VGA, , and .
justed to 50 by a proper choice of the bias current and the size The larger allowable input and output signal swings leads to
of input different transistors of the buffer. better P1dBs. From (10) and (11), as increases and de-
Regarding the frequency response, assuming that the VGA creases, the gain decreases such that the allowable input swing
is evaluated under a 50- environment, the bandwidth of the is increased, leading to higher P1dB; nevertheless, is
VGA is dominated by the pole at the input and the inter-stage reduced such that the allowable swing of the output signal is re-
node between two amplifiers. The input pole is a function of the duced. When the allowable input swings defined by the gain is

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 1652 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 8, AUGUST 2006

Fig. 8. Plot of (14) for different values of threshold voltage of the nMOS and Fig. 9. Plot of (14) for process variations of K and K .\!
pMOS transistors.

Considering the process variation of the threshold voltage

equal to that defined by the , the maximum P1dB is ob-
, assuming that and , from the
tained. If the gain continues to decreases then decreases
numerical analysis, the overall gain curve as given in (14) is
such that the allowable input swing is reduced, leading to the re-
shifted to the negative or positive axis for ,
duction of the P1dB. Consequently, the P1dB shows a peaking
and , respectively. Fig. 8 shows the plot of (14)
characteristic.
for of 0.55/0.45 V and 0.45/0.55 V, respectively.
C. Design Consideration for Process Variation ( As shown in Fig. 8, the range of decibel linear gain variation
and ) is nearly constant. Consequently, the process variation of the
threshold voltage of the nMOS and pMOS transistors has al-
Note that (8) and (11) are obtained by assuming most no effect on the decibel linear gain variation of the pro-
, and . Practically, posed VGA.
the can be obtained by a proper choice of Considering the process variation of transistors and in
the aspect ratios of transistors and in Fig. 4; however, Fig. 4, the can be obtained by a proper choice
is usually different from such that (8) and (11) of the aspect ratios of transistors and . Moreover, transis-
should be reconsidered. From (6), (7), and (10), assuming that tors and are placed closely in the layout design, leading
and , the gain of the to the same process variation; therefore, the process variation of
proposed VGA can be given as the ratio is cancelled. Though the ratio varies by
%, only a few decibel deviations in the decibel linear gain
variation range are realized as shown in Fig. 9. Consequently,
the proposed VGA shows good robustness against process vari-
ation of transistor and .

(13) D. Design Consideration for Temperature Variations

In VGA designs, the gain is required to be temperature insen-
sitive in a wide range of temperature variations; for example,
Let in military applications, the gain should have minimal devia-
, and , tion over a temperature range from 30 C to 80 C. For sim-
(13) can be rewritten as plicity, assume that and
( and ); however, the analysis of the gain versus
temperature for these assumptions can be applied for the case
where and . In our CMOS technology,
the resistor , the mobility , and the threshold voltage
are decreasing functions of temperature. Consequently,
(14) from (9) and (14), and the coefficient are increasing
and decreasing functions of temperature, respectively. Let
where is a constant and does not affect the range and ,
of the decibel linear gain variation of the proposed VGA. As where and are constants at ,
shown in (14), for and and and the temperature variables; (14) can then be
, (14) has the same form of expression as (3), where rewritten as
can be achieved by adjusting the bias
current . The plot of (14) for and a typical value
of V is depicted in Fig. 8 by the solid
line, where more than 60 dB of decibel linear variation can be
obtained as previously discussed in Section II. (15)

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 DUONG et al.: A 95-DB LINEAR LOW-POWER VGA 1653

Fig. 10. Plot of (15) for temperature variation of the threshold voltage.

Fig. 12. Proposed bias circuit for temperature-independent gain.

Fig. 11. Plot of (15) for temperature variation of the threshold voltage and mo-
bilities.

In (15), the temperature variation of the threshold voltage

is first considered, where is assumed to be Fig. 13. Plot of gain for different temperatures of the proposed VGA that adopt
the bias circuit shown in Fig. 12.
independent of temperature . In (15), for a typical
value of V and V at 27 C,
then . As the temperature varies from from [18], and the output current of the PTC, , is given in
30 C to 80 C, in the given CMOS technology, the threshold (9). In Fig. 12, the bias current is given as
voltage can vary by an amount of less than 10% (i.e.,
0.45~0.55 V), which corresponds to from 0.909
( 80 C) to 1.111 ( 30 C). The plots of (15) for
(16)
30 C 80 C are depicted in Fig. 10. As shown in
Fig. 10, the temperature variation of the threshold voltage leads In (16), is proportional to temperature while is indepen-
to gain deviation from the conventional curve (solid curve), and dent of temperature; therefore, is a decreasing function of
the range of gain variation is also varied. temperature. Replace in (15) by and let
Now, considering the temperature variation of (15) where , then is a decreasing function of tem-
both and are functions of temperature. As previ- perature. As the temperature varies from 30 C to 80 C,
ously discussed, is proportional to temperature such that assuming that varies by 20% is from 1.2
is an increasing function of temperature, while is ( 30 C) to 0.8 ( 80 C)] and varies by 10%
a decreasing function. The ratio in the VGA design [ from 0.909 ( 30 C) to 1.111 ( 80 C)], the
can vary by an amount of %. The plots of (15) for % and plot of (15) for different temperatures is shown in Fig. 13. As
% variation of and , respectively, are shown in shown in Fig. 13, with the proposed bias circuit, the proposed
Fig. 11. As shown in Fig. 11, the proposed VGA shows a good VGA shows a good temperature-independent gain over a wide
temperature-independent characteristic in a small value of gain range of gain variation.
near 0 dB; otherwise, a large deviation of the gain curve over
temperature variation is realized. Consequently, the proposed E. Noise and Power Supply Rejection Analyses
VGA shows a poor temperature-independent gain characteristic. Considering the noise of the proposed VGA in Fig. 7, the
In this paper, a new bias circuit for the VGA is proposed to input-referred noise of the VGA is dominated by the noise of
get the temperature-independent gain characteristic. The bias the variable gain circuit shown in Fig. 6, and the noise of the
circuit is shown in Fig. 12, which consists of a temperature-in- control stage and the common-mode feedback circuit is typ-
dependent current (TIC), a proportional-to-temperature current ically negligible [11]. The noise components of the variable
(PTC), and a current subtraction circuit. The TIC is adopted gain circuit in Fig. 6 are illustrated in Fig. 14(a), where

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 1654 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 8, AUGUST 2006

Fig. 14. Noise sources of the variable gain circuit shown in Fig. 6.

and are input-referred noise voltage and current, respec- where and are a process-dependent constants of the
tively. In Fig. 14(a), the and thermal noises of transistors corresponding transistors on the order of V F [11]. As
are modeled as voltage sources in series with their gates and shown in (17), at the maximum gain, is maximized
current sources. Since the noise sources in the circuit are un- while is minimized such that the total input-referred
correlated, superposition of noise power quantities is possible, noise voltage as given in (17) is minimal (the lowest noise). As
and the source terminals of transistors cannot be the gain decreases, reduces while increases;
considered virtual ground, making it difficult to use the half-cir- thus, the total input-referred noise voltage as given in (17) in-
cuit concept. Thus, the effect of noise sources in each branch creases (higher noise). Consequently, the noise of the proposed
of the differential amplifier is derived individually as shown in VGA is a decreasing function of the gain.
Fig. 14(b), where the inputs are shorted together in order to cal- Considering the power-supply rejection ratio (PSRR) of the
culate the input-referred noise voltage. By reducing the circuit in proposed VGA in Fig. 6, the PSRR is defined as the gain from
Fig . 14(b) to (c) and calculating the input-referred noise voltage, the input to the output divided by the gain from the supply
the total input-referred noise voltage of the variable gain circuit to the output. The differential voltage gain from the input to
as shown in Fig. 14(a) can be given as output is given in (11). As shown in Fig. 6, a change in
the supply voltage results in the same change in the differential
output nodes so that ; thus the gain from the supply
to the differential outputs is zero. Consequently, the PSRR ap-
proaches infinity. Practically, the mismatch in the differential
pair decreases the PSRR.

IV. MEASUREMENT RESULTS

The two-stage VGA, shown in Fig. 7 where the control circuit
block adopts the bias current shown in Fig. 5, is fabricated in
0.18- m CMOS technology with the supply voltages
V and V. The threshold voltages of the nMOS
(17) and pMOS transistors in the given technology are about 0.4 V;
hence, the can vary from 0.4 to 1.4 V. Fig. 15 shows the

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 DUONG et al.: A 95-DB LINEAR LOW-POWER VGA 1655

Fig. 15. Measured gain of the proposed VGA versus control voltage V for
different values of R .
Fig. 17. Measured frequency response of the proposed VGA at different gain
settings (R = 1 k
).

Fig. 16. Measured gain versus V at temperatures of 27 C and 80 C.

Fig. 18. Measured P1 dB of the proposed VGA as a function of gain (R =1

measured gain versus control voltage at 20 MHz for the k
).
external resistor , and 1 k , respectively. In Fig.
15, for 1k , the VGA shows a maximum TABLE I
gain variation of 95 dB (from 52 to 43 dB) and 90-dB range OVERALL PERFORMANCE SUMMARY OF THE PROPOSED VGA
with a linearity error of less than dB, while dissipating an
average current of less than 3.6 mA. As shown in Fig. 15, for
and 0.5 k , the total amount of
gain variation reduces to 84 dB ( 48 to 36 dB) and 68 dB (
40 to 28 dB), respectively.
Fig. 16 shows the measured gain versus control voltage at
temperatures of 27 C and 80 C, respectively. As shown in
Fig. 16, the proposed VGA is strongly sensitive to temperature
variation. The maximum deviation of the gain from 27 C to 80
C is up to 6 dB.
The reduction in gain variation range, about 23 dB, compared
to the predictions in (3), is due to the shortcomings of the ampli- shown in Fig. 18, as the V, decreases, the
fier topology. From Figs. 4 and 6, as the control currents and allowable output swing is reduced, resulting in the reduction of
become too small or large, the transistors - enter P1dB.
subthreshold or linear mode operation, in which case (10) be- The microphotographs of the chip and layout of the proposed
comes invalid. VGA are shown in Fig. 19. The VGA, excluding bondpads, oc-
The frequency response of the proposed VGA at k cupies less than 0.4 mm . The overall VGA performance is sum-
is shown in Fig. 17. At a maximum gain of 43 dB, the measured marized in Table I and a comparison with other works is given
bandwidth of the VGA is 32 MHz. The bandwidth increases in Table II. As shown in Table II, the proposed VGA achieves
with reduction in gain. At a minimum gain of 52 dB, the 3-dB the best performance in terms of decibel linear gain variation,
bandwidth reaches its maximum value of 1.05 GHz. power consumption, and chip area.
The measured P1dB of the proposed VGA as a function of As shown in Fig. 16, by the control circuit block shown in
gain for 1 k is shown in Fig. 18, where P1dB varies Fig. 4 which adopts the bias current shown in Fig. 5, the pro-
from 17 to 48 dBm. As previously discussed, the P1dB is posed VGA is strongly sensitive to temperature variation. How-
maximized around of 0.9 and 1 V, and as the gain reduces, ever, if the bias circuit as shown in Fig. 12 is utilized in the
decreases so that decreasing the allowable input signal control circuit block, the proposed VGA shows a good tem-
swing results in the reduction of P1dB as shown in Fig. 18. Also perature-independent characteristic as previously discussed and

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 1656 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 8, AUGUST 2006

TABLE II
PERFORMANCE COMPARISON OF THE PROPOSED AND PREVIOUSLY REPORTED VGAs

(*) not found

Fig. 20. Simulated gain versus control signal at different temperatures of the
proposed VGA that adopt the bias circuit shown in Fig. 12.

decibel linear control range is utilized, so that fewer VGA stages

are needed to achieve wide dynamic gain range. Consequently,
chip size (or cost) and power consumption are reduced. The
VGA-composed of the two-stage amplifier, a control stage, and
a buffer-which implements the new exponential approximation
function, is reported. The proposed VGA also allows variation
in the amount of gain control range to enable its use in different
applications. The proposed VGA is implemented in 0.18- m
CMOS technology and shows overall gain variation of 95 dB
in two cascaded stages, and 90-dB linear range with a linearity
Fig. 19. (a) Microphotograph of chip (b) and layout of the proposed VGA. error of less than dB. The P1dB and 3-dB bandwidth vary
from dBm (32-MHz bandwidth at maximum gain) to
17 dBm (1.05 GHz bandwidth at minimum gain). The VGA
shown in Fig. 20. Fig. 20 shows the simulated gain versus con- dissipates an average current of 3.6 mA from a 1.8-V supply.
trol voltage at 30 C, 27 C, and 80 C of the two-stage VGA
that adopts the bias circuit shown in Fig. 12. As shown in Fig. 20, REFERENCES
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from 0.47 to 1.33 V, the maximum decibel gain deviation of the [2] W. M. Christopher, “A variable gain CMOS amplifier with exponential
VGA from 30 C to 80 C is less than 2.5 dB. gain control,” in Dig. Tech. Papers IEEE Symp. VLSI Circuits, 2000, pp.
146–149.
[3] P. Huang, L. Y. Chiou, and C. K. Wang, “A 3.3-V CMOS wideband
V. CONCLUSION exponential control variable-gain-amplifier,” in Proc. IEEE Int. Symp.
An all-CMOS VGA with a wide range of gain variation, Circuits Syst., May 1998, pp. I-285–I-288.
[4] M. M. Green and S. Joshi, “A 1.5-V CMOS VGA based on pseudo-
small chip size, and low-power consumption is proposed. differential structures,” in Proc. IEEE Int. Symp. Circuits Syst., May
The new exponential approximation function with a very wide 2000, pp. IV-461–IV-464.

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 DUONG et al.: A 95-DB LINEAR LOW-POWER VGA 1657

[5] C.-C. Chang, M.-L. Lin, and S.-I. Liu, “CMOS current-mode exponen- Quan Le (S’05) received the B.S. degree in physics
tial-control variable-gain amplifier,” Electron. Lett., vol. 37, no. 14, pp. and the M.S. degree in radio electronics from Hanoi
868–869, Jul. 2001. National University, Hanoi, Vietnam, in 1996 and
[6] W. M. C. Sansen and R. G. Meyer, “Distortion in bipolar transistor 2000, respectively. He has been working toward the
variable-gain amplifiers,” IEEE J. Solid-State Circuits, vol. SC-8, no. Ph.D. degree in electrical engineering since 2001
8, pp. 275–282, Aug. 1973. at the Information and Communications University
[7] W. M. C. Sansen and R. G. Meyer, “An integrated wideband variable- (ICU), Daejon, Korea.
gain amplifier with maximum dynamic range,” IEEE J. Solid-State Cir- From 1996 to 2001, he was with Vietnam Posts and
cuits, vol. SC-9, no. 8, pp. 159–166, Aug. 1974. Telecom (VNPT) and worked on new technologies
[8] S. Otaka, G. Takemura, and H. Tanimoto, “A low-power low-noise ac- in satellite communication. Since 2001, he has been
curate linear-in-dB variable-gain amplifier with 500-MHz bandwidth,” engaged in silicon-based RF integrated circuit design
IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1942–1948, Dec. 2000. for high-speed wireless and wired communication. His current research interests
[9] G. S. Sahota and C. J. Persico, “High dynamic range variable-gain am- include transceiver and clock and data recovery integrs for high-speed burst-
plifier for CDMA wireless applications,” in Proc. IEEE Int. Solid-State mode and continuous-mode optical communication.
Conf., 1997, pp. 374–375.
[10] Q.-H. Duong and S.-G. Lee, “CMOS exponential current-to-voltage
circuit based on newly proposed approximation method,” in Proc. IEEE
Int. Symp. Circuits Syst., May 2004, pp. II.866–II.868.
[11] Razavi, Design of Analog CMOS Integrated Circuits. New York:
McGraw-Hill, 2001, pp. 233–239, 377–381.
Chang-Wan Kim (S’05) was born in Dae-Gue,
[12] K.-J. Koh, Y.-S. Youn, and H.-K. Yu, “A gain boosting method at RF
frequency using active feedback and its application to RF variable gain Korea, in 1972. He received the B.S. degree in elec-
amplifier (VGA),” in Proc. IEEE Int. Symp. Circuits Syst., May 2002, tronics and telecommunication from Kyung-Pook
pp. III.89–III.92. National University, Daegu, Korea, in 1997, and
[13] T. Yamaji, N. Kanou, and T. Itakura, “A temperature-stable CMOS the M.S. degree in electrical engineering from the
Information and Communications University (ICU),
variable-gain amplifier with 80-dB linearly controlled gain range,”
IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 553–558, May 2002. Daejon, Korea, in 2003.
From 1997 to 2003, he worked as a RF Device De-
[14] M. Mostafa, H. Elwan, A. Bellaour, B. Kramer, and S. H. K. Embabi,
“A 110 MHz 70 dB CMOS variable gain amplifier,” in Proc. IEEE Int. sign Engineer at LG Information and Communica-
tions Ltd. He is now working toward the Ph.D. degree
Symp. Circuits Syst., May 1999, pp. 628–639.
[15] O. Watanabe, S. Otaka, M. Ashida, and T. Itakura, “A 380-MHz CMOS in RF microelectronics at the RFME Lab, ICU. Since
linear-in-dB signal-summing variable gain amplifier with gain com- the beginning of 2003 in ICU, he has been leading a ultrawideband transceiver
design project. His main research interests are RF transceiver front-end circuit
pensation techniques for CDMA systems,” in Dig. Tech. Papers IEEE
Symp. VLSI Circuits, 2002, pp. 136–139. design and system-level integration of transceivers.
[16] R. Gomez and A. A. Abidi, “A 50-MHz variable gain amplifier cell in 2
m CMOS,” in Dig. Tech. Papers IEEE Symp. Custom Integr. Circuits
Conf., 1991, pp. 9.4/1–9.4/3.
[17] Y. Fujimoto, H. Tani, M. Maruyama, H. Akada, H. Ogawa, and M.
Miyamoto, “A low-power switched-capacitor variable gain amplifier,”
IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1213–1216, Jul. 2004. Sang-Gug Lee (M’05) was born in Gyungnam,
[18] F. Fiori and P. S. Crovetti, “A new compact temperature-compensated Korea, in 1958. He received the B.S. degree in
CMOS current reference,” IEEE Trans. Circuits Syst. II, Expr. Briefs, electronic engineering from the Gyungbook Na-
vol. 52, no. 11, pp. 724–728, Nov. 2005. tional University, Korea, in 1981, and the M.S. and
[19] Q.-H. Duong, L. Quan, and S.-G. Lee, “An all CMOS 84-dB linear Ph.D. degrees in electrical engineering from the
low-power variable gain amplifier,” in Dig. Tech. Papers IEEE Symp. University of Florida, Gainesville, in 1989 and 1992,
VLSI Circuits, 2005, pp. 114–117. respectively.
In 1992, he joined Harris Semiconductor, Mel-
Quoc-Hoang Duong (S’05) was born in Bacninh, bourne, FL, where he was engaged in silicon-based
Vietnam, in 1978. He received the B.S. degree in elec- RF integrated circuit (IC) designs. From 1995 to
tronics and telecommunications from Hanoi Univer- 1998, he was with Handong University, Pohang,
sity of Technology, Hanoi, Vietnam, in 2001 and the Korea, as an Assistant Professor in the School of Computer and Electrical
M.S. degree from the Information and Communica- Engineering. Since 1998, he has been with the Information and Communi-
tions University (ICU), Daejeon, Korea, in 2004. He cations University, Daejeon, Korea, where he is now an Associate Professor.
is working toward the Ph.D. degree at RFME Labo- His research interests include the silicon technology-based (BJT, BiCMOS,
ratory, ICU. CMOS, and SiGe BICMOS) RF IC designs such as low-noise amplifier, mixer,
From 2002 to 2006, he was engaged in silicon tech- oscillator, and power amp. He is also active in high-speed IC designs for
nology-based analog circuit designs such as bias ref- optical communication such as the transimpedance amplifier (TIA), driver
erences, variable gain amplifier, automatic gain con- amp, limiting amp, clock and data recovery, and MUX/DEMUX.
trol, transimpedance amplifier (TIA), low–pass filter (LPF), and baseband trans-
ceiver. His current research interests include wakeup circuit for sensor networks
and buffer for LCD drivers.

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