UNIT 6

PIC 16F877A Microcontroller Core Features

6.1. Architecture:
Fig. 6.1 shows PIC 16F877A architecture.

Fig. 6.1 PIC 16F877A architecture

6.2. Functional Pin description:

OSC1/CLKI: Oscillator crystal or external clock input.
OSC1: Oscillator crystal input or external clock source input. ST buffer when configured in
RC mode; otherwise CMOS.
CLKI: External clock source input. Always associated with pin function OSC1
OSC2/CLKO: Oscillator crystal or clock output.
OSC2: Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.
CLKO: In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and
denotes the instruction cycle rate.
MCLR/VPP: Master Clear (input) or programming voltage (output).
MCLR: Master Clear (Reset) input. This pin is an active low Reset to the device.
VPP: Programming voltage input.
Port A: Port A is bidirectional I/O port.
RA0/AN0: Digital I/O or Analog input 0.
RA1/AN1: Digital I/O or Analog input 1.
RA2/AN2/VREF-/CVREF: Digital I/O or Analog input 2 or A/D reference voltage (Low)
input or Comparator VREF output.
RA3/AN3/VREF+: Digital I/O or Analog input 3 or A/D reference voltage (High) input.
RA4/T0CKI/C1OUT: Digital I/O – Open-drain when configured as output or Timer0 external
clock input or Comparator 1 output.
RA5/AN4/SS/C2OUT: Digital I/O or Analog input 4 or SPI slave select input or Comparator
2 output.
Port B: PORTB is a bidirectional I/O port. PORTB can be software programmed for internal
weak pull-up on all inputs.
RB0/INT: Digital I/O or External interrupt.
RB1: Digital I/O
RB2: Digital I/O
RB3/PGM: Digital I/O or Low-voltage ICSP programming enable pin.
RB4: Digital I/O
RB5: Digital I/O
RB6/PGC: Digital I/O or In-circuit debugger and ICSP programming clock.
RB7/PGD: Digital I/O or In-circuit debugger and ICSP programming data.
Port C: Port C is bidirectional I/O port.
RC0/T1OSO/T1CKI: Digital I/O or Timer1 oscillator output or Timer1 external clock input.
RC1/T1OSI/CCP2: Digital I/O or Timer1 oscillator input or Capture2 input, Compare2 output,
PWM2 output.
RC2/CCP1: Digital I/O or Capture1 input, Compare1 output, PWM1 output.
RC3/SCK/SCL: Digital I/O or Synchronous serial clock input/output for SPI mode
Synchronous serial clock input/output for I2C mode.
RC4/SDI/SDA: Digital I/O or SPI data in or I2C data I/O.
RC5/SDO: Digital I/O or SPI data out.
RC6/TX/CK: Digital I/O or USART asynchronous transmit or USART1 synchronous clock.
RC7/RX/DT: Digital I/O or USART asynchronous receive or USART synchronous data.
Port D: Port D is bidirectional I/O port or Parallel Slave Port when interfacing to a
microprocessor bus.
RD0/PSP0: Digital I/O or Parallel Slave Port data.
RD1/PSP1: Digital I/O or Parallel Slave Port data.
RD2/PSP2: Digital I/O or Parallel Slave Port data.
RD3/PSP3: Digital I/O or Parallel Slave Port data.
RD4/PSP4: Digital I/O or Parallel Slave Port data.
RD5/PSP5: Digital I/O or Parallel Slave Port data.
RD6/PSP6: Digital I/O or Parallel Slave Port data.
RD7/PSP7: Digital I/O or Parallel Slave Port data.
Port E: Port E is bidirectional I/O port.
RE0/RD/AN5: Digital I/O or Read control for Parallel Slave Port or Analog input 5.
RE1/WR/AN6: Digital I/O or Write control for Parallel Slave Port or Analog input 6.
RE2/CS/AN7: Digital I/O or Chip select control for Parallel Slave Port Analog input 7.
VSS: Ground reference for logic and I/O pins.
VDD: Positive supply for logic and I/O pins.
NC: These pins are not internally connected. These pins should be left unconnected.

Various Registers:
Fig. 6.2. shows various registers in PIC 16F877A.

Fig. 6.2. Various registers in PIC 16F877A

Status Register
The Status register contains the arithmetic status of the ALU, the Reset status and the bank
select bits for data memory. The Status register can be the destination for any instruction, as
with any other register. If the Status register is the destination for an instruction that affects the
Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared
according to the device logic. Furthermore, the TO and PD bits are not writable, therefore, the
result of an instruction with the Status register as destination may be different than intended.
For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the
Status register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only
BCF, BSF, SWAPF and MOVWF instructions are used to alter the Status register because
these instructions do not affect the Z, C or DC bits from the Status register.
Note: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction.

bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h-1FFh)
10 = Bank 2 (100h-17Fh)
01 = Bank 1 (80h-FFh)
00 = Bank 0 (00h-7Fh)
Each bank is 128 bytes.
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow, the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with
either the high, or low order bit of the source register.

OPTION_REG Register:
The OPTION_REG Register is a readable and writable register, which contains various control
bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also
as the prescaler), the external INT interrupt, TMR0 and the weak pull-ups on PORTB.
Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the
Watchdog Timer.
bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits

6.4. Memory organization:

6.4.1. Program Memory organization:
The PIC16F87XA devices have a 13-bit program counter capable of addressing an 8K word x
14 bit program memory space. The PIC16F876A/877A devices have 8K words x 14 bits of
Flash program memory, while PIC16F873A/874A devices have 4K words x 14 bits. Accessing
a location above the physically implemented address will cause a wraparound.
The Reset vector is at 0000h and the interrupt vector is at 0004h.

Fig. 6.3 shows PIC 16F877A Program Memory Map and Stack.
 Fig. 6.3 PIC 16F877A Program Memory Map and Stack

PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register which
is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are
indirectly writable through the PCLATH register. On any Reset, the upper bits of the PC will
be cleared. Fig. 6.4. shows two situations for the loading of the PC.

Fig. 6.4. Two situations for the loading of the PC.

The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0>
→ PCH). The lower example in the figure shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH<4:3> → PCH).

6.4.2. Data Memory organization:

The data memory is partitioned into multiple banks which contain the General Purpose
Registers and the Special Function Registers. Bits RP1 (Status<6>) and RP0 (Status<5>) are
the bank select bits. Each bank extends up to 7Fh (128 bytes). The lower locations of each bank
are reserved for the Special Function Registers. Above the Special Function Registers are
General Purpose Registers, implemented as static RAM. All implemented banks contain
Special Function Registers. Some frequently used Special Function Registers from one bank
may be mirrored in another bank for code reduction and quicker access.

General Purpose Register File:

The register file can be accessed either directly, or indirectly, through the File Select Register
(FSR).

Indirect Addressing, INDF and FSR Registers:

The INDF register is not a physical register. Addressing the INDF register will cause indirect
addressing. Indirect addressing is possible by using the INDF register. Any instruction using
the INDF register actually accesses the register pointed to by the File Select Register, FSR.
Reading the INDF register itself, indirectly (FSR = 0) will read 00h. Writing to the INDF
register indirectly results in a no operation (although status bits may be affected). An effective
9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (Status<7>)
as shown in Fig. 6.5.

Fig. 6.5. Direct/Indirect Addressing

6.4.3. Data EEPROM and Flash Program Memory:
The data EEPROM and Flash program memory is readable and writable during normal
operation (over the full VDD range). This memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the Special Function Registers. There are six
SFRs used to read and write this memory:
• EECON1
• EECON2
• EEDATA
• EEDATH
• EEADR
• EEADRH
When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and
EEADR holds the address of the EEPROM location being accessed. These devices have 128
or 256 bytes of data EEPROM (depending on the device), with an address range from 00h to
FFh. On devices with 128 bytes, addresses from 80h to FFh are unimplemented and will
wraparound to the beginning of data EEPROM memory. When writing to unimplemented
locations, the on-chip charge pump will be turned off.
When interfacing the program memory block, the EEDATA and EEDATH registers form a
two-byte word that holds the 14-bit data for read/write and the EEADR and EEADRH registers
form a two-byte word that holds the 13-bit address of the program memory location being
accessed. These devices have 4 or 8K words of program Flash, with an address range from
0000h to 0FFFh for the PIC16F873A/874A and 0000h to 1FFFh for the PIC16F876A/877A.
Addresses above the range of the respective device will wraparound to the beginning of
program memory.
The EEPROM data memory allows single-byte read and write. The Flash program memory
allows single-word reads and four-word block writes. Program memory write operations
automatically perform an erase-before write on blocks of four words. A byte write in data
EEPROM memory automatically erases the location and writes the new data (erase-before-
write).
The write time is controlled by an on-chip timer. The write/erase voltages are generated by an
on-chip charge pump, rated to operate over the voltage range of the device for byte or word
operations.
When the device is code-protected, the CPU may continue to read and write the data EEPROM
memory. Depending on the settings of the write-protect bits, the device may or may not be able
to write certain blocks of the program memory; however, reads of the program memory are
allowed. When code-protected, the device programmer can no longer access data or program
memory; this does NOT inhibit internal reads or writes.

EEADR and EEADRH:

The EEADRH:EEADR register pair can address up to a maximum of 256 bytes of data
EEPROM or up to a maximum of 8K words of program EEPROM. When selecting a data
address value, only the LSByte of the address is written to the EEADR register. When selecting
a program address value, the MSByte of the address is written to the EEADRH register and the
LSByte is written to the EEADR register. If the device contains less memory than the full
address reach of the address register pair, the Most Significant bits of the registers are not
implemented.
For example, if the device has 128 bytes of data EEPROM, the Most Significant bit of EEADR
is not implemented on access to data EEPROM.

EECON1 and EECON2 Registers:

EECON1 is the control register for memory accesses.

bit 7 EEPGD: Program/Data EEPROM Select bit

1 = Accesses program memory
0 = Accesses data memory
Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress.
bit 6-4 Unimplemented: Read as ‘0’
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during
normal operation)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
bit 1 WR: Write Control bit
1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read; RD is cleared in hardware. The RD bit can only be set
(not cleared) in software.
0 = Does not initiate an EEPROM read

Reading Data EEPROM Memory

To read a data memory location, the user must write the address to the EEADR register, clear
the EEPGD control bit (EECON1<7>) and then set control bit RD (EECON1<0>). The data is
available in the very next cycle in the EEDATA register; therefore, it can be read in the next
instruction. EEDATA will hold this value until another read or until it is written to by the user
(during a write operation). The steps to reading the EEPROM data memory are:
1. Write the address to EEADR. Make sure that the address is not larger than the memory size
of the device.
2. Clear the EEPGD bit to point to EEPROM data memory.
3. Set the RD bit to start the read operation.
4. Read the data from the EEDATA register.

Program for Data EEPROM Read:

BSF STATUS,RP1 ;
BCF STATUS,RP0 ; Bank 2
MOVF DATA_EE_ADDR,W ; Data Memory
MOVWF EEADR ; Address to read
BSF STATUS,RP0 ; Bank 3
BCF EECON1,EEPGD ; Point to Data ; memory
BSF EECON1,RD ; EE Read
BCF STATUS,RP0 ; Bank 2
MOVF EEDATA,W ; W = EEDATA
Writing to Data EEPROM Memory:
The steps to write to EEPROM data memory are:
1. If step 10 is not implemented, check the WR bit to see if a write is in progress.
2. Write the address to EEADR. Make sure that the address is not larger than the memory
size of the device.
3. Write the 8-bit data value to be programmed in the EEDATA register.
4. Clear the EEPGD bit to point to EEPROM data memory.
5. Set the WREN bit to enable program operations.
6. Disable interrupts (if enabled).
7. Execute the special five instruction sequence:
a. Write 55h to EECON2 in two steps (first to W, then to EECON2)
b. Write AAh to EECON2 in two steps (first to W, then to EECON2)
c. Set the WR bit
8. Enable interrupts (if using interrupts).
9. Clear the WREN bit to disable program operations.
10. At the completion of the write cycle, the WR bit is cleared and the EEIF interrupt flag
bit is set. (EEIF must be cleared by firmware.) If step 1 is not implemented, then
firmware should check for EEIF to be set, or WR to clear, to indicate the end of the
program cycle.

Program for DATA EEPROM WRITE:

BSF STATUS,RP1 ;
BSF STATUS,RP0
BTFSC EECON1,WR ;Wait for write
GOTO $-1 ;to complete
BCF STATUS, RP0 ;Bank 2
MOVF DATA_EE_ADDR,W ;Data Memory
MOVWF EEADR ;Address to write
MOVF DATA_EE_DATA,W ;Data Memory Value
MOVWF EEDATA ;to write
BSF STATUS,RP0 ;Bank 3
BCF EECON1,EEPGD ;Point to DATA memory
BSF EECON1,WREN ;Enable writes
BCF INTCON,GIE ;Disable INTs.
MOVLW 55h ;
MOVWF EECON2 ;Write 55h
MOVLW AAh ;
MOVWF EECON2 ;Write AAh
BSF EECON1,WR ;Set WR bit to begin write
BSF INTCON,GIE ;Enable INTs.
BCF EECON1,WREN ;Disable writes