B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.

SRIKANT

NUMBER SYSTEMS

NUMBER SYSTEM :- A number system is a code having an assigned symbol for each distinct magnitude. The
symbols are called “digits”. The number of digits in a number system will determine the base of the system. In all
number systems, the weight of a number depends on its relative position.

BASE or RADIX : - The base or radix of a number system is the total number of different digits or basic symbols
used in a number system. In the binary system we have 0 & 1 as digits , so the base or radix is 2. In the decimal
system we have 10 digits ie. 0 through 9, so the base or radix is 10.

BINARY SYSTEM : - This number system has a base or radix of 2. The symbols or digits used in this system are
0 & 1.

OCTAL SYSTEM : - This number system has a base or radix of 8. The symbols or digits used in this system are
0 through7.( 0, 1, 2, 3, 4, 5, 6, 7 )

DECIMAL SYSTEM :- This number system has a base or radix of 10. The symbols or digits used in this system are
0 through 9. ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 )

HEXA DECIMAL SYSTEM :- This number system has a base or radix of 16. The symbols or digits used in this
system are 0 through F. ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F )

CODE CONVERSIONS

(1) BINARY TO DECIMAL CONVERSION:-

(i) ( 101111 . 11010 )2 = ( ? )10

Integeral part : (101111 )2 = ( 1 25 ) + ( 0  24 ) + ( 1  23 ) + ( 1  22 ) + ( 1  21 ) + ( 1  20 )
= 32 + 0 + 8 + 4 + 2 + 1
= 47
ie. (101111 )2 = ( 47 )10

Fractional Part : (0.11010 )2 = ( 1 1/2 ) + ( 1 1/4 ) + ( 0 1/8 ) + ( 1  1/16 ) + ( 0 1/32 )

= 0.5 + 0.25 + 0 + 0.0625 + 0
= 0. 8125
ie. (0.11010 )2 = ( 0. 8125 )10

Thus ( 101111.11010 )2 = ( 47 . 8125 )10

(ii) ( 111010 . 101101 )2 = ( ? )10

Integeral part : (111010 )2 = ( 1 25 ) + ( 1  24 ) + ( 1  23 ) + ( 0  22 ) + ( 1  21 ) + ( 0  20 )
= 32 + 16 + 8 + 0 + 2 + 0
= 58
ie. (111010 )2 = ( 58 )10

Fractional Part : (0.101101 )2 = ( 1 1/2 ) + ( 0 1/4 ) + ( 1 1/8 ) + ( 1  1/16 ) + ( 0 1/32 ) + ( 0 1/64 )

= 0.5 + 0 + 0.125 + 0.0625 + 0 + 0.015625
= 0. 703125
ie. (0.101101 )2 = ( 0. 703125 )10

Thus ( 111010 . 101101 )2 = ( 58 . 703125 )10

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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

(2) OCTAL TO DECIMAL CONVERSION:-

(i) ( 457 . 245 )8 = ( ? )10

Integeral part :
(457)8 = ( 4 82 ) + ( 5  81 ) + ( 7  80 )
= 256 + 40 + 7
= 303
ie. (457)8 = ( 303 )10
Fractional Part :
(0.245 )8= ( 2 1/8 ) + ( 4 1/64 ) + ( 5 1/512 )
= 0.25 + 0.0625 + 0.0097656
= 0. 3222656
ie. (0.245)8 = (0. 3222656 )10

Thus ( 457.245)8 = ( 303 . 3222656 )10

(ii) ( 1427 . 3426 )8 = ( ? )10
Integeral part :
(1427 )8 = ( 1 83 ) + ( 4  82 ) + ( 2  81 ) + ( 7  80 )
= 512 + 256 + 16 + 7
= 791
ie. (1427)8 = ( 791)10

Fractional Part :
(0.3426 )8 = ( 3 1/8 ) + ( 4 1/64 ) + ( 2 1/512) + ( 6  1/4096 )
= 0.375 + 0.0625 + 0.00391 + 0.001465
= ( 0. 442875 )10
ie.(0.3426)8 = ( 0.442875)10

Thus ( 1427 . 3426 )8 = ( 791 . 442875 )10

(3) HEXADECIMAL TO DECIMAL CONVERSION :-

(i) ( F9AC . 5D8B )16 = ( ? )10
Integeral part :
(F9AC)16 = ( F 163) + ( 9 162 ) + ( A  161 ) + ( C 160 )
= ( 15 163) + ( 9 162 ) + ( 10  161 ) + ( 12 160 )
= 61440 + 2304 + 160 + 12
= 63916
ie. (F9AC)16 = ( 63916 )10

Fractional Part :
(0.5D8B )16= ( 5 1/16) + ( D 1/162 ) + ( 8 1/163 ) + ( B 1/164)
= 0.3125 + 0.051 + 0.00195 + 0.000168
= ( 0. 36562 )10
ie. (0.5D8B )16 = ( 0. 36562 )10
Thus (F9AC . 5D8B)16 = ( 63916 . 36562 )10

(ii) ( 9EA6 . 2FA )16 = ( ? )10

Integeral part :
(9EA6)16 = ( 9 163 ) + ( E  162 ) + ( A  161 ) + ( 6 160 )
= ( 9 163) + ( 14 162 ) + ( 10  161 ) + ( 6 1 )
= 36864 + 3584 + 160 + 6
= 40614
ie. (9EA6)16 = ( 40614 )10

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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

Fractional Part :
(0.2FA )16 = ( 2 1/16) + ( F 1/162 ) + ( A 1/163 )
= ( 2 1/16 ) + ( 15 1/256 ) + ( 10 1/4096)
= 0.125 + 0.0586 + 0.00244
= 0. 18604
ie. (0.2FA )16 = ( 0. 18604 )10
Thus ( 9EA6 . 2FA )8 = ( 40614 . 18604 )10

(1) DECIMAL TO BINARY CONVERSION :-

(i) ( 47 . 8125 )10 = ( ? )2

Integeral part :

2 47 1
2 23 1
2 11 1
2 5 1 ie. ( 47 )10 = ( 101111 )2
2 2 0
1

Fractional Part :

( 0.8125  2 ) = 1.625  1
( 0.625  2 ) = 1.25  1 ie. ( 0 . 8125 )10 = ( 0.1101 )2
( 0.25  2 ) = 0.5  0
( 0. 5  2 ) = 1.0  1

Thus ( 47 . 8125 )10 = ( 101111 . 1101)2

(ii) ( 58 . 703125 )10 = ( ? )2

Integeral part :

2 58 0
2 29 1
2 14 0
2 7 1 ie. ( 58)10 = ( 111010 )2
2 3 1
1

Fractional Part :

( 0.703125  2 ) = 1.40625  1
( 0.40625  2 ) = 0.8125 0
( 0.8125  2 ) = 1.625 1 ie. ( 0 . 703125 )10 = ( 0 . 101101)2
( 0.625  2 ) = 1.25 1
( 0.25  2 ) = 0.5 0
( 0. 5  2 ) = 1.0 1

Thus ( 58 . 703125 )10 = (111010 . 101101)2

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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

(2) DECIMAL TO OCTAL CONVERSION :-

(i) ( 303 . 3222656 )10 = ( ? )8

Integeral part :

8 303 7
8 37 5 ie. ( 303)10 = ( 457)8
4

Fractional Part :
( 0.3222656  8 ) = 2.5781248  2
( 0.5781248  8 ) = 4.6249984 4
( 0.6249984  8 ) = 4.9999872 4 ie. ( 0 . 3222656 )10 = ( 0 . 244777 )8
( 0.9999872  8 ) = 7.9998976 7
( 0.9998976  8 ) = 7.9991808 7
( 0. 9991808  8 ) = 7.9934464 7

Thus ( 303 . 3222656 )10 = (457 . 244777 )8

(ii) ( 791 . 442875 )10 = ( ? )8

Integeral part :

8 791 7
8 98 2 ie. ( 791)10 = ( 1427)8
8 12 4
1

Fractional Part :
( 0.442875  8 ) = 3.543  3
( 0.543  8 ) = 4.344 4
( 0.344  8 ) = 2.752 2 ie. ( 0 . 442875 )10 = ( 0 . 342601 )8
( 0.752 8 ) = 6.016 6
( 0.016 8 ) = 0.128 0
( 0.128  8 ) = 1.024 1

Thus ( 791 . 442875 )10 = ( 1427 . 342601)8

(3) DECIMAL TO HEXADECIMAL CONVERSION :-

(i) ( 63916 . 36562 )10 = ( ? )16

Integeral part :

16 63916 12 C
16 3994 10 A
ie. ( 63916)10 = ( F9AC )16
16 249 9 9
15 F

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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

Fractional Part :
( 0.36562 16 ) = 5.84992  5  5
( 0.84992  16 ) = 13.59872  13  D
( 0.59872  16) = 9.57952  9  9 ie. ( 0 . 36562 )10 = ( 0.5D994 )16
( 0.57952  16 ) = 9.27232  9  9
( 0.27232  16 ) = 4.35712  4  4

Thus (63916 . 36562)10 = ( F9AC . 5D994 )16

(ii) ( 40614 . 18604 )10 = ( ? )16

Integeral part :

6 16 40614 6
A 16 2538 10
E ie. ( 40614) = ( 9EA6
16 10158 14)16 Fractional Part :
9 9 ( 0.18604  16 ) = 2.97664  2  2
( 0.97664  16 ) = 15.62624  15  F
( 0.62624  16) = 10.01984  10  A ie. ( 0 . 18604 )10 = ( 0 . 2FA05 )16
( 0.01984  16) = 0.31744  0  0
( 0.31744  16) = 5.07904  5  5

Thus ( 40614 . 18604 )10 = ( 9EA6 . 2FA05 )16

(1) OCTAL TO BINARY CONVERSION :-

(i) ( 457 . 245 )8 = ( ? )2

Integeral part :

( 457 )8 = 4 5 7
{ 100 101 111 }
= ( 100101111 )2
ie. ( 457 )8 = ( 100101111 )2
Fractional Part :

( 0.245 )8 = 2 4 5
{ 010 100 101 }
= ( 0. 010100101 )2
ie. ( 0.245 )8 = ( 0.010100101 )2

Thus ( 457 . 245 )8 = ( 100101111 . 010100101)2

(ii) ( 1427. 3426)8 = ( ? )2

Integeral part :

( 1427 )8 = 1 4 2 7
{ 001 100 010 111 }
= ( 1100010111 )2

ie. ( 1427)8 = ( 1100010111 )2

Fractional Part :

( 0. 3426)8 = 3 4 2 6

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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

{ 011 100 010 110 }

= ( 0. 01110001011)2
ie. ( 0.3426)8 = ( 0.01110001011 )2

Thus ( 1427 . 3426 )8 = (1100010111 . 01110001011)2

(2) HEXADECIMAL TO BINARY CONVERSION :-

(i) ( F9AC . 5D8B )16 = ( ? )2

Integeral part :
( F9AC )16 = F 9 A C
{ 1111 1001 1010 1100 } = ( 1111100110101100 )2

ie. ( F9AC)16 = ( 1111100110101100 )2

Fractional Part :

( 0 . 5D8B )16 = 5 D 8 B
{ 0101 1101 1000 1011 } = ( 0. 0101110110001011)2

Thus ( F9AC . 5D8B)16 = (1111100110101100 . 0101110110001011)2

(ii) ( 9EA6 . 2FA )16 = ( ? )2

Integeral part :

( 9EA6 )16 = 9 E A 6
{ 1001 1110 1010 0110} = ( 1001111010100110 )2

ie. ( 9EA6 )16 = (1001111010100110 )2

Fractional Part :

( 0 . 2FA)16 = 2 F A
{ 0010 1111 1010 } = ( 0. 001011111010)2

Thus ( 9EA6 . 2FA )16 = ( 1001111010100110 . 001011111010 )2

(1) BINARY TO OCTAL CONVERSION :-
(i) ( 100101111 . 010100101 )2 = ( ? )8

Integeral part :

( 100 , 101, 111 )2 = { 100 101 111 } = ( 457 )8

4 5 7
ie. ( 100101111 )2 = ( 457 )8

Fractional Part :-

( 0. 010, 100, 101 )2 = { 010 100 101 } = (245 )8

2 4 5
ie. ( 100101111 )2 = ( 0. 245 )8

Thus (100101111 . 010100101)2 = ( 457 . 245 )8

(ii) ( 1100010111 . 01110001011 )2 = ( ? )8

Integeral part :

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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

( 1, 100, 010, 111 )2 = { 001 100 010 111 } = ( 1427 )8

1 4 2 7
ie. ( 1100010111)2 = ( 1427 )8

Fractional Part :

(0. 011, 100, 010, 11)2 = { 011 100 010 110 } = ( 0. 3426)8
3 4 2 6
ie. ( 0.01110001011)2 = ( 0.3426 )8

Thus = (1100010111 . 01110001011)2 = ( 1427 . 3426 )8

(2) BINARY TO HEXADECIMAL CONVERSION :-

(i) (1001111010100110 . 001011111010)2 = ( ?)16

Integeral part :
( 1001111010100110)2 = { 1001, 1110, 1010, 0110 }
= ( 1001, 1110, 1010, 0110 )2
9 6
ie. ( 1001111010100110)2 = ( 9EA6 )16

Fractional Part :
( 0. 001011111010 )2 = { 0010, 1111, 1010, }
2
ie. ( 0. 001011111010 )2 = ( 0.2FA )16

Thus (1001111010100110 . 001011111010 )2 = ( 9EA6 . 2FA)16

(ii) ( 1111100110101100 . 010111011000101100 )2 = ( ?)16

Integeral part :
( 1111100110101100 )2 = { 1111, 1001, 1010, 1100 }
= ( 1111, 1001, 1010, 1100 )2
F 9 A C
ie. ( 1111100110101100 )2 = ( F9AC )16

Fractional Part :
( 0. 010111011000101100 )2 = { 0101, 1101, 1000, 1011, 0000 }
5 D 8 B 0
ie. ( 0. 010111011000101100 )2 = ( 0. 5D8B )16

Thus ( 1111100110101100 . 0101110110001011 )2 = ( F9AC . 5D8B)16

(1) HEXADECIMAL TO OCTAL CONVERSION :-

(i) ( F9AC . 5D8B )16 = ( ? )8
Integeral part :

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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

( F9AC )16 = F 9 A C
{ 1111 1001 1010 1100 } = ( 1111100110101100 )2

ie. ( F9AC)16 = ( 1, 111, 100, 110, 101, 100 )2

= ( 001, 111, 100, 110, 101, 100 )2 = 174654
1 7 4 6 5 4
ie. ( F9AC)16 = ( 174654 )8

Fractional Part :
( 0 . 5D8B )16 = 5 D 8 B

{ 0101 1101 1000 1011 } = ( 0 . 010, 111, 011, 000, 101, 100)2
= ( 010, 111, 011, 000, 101, 100 )2
2 7 3 0 5 4
= ( 0 . 273054 )8
ie. (0.5D8B ) = = ( 0 . 273054 )8
Thus ( F9AC . 5D8B)16 = (174654 . 273054)8

(ii) ( 9EA6 . 2FA )16 = ( ? )8

Integeral part :
( 9EA6 )16 = 9 E A 6
{ 1001 1110 1010 0110}

= (1001111010100110 )2

ie. ( 9EA6)16 = ( 1, 001, 111, 010, 100, 110 )2

= ( 001, 001, 111, 010, 100, 110 )2
1 1 7 2 4 6
= ( 117246 )8
ie. ( 9EA6)16 = ( 117246 )8
Fractional Part :
( 0 . 2FA)16 = 2 F A
{ 0010 1111 1010 }
= ( 0. 001011111010)2

= ( 0 . 001, 011, 111, 010)2

= ( 001, 011, 111, 010 )2
1 3 7 2
= ( 0 . 1372 )8
ie. ( 0 . 2FA)16 = ( 0 . 1372 )8
Thus ( 9EA6 . 2FA)16 = ( 117246 . 1372 )8

(2) OCTAL TO HEXADECIMAL CONVERSION :-

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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

(i) ( 174654 . 273054 )8 = ( ? )16

Integeral part :

( 174654 )8 = 1 7 4 6 5 4
{ 001 111 100 110 101 100 }
= ( 0000, 1111, 1001, 1010, 1100 )2
0 F 9 A C
ie. ( 174654 )8 = ( F9AC )16

Fractional Part :
( 0.273054 )8 = 2 7 3 0 5 4
010 111 011 000 101 100

= ( 0 . 0101, 1101, 1000, 1011, 0000 )

5 D 8 B 0
ie. ( 0.273054 )8= (0 . 5D8B0 )16

Thus (174654 . 273054)8 = ( F9AC . 5D8B )16

(ii) ( 117246 . 1372 )8 = ( ? )16

Integeral part :
( 117246 )8 = 1 1 7 2 4 6
{ 001 001 111 010 100 110 }

= (0000, 1001, 1110, 1010, 0110 )2

0 9 E A 6
ie ( 117246 )8 = ( 09EA6)16

Fractional Part :
( 0.1372 )8 = 1 3 7 2
001 011 111 010

= ( 0 . 0010, 1111, 1010, )

2 F A
ie. ( 0.1372 )8 = (0 . 2FA)16

Thus (117246 . 1372)8 = ( 9EA6 . 2FA )16

BINARY ARITHMETIC
(1) BINARY ADDITION :

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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

(i) Add ( 111011.1101 )2 and ( 11111 .011 )2

1 1 1 0 1 1 . 1 1 0 1 Augend
+ 0 1 1 1 1 1 . 0 1 1 0 Addend
1 0 1 1 0 1 1 . 0 0 1 1 Sum

(ii) Add ( 10110.1111 )2 and ( 1000111 .1101 )2

0 0 1 0 1 1 0 . 1 1 1 1 Augend
+ 1 0 0 0 1 1 1 . 1 1 0 1 Addend
1 0 1 1 1 1 0 . 1 1 0 0 Sum

(2) BINARY SUBTRACTION :

(i) Subtract ( 11111.011 )2 from ( 111011 .1101 )2

1 1 1 0 1 1 . 1 1 0 1 Minuend
 0 1 1 1 1 1 . 0 1 1 0 Subtrahend
1 1 1 0 0 . 0 1 1 1 Difference

(ii) Subtract ( 10110.1111 )2 from ( 1000111 . 1100 )2

1 0 0 0 1 1 1 . 1 1 0 0 Minuend
 0 0 1 0 1 1 0 . 1 1 1 1 Subtrahend
1 1 0 0 0 0 . 1 1 0 1 Difference

(3) BINARY MULTIPLICATION :

(i) Multiply ( 1110.110 )2 and ( 1010 .010 )2

Multiplicand Multiplier
1 1 1 0 . 1 1 0  1 0 1 0 . 0 1 0
0 0 0 0 0 0 0
1 1 1 0 1 1 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0 Partial products
1 1 1 0 1 1 0
0 0 0 0 0 0 0
1 1 1 0 1 1 0
1 0 0 1 0 1 1 1 .0 0 1 1 0 0 Final Product

(ii) Multiply ( 1010.11 )2 and ( 111 .01 )2

Multiplicand Multiplier
1 0 1 0 . 1 1  1 1 1 . 0 1

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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

1 0 1 0 1 1
0 0 0 0 0 0
1 0 1 0 1 1 Partial products
1 0 1 0 1 1
1 0 1 0 1 1
1 0 0 1 1 0 1 .1 1 1 1 Final Product

(4) BINARY DIVISION:

(i) Divide ( 110001 )2 by ( 111 )2

111 Dividend
110001 111
Divisor 111 Quotient
01010
111
000111
111
000000 Remainder

(ii) Divide ( 10100.110 )2 by ( 11.101 )2

NOTE : { 10100.110  11.101 } is the same as {10100110  11101 }, therefore we can divide the numbers as
shown below :

Divisor
11101 10100110 101.1011 Quotient
Dividend
11101
0110010
11101
000101010
11101
00000110100
11101
000000101110
11101
000000010001 Remainder

BINARY SUBTRACTION USING COMPLEMENTARY NUMBERS

(1) BINARY SUBTRACTION USING 1’s COMPLEMENT :

1’s COMPLEMENT : The 1’s complement of any binary number is obtained by subtracting every binary digit
from 1 , for example , the 1’s complement of the number 11011 is obtained as follows :
( 11111  11011 ) = 00100, therefore the 1’s complement of (11011) 2 is (00100)2.

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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

The 1’s complement is also obtained by complementing every digit of the given binary number, ie. The 1’s
complement of the number ( 11111 )2 is ( 00000 )2 & vice versa the 1’s complement of ( 00000 ) 2 is ( 11111 )2
Negative numbers can be represented by 1’s complement numbers, hence the process of subtraction in a processor can
be carried out using an adder unit instead of a subtractor unit, as a result it minimizes the hardware in a computer.

(i) Subtract 25 from 45

45 binary equivalent is : 101101 write the positive number as it is

 25 binary equivalent is : 011001 write the 1’s complement of the negative number
20

ie. 45 binary equivalent is : 1 0 1 1 0 1

 25 1’s complement is :  1 0 0 1 1 0
20 1 0 1 0 0 1 1
since carry is generated, it has to be taken as
end-around carry as shown below :

1 0 1 1 0 1
 1 0 0 1 1 0
1 0 1 0 0 1 1
 1 end-around carry
0 1 0 1 0 0 = 20

(ii) Subtract 15 from 31

31 binary equivalent is : 11111 write the positive number as it is

 15 binary equivalent is : 01111 write the 1’s complement of the negative number
16

ie. 31 binary equivalent is 1 1 1 1 1

 15 1’s complement is  1 0 0 0 0
16 1 0 1 1 1 1
since carry is generated, it has to be taken as
end-around carry as shown below :

1 1 1 1 1
 1 1 0 0 1
1 0 1 1 1 1
 1 end-around carry
1 0 0 0 0 = 16

(iii) Subtract 31 from 15

15 binary equivalent is : 01111 write the positive number as it is

 31 binary equivalent is : 11111 write the 1’s complement of the negative number
 16

ie. 15 binary equivalent is 0 1 1 1 1 since carry is not generated, complement the

 0 0 0 0 0 result & attach a negative sign as shown below
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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

 31 1’s complement is
 16 = ( 10000) = ( 16 )

(iv) Subtract 45 from 25

25 binary equivalent is : 011001 write the positive number as it is

 45 binary equivalent is : 101101 write the 1’s complement of the negative number
 20

ie. 25 binary equivalent is 0 1 1 0 0 1 since carry is not generated, complement the

 45 1’s complement is  0 1 0 0 1 0 result & attach a negative sign as shown
 20 1 0 1 0 1 1 = ( 010100) = ( 20 )

(1) BINARY SUBTRACTION USING 2’s COMPLEMENT :

2’s COMPLEMENT : The 2’s complement of any binary number is obtained by adding 1 to the 1’s
complement , for example , the 2’s complement of the number 11011 is obtained as follows :
The 1’s complement of (11011)2 is (00100)2 , the 2’s complement is obtained by adding 1 to (00100)2 , ie.
(00100  1)2 = (00101)2
The 2’s complement is also obtained by writing the LSB of the given binary number as it is and complementing the
rest of the digits . For example the 2’s complement of ( 11011 ) 2 is ( 00101 )2 . If the LSB is not a 1 but a 0 then all
these initial 0’s are retained unchanged & then the first 1 that is encountered is kept unchanged & the rest of the bits
are complemented. For example the 2’s complement of ( 1101100 ) 2 is ( 0010100 )2
Subtraction can be carried out through addition by using 2’s complement numbers, hence subtraction in a processor
can be carried out using an adder unit instead of a subtractor unit, as a result it minimizes the hardware in a computer.
However the advantage of using 2’s complement is that during the process of subtraction whenever a carry is
generated , it need not be used as end-around carry but has to be just neglected. This means that the subtraction
process using complementary numbers becomes simple. When a carry is not generated the resultant umber will be a
negative number.

(i) Subtract 25 from 45

45 binary equivalent is : 101101 write the positive number as it is

 25 binary equivalent is : 011001 write the 2’s complement of the negative number
20

ie. 45 binary equivalent is : 1 0 1 1 0 1

 25 2’s complement is:  1 0 0 1 1 1
20 1 0 1 0 1 0 0
since carry is generated, it has to be
neglected & result is taken as shown below
ie. ( 010100 )2 = ( 20 )10
(ii) Subtract 15 from 31

31 binary equivalent is : 11111 write the positive number as it is

 15 binary equivalent is : 01111 write the 1’s complement of the negative number
16

ie. 31 binary equivalent is 1 1 1 1 1

 1 0 0 0 1
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 15 2’s complement is
16
since carry is generated, it has to be
neglected & result is taken as shown below
ie. ( 10000 ) 2 = ( 16 )10

(iii) Subtract 31 from 15

15 binary equivalent is : 01111 write the positive number as it is

 31 binary equivalent is : 11111 write the 2’s complement of the negative number
 16

ie. 15 binary equivalent is 0 1 1 1 1 since carry is not generated, complement the

 31 2’s complement is resultant number, add 1 to it & attach a
 0 0 0 0 1
negative sign as shown below
 16 1 0 0 0 0 Resultant number
ie. Resultant number is( 10000) & the answer will be complement of the resultant number plus 1 , with a negative
sign,
ie. ( 01111  1)2 = ( 10000 )2 = ( 20)10

(iv) Subtract 45 from 25

25 binary equivalent is : 011001 write the positive number as it is

 45 binary equivalent is : 101101 write the 1’s complement of the negative number
 20

ie. 25 binary equivalent is 0 1 1 0 0 1 since carry is not generated, complement the

 45 2’s complement is  0 1 0 0 1 1 resultant number, add 1 to it & attach a
negative sign as shown below
 20 1 0 1 1 0 0
Resultant number
ie. Resultant number is( 101100 ) & the answer will be complement of the resultant number plus 1 , with a negative
sign,
ie. ( 010011  1)2 = ( 010100)2 = ( 20)10

LOGIC GATES
(1) OR-GATE :- Figure shows the logic circuit of a 2 input OR gate. The 2 inputs result in 4 input combinations of
0s & 1s. The operating conditions of the 4 combinations is summarized in the following truth table :-
A B Y = (AB) Logic symbol for OR Gate
0 0 0 Input A = Logic 0 or 1
0 1 1 A Input B = Logic 0 or 1
1 0 1
Y = (A+B)
B
1 1 1 Logic – 0 = 0 Volt
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The OR operation is represented by the operator “ + ” Logic – CDGI,
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(2) AND-GATE :- Figure shows the logic circuit of a 2 input AND gate. The 2 inputs result in 4 input
combinations of 0s & 1s. The operating conditions of the 4 combinations is summarized in the following truth table :-
A B Y = (A . B) Logic symbol for AND Gate :
0 0 0
Input A = Logic 0 or 1
0 1 0 A Input B = Logic 0 or 1
Y = (A . B)
1 0 0 B
1 1 1 Logic – 0 = 0 Volt
Logic – 1 = 5 Volts
The AND operation is represented by the operator “ . ”

(3) NOT-GATE :- Figure shows the logic circuit of a NOT gate (Inverter). It is single input circuit in which the
output is a complement of the input ie. if the input is logic-1 the output will be logic-0 & vice versa. As it has a single
input, there are only two possible inputs 0 & 1.The NOT gate operation is explained for these two input combinations.
A Y = (A)’ Logic symbol for NOT Gate : Input A = Logic 0 or 1
0 1
A Y = (A)’
1 0 Logic – 0 = 0 Volt
The NOT operation is represented by the operator “ ’ ” Logic – 1 = 5 Volts

(4) NAND-GATE :- Figure shows the logic circuit of a 2 input NAND gate. A 2-input NAND gate is realised using
an AND gate & a NOT gate. It is actually a combination of a two input AND Gate & a NOT Gate as shown in the
logic circuit. It is also called a Negated AND gate (AND gate followed by a NOT gate). The logic symbol for a
2-input NAND gate is also shown along with the truth table .
A B Y=A. B Y = (A . B)’ A (A.B)
0 0 0 1 Y = (A . B)’
B Input A = Logic 0 or 1
0 1 0 1 Input B = Logic 0 or 1
1 0 0 1
1 1 1 0 A Logic – 0 = 0 Volt
Y = (A . B)’ Logic – 1 = 5 Volts
B

(5) NOR-GATE :- Figure shows the logic circuit of a 2 input NOR gate. A 2-input NOR gate is realised using an
OR gate & a NOT gate. It is actually a combination of a two input OR Gate & a NOT Gate as shown in the logic
circuit. It is also called a Negated OR gate (OR gate followed by a NOT gate). The logic symbol for a 2-input NOR
gate is also shown along with the truth table .
A B Y = A+B Y = (A+B)’ A (A+B)
Y = (A+B)’
0 0 0 1 B Input A = Logic 0 or 1
0 1 1 0 Input B = Logic 0 or 1
1 0 1 0
1 1 1 0 A Logic – 0 = 0 Volt
Y = (A+B)’
B Logic – 1 = 5 Volts

(6) EXCLUSIVE-OR GATE[ EX-OR GATE ] :- The Exclusive-OR gate can be derived using the basic gates
ie. AND, NOT & OR gates, or the universal gates ie. NAND or NOR gates. The basic gate realisation for a 2-input
EX-OR gate along with the logic symbol & truth table is as shown.
A B Y = (A B) A (A’. B)
0 0 0
B
0 1 1
A
1 0 1 Y = (AB) Y = (A’. B +A. B’)
1 1 0 B
A
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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

The EX-OR operation is represented by the operator “” & output equation is given by : Y = AB = (A’.B+A.B’)
(7) EXCLUSIVE NOR – GATE [ Ex – NOR GATE ]:-

A A (AB)
Y = (AB)’ = (A B) Y = (AB)’ = (A B)
B B
A B Y = (A B) Y = (A B)’ =(AB)
Figure shows the logic symbol of a 2 input EX-NOR gate .It is a
0 0 0 combination of a two input EX-OR Gate & a NOT-Gate. It is
1
also called a Negated EX-OR gate (EX-OR gate followed by a
0 1 1 0
NOT gate). The realization of a 2-input EX-NOR gate using an
1 0 1 0 EX-OR gate & a NOT gate along with the truth table is also
1 1 0 1 shown .
The EX-NOR operation is represented by the operator “ ”
The output equation is given by : Y = AB = (A.B+A’.B’)
DE MORGAN’S THEOREM : Statement of De Morgan’s Theorem :

I theorem : The complement of the sum is equal to the product of the complements.
ie. ( A+B)’ = (A’ . B’ )

II theorem : The complement of the product is equal to the sum of the complements.
ie. ( A.B)’ = (A’ + B’ )

Note : Here the sum & product refer to the Boolean sum & product ie. OR & AND respectively

Proof of De Morgan’s I Theorem :

A B (A+B) (A+B)’ A’ B’ (A’ . B’)

0 0 0 1 1 1 1
Since entries in the two columns shown
0 1 1 0 1 0 0
are identical, the theorem is proved
1 0 1 0 0 1 0
1 1 1 0 0 0 0
IDENTICAL

Proof of De Morgan’s II Theorem :

A B (A.B) (A.B)’ A’ B’ (A’+ B’)

0 0 0 1 1 1 1
Since entries in the two columns shown
0 1 0 1 1 0 1
are identical, the theorem is proved
1 0 0 1 0 1 1
1 1 1 0 0 0 0
IDENTICAL

UNIVERSAL LOGIC GATES :- A universal logic gate can be used to realize all the basic & derived gates (ie.
OR, AND, NOT etc.) . Practically it is observed that NAND & NOR gates function as universal gates ie. it is possible
to realize all basic & derived gates using NAND & NOR gates.

(1) NAND – GATE AS UNIVERSAL GATE :-

(i) Realisation of NOT gate :-

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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

A Y = (A)’ Y = (A . A)’ =(A)’

(ii) Realisation of AND gate :-

(A.B)’
A
Y = (A.B) Y = [(A . B)’]’ = (A . B)
B

(iii) Realisation of OR gate :-

A’
A

Y = (A+B) Y = (A’. B’)’ = (A +B)

B
B’
(iv) Realisation of Ex – OR gate :-
(A.B’)’

Y = (AB) Y = (A. B’)+(A’.B)

(A’.B)’

(A.B’)’

Y = (AB) Y = (A. B’)+(A’.B)

(A.B’)’

(2) NOR – GATE AS UNIVERSAL GATE :-

(i) Realisation of NOT gate :-

A Y = (A)’ Y = (A +A)’ =(A)’

(ii) Realisation of OR gate :-

(A+B)’
A
Y = (A+B) Y = [(A +B)’]’ = (A +B)
B

(iii) Realisation of AND gate :-

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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

A’
A

Y = (A.B) Y = (A’+ B’)’ = (A . B)

B
B’
(iv) Realisation of Ex – OR gate :-

A (A+B)’
B
Y = (AB) Y = (A. B’)+(A’.B)
A A’

B (A’+B’)’
B’

(1) HALF ADDER :- It is a logic circuit used to add 2 one bit binary numbers. A half adder circuit has two
inputs & two outputs ( sum & carry ) . The addition of 2 bits can be shown using the following truth table :

A B SUM(S) CARRY(C) The logic circuit for a half adder is realized using the Boolean expression
0 0 0 0 obtained from the truth table :-
0 1 1 0 (i) Sum = S = (A’. B + A . B’) = ( A  B )
1 0 1 0 (ii) Carry = C = ( A . B )
1 1 0 1 The Half Adder circuit is therefore realized as shown below :

A B

SUM = S = (A’. B + A . B’) = ( A  B )

CARRY =C = (A . B )

(2) FULL ADDER :- The Half adder circuit can be used to add 2 one bit binary numbers effectively, but when
multi bit numbers are to be added then the carry bit that is generated should also be taken care of. This carry bit has to
be added to the existing two input bits, which means this circuit would require 3 inputs, ie. two input terminals to add
the actual input bits & an additional input terminal to handle the carry bit generated from the previous addition. This is
done using a Full adder circuit which is realized using 2 Half adders & a single OR – Gate as shown . The logic circuit
for a Full adder is realized using the Boolean expression obtained from the truth table which is shown:-
A A B C SUM(S) CARRY(C) (i) SUM = (A’.B’.C + A’. B.C’+A.B’.C’+A.B.C)
0 0 0 0 0 = (A.B’.C’+ A’. B.C’+A’.B’.C +A.B.C)
B
0 0 1 1 0 SUM = A B  C )
SUM= (( A
(ii) CARRY = (A’.B.C + A . B’.C+A.B.C’+A.B.C)
C0 1 0 1 0
= BC(A’+A) + A .B’.C+A.B.C’
0 1 1 0 1
1 0 0 1 0 = B.C + A.B’.C+A.B.C’ = B(C+C’.A)+A.B’.C
A.B = B(C+A)+A.B’.C = B.C + B.A + A .B’.C
1 0 1 0 1
1 1 0 0 1 = C(B+B’.A) + B . A = C.(B+A)+B.A
CARRY = A .B + B.C + C. A
1 1 1 1 1
The Full adder circuit is therefore realized as shown :
B.C CARRY = (A . B + B.C + C.A)

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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

A Full adder can also be realized using two half adders & a single 2 – input OR – gate as shown :

A Carry = (A.B)
HALF Carry = (A.B+B.C+C.A)
B ADDER-1
Sum = HALF Carry = (D.C) = (A  B). C
(A  B) =D ADDER-2
C
Sum = (A  B  C)
Sum = (D  C)

Figure below shows a Full adder realized using two half adders consisting of 2 input Ex-OR gates, 2-input AND gates
& a 2-input OR – gate :
HALF
ADDER-1

CARRY = (A.B + B.C + C.A)

A
B
SUM = ( A  B  C )
C

HALF
ADDER-2
R-S FLIP FLOP : A flip flop is a basic memory element ( data storage element ). A flip flop is realised using a group
of logic gates. A NAND gate or a NOR gate individually cannot act as a storage element but when two gates are cross
coupled with feed back then they can work as storage or memory elements. Such cross coupled NAND gates or NOR
gates with feedback are known as flip flops. A flip flop is a bistable electronic circuit that has two stable states , which
means the flip flop output will permanently remain either 0 (low) or 1(high) until it is forced to change its state by an
external trigger. A flip flop circuit will have two outputs, one is the Q output & the other is the Q’ output which will
always be the complement of the Q output , ie Q & Q’ are always complementary to each other. Flip flops can be
realised using two cross coupled inverters, hence we can use a NOR gate inverter or a NAND gate inverter as shown.
R
Q S R Q ( Output )
0 0 No Change # No Change or Last State or Memory State
0 1 0 ( Reset )
1 0 1 ( Set )
Q’
S
Dept. of E & C 1 1 Race 19 # Race or Invalid or Not Allowed ? State
or Indore
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B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

The truth table shown for a NOR gate inverter flip flop is similar to that of a transistor flip flop .
S
Q S R Q ( Output )
0 0 Race # Race or Invalid or Not Allowed or ? State
0 1 1 ( Set )
1 0 0 ( Reset ) # No Change or Last State or Memory State
Q’ 1 1 No Change
R
The truth table shown for a NAND gate inverter flip flop is the inverted form
of that shown for a NOR gate flip flop, hence inverters or steering gates are used to drive the inputs to the gates as
shown :

S’ S R Q ( Output )
S
Q 0 0 No Change # No Change or Last State or Memory State
0 1 0 ( Reset )
Steering
gates 1 0 1 ( Set ) # Race or Invalid or Not Allowed or ? State
1 1 Race
Q’
R
R’
The truth table shown for a NAND gate inverter flip flop with steering gates is similar to that shown for a transistor
flip flop, hence inverters or driving gates are used to realize the desired practical R-S flip flop.
In order to overcome the RACE problem in R-S flip flops the J-K flip flop is used.
CLOCKED R-S FLIP FLOP :

S S’
Q Clock S R Q ( Output )
X (0 or 1) 0 0 No Change X – Don’t Care Condition,
1 0 1 0 ( Reset ) ie. Clock is either 0 or 1
Clock
1 1 0 1 ( Set )
Q’ 1 1 1 Race
R R’
The clock signal is also known as the enabling signal which makes the logic circuit perform the required operation.If
clock = 0 then the logic circuit will not respond to the input signals ie. the circuit output will remain unaltered. Only
when the clock = 1( rising or falling edge ) the logic circuit is enabled & will respond to the applied input signals.
J-K FLIP FLOP : A J-K flip flop is realized using a clocked S-R flip flop and two AND gates with appropriate feed
back as shown in figure. The problem with the R-S flip flop is that it exhibits the RACE condition when both S & R
are high ie when both are logic-1. This condition is a logically unpredictable state. The J-K flip flop eliminates the
unpredictable condition that occurs in the S-R flip flop and hence can be practically used in logic circuits. The J input
is
willanalogous to theand
Set , ie. Q=1, S input
when&J=0
the&KK=1,
inputthe
is J-K
analogous to will
flip flop the RReset,
input.ie.
This means
Q=0. that when
As usual there J=1
will &
beK=0 , the J-K
no change in flip
the
output condition when J=K =0. However the most important change when compared to the S-R flip flop is that the
J-K flip flop will complement its output condition when J=K =1 with the clock high. The operation of a J-K flip can
be clearly understood from the truth table given below.

S=J.Q’
J S’
Q Input S = J . Q’
Input R = K . Q
Clock
Q’
K
R’
R=K.Q

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 B.E.E.E. (BE – 1004) UNIT-5 : BASIC ELECTRONICS Prof. K.SRIKANT

Realisation using S-R flip flop & AND gates Logic Symbol of J-K flip flop

Preset

J Q

Clock
Clk

K Q’

Clear

S= R= Output
Clk J K Qn Qn’ Remarks
J.Qn’ K.Qn (Qn+1)
1 0 0 0 1 0 0 0 = Qn ie. No Change or Last State or
1 0 0 1
0 1 0 0
Memory
1 0 1 0 1 0 0 0
=0, ie. Reset ( Make Q = 0 )
1 0 1 1 0 0 1 0
1 1 0 0 1 1 0 1
=1, ie. Set ( Make Q = 1 )
1 1 0 1 0 0 0 1
1 1 1 0 1 1 0 1 = Q n’ ie. Toggle or Complement or
1 1 1 1 0 0 1 0 Switch to opposite state
Q n represents the Present State ; Qn+1 represents the Next State ie. the state of the output after the clock
Race Around Condition in J-K Flip Flop : By using two AND gates & appropriate feed back the RACE problem
pulse is applied.
that existed in the S-R flip flop could be eliminated in a J-K flip flop. However there is a problem of an unpredictable
state occurring in the J-K flip flop also . Due to this problem the Q output will start oscillating between the 0 ( low) &
1 (high) states .The output condition therefore could be either 0 or 1. This problem is known as the Race around
Condition. The race around condition in a J-K flip flop occurs when J=1, K=1 and the clock is also =1, with the clock
pulse width “tp” greater than the propagation delay “t” of the gates. We assume that the inputs of the J-K flip flop do
not change during a clock pulse , but due to the feed back they change when the clock remains high (1), hence the
output condition starts oscillating between the low & high states. This problem can be avoided by making the clock
pulse width less than the propagation delay of the gates, but practically this is difficult because the propagation delay
is very small, hence the problem of Race Around Condition is overcome using a Master-Slave J-K flip flop. In this
flip flop the input conditions do not change when the clock remains high, hence the output does not oscillate.

Dept. of E & C 21 CDGI, Indore