SystemVerilog Introduction (1)

Presentation Objectives
• Provide a brief history and status update
of SystemVerilog as a HW Design &
Verification Language
• Provide a high level overview of the
language capabilities and usage aspects

This is not meant to be a tutorial of the language

Parts of this presentation are based on material which was presented
in DAC SystemVerilog workshop by technical committees chairs

SystemVerilog Introduction (2)

Agenda
• Background
– HW Design Languages
– Problem Statement
– IEEE P1800 Activity
• SystemVerilog Design Modeling
• SystemVerilog for Verification
– Extensions for Test-Bench Modeling
– Assertions
• SystemVerilog DPI
• A Quiz
• Conclusions

SystemVerilog Introduction (3)

 HW Design Languages
• Hardware Description Language (HDL) is used to
describe digital hardware elements
• Various levels of design abstractions are used:
– Behavioral: flow control, arithmetic operators, complex
delays
– Register Transfer Level (RTL): Structural description of
the registers and the signal changes between registers
– Gate level: combinatorial logic gates (and, or, not,…)
– Switch level: layout description of the wires, resistors
and transistors (CMOS,PMOS, etc)
• Two main subsets:
– Synthesizable – reflecting HW / Silicon
– Non-Synthesizable – reflecting instrumentation code

SystemVerilog Introduction (4)

 The Problem!
What’s Next?

Design Size
• Quest for Performance is driving up
complexity
– Deeper pipelines, increase in logic
functionality and complexity, power issues,
explosion in flops
Verilog RTL
• Explosion in lines of RTL Code making
verification a lot harder Schematics
• Low Abstraction level of the RTL is driving 80’s 90’s
higher verification effort and lower
simulation speed
– Trillions of cycles per lead project and Increasing rate

# Pre-silicon bugs
more pre-silicon bug escapes
• Verification effort is reaching 60% of the
total design cycle
– Usage of different languages makes it even
harder: reference models in C/C++, RTL in
Verilog or VHDL, Test Benches,
Assertions, Checkers, Coverage Lead Projects

SystemVerilog Introduction (5)

 Verilog History
Verilog-1995 SystemVerilog 3.0
Gateway started to
First IEEE Verilog Accellera
develop Verilog
Standard Extensions to V2K

1984 1990 1995 2001 2002 2003

Cadence bought Verilog-2001 (V2K) SystemVerilog 3.1

Gateway, and Enhancement – 2nd Extensions to 3.0
started pushing IEEE Verilog
Verilog Standard

SystemVerilog
SystemVerilogIEEE
IEEEStandard
Standardis
isexpected
expected
to
tobecome
becomeavailable
availableby
byOct’2005
Oct’2005

SystemVerilog Introduction (6)

SystemVerilog
SV3.1 Focus: design
SystemVerilog 3.1 - HDVL language cleanup
Queues
Test Bench Assertions APIs OO Classes Semaphores
& Lists

SV3.0 Focus: enhance design

System Verilog 3.0 language capabilities
Data Types Structures Advanced Control
Interfaces Casting
& Enums & Unions Operators Flow

Verilog2K
Multi-D Arrays Generate Automatic Tasks

Verilog95
Gate Level Modeling & Timing Hardware Concurrency

SystemVerilog Introduction (7)

 SystemVerilog Components
Transaction-Level Advanced
V
Full Testbench Verilog As er verification capability

be g
se ilog

h
s t r ilo
Language with for semiformal and

nc
Testbench rti

Te Ve
Coverage formal methods.
on The Assertion
IEEE Language Standard
Verilog for Verilog
PI
2001 A e
Ve sig
I & ac
De

f
rilo n
P
D nt er
g

Design I
Abstraction:
Interface Direct C interface,
semantics, abstract Assertion API and
data types, Coverage API
abstract operators
and expressions

SystemVerilog Introduction (8)

 IEEE P1800 Structure
Chair - Johny Srouji
Vice chair – Shrenik Mehta
IEEE P1800 Secretary - Dennis Brophy
SystemVerilog WG Program Mgr: Noelle Humenick

Errata Chair: Karen Pieper LRM – Chair: TBD

Stu Sutherland

P1800 Errata 1364 Verilog

Sub-WG Sub-WG
Champions

SV- SV- SV- SV-CC & BTF Encryption Errata

BC EC AC PTF

(transfer/merge)
SystemVerilog Introduction (9)
SystemVerilog Design Modeling
SystemVerilog enhances Verilog for Design Modeling

• Data Types • Capturing Design Intent

– SystemVerilog Data Types – always_* Procedural blocks
– Packed & Unpacked Arrays – Unique and Priority Case
• Data Organization – Nets and Variables
– Structures & Unions • Powerful Syntax
– Type Casting – Copy / Buffering
– Enumerated Data Types – Port Connections
• C-like functionality

SystemVerilog Introduction (10)

Basic SV3.1 Data Types
reg r; // 4-value Verilog-2001 single-bit datatype
integer i; // 4-value Verilog-2001 >= 32-bit datatype
bit b; // single bit 0 or 1
logic w; // 4-value logic, x 0 1 or z as in Verilog
byte b; // 2 value, 8 bit signed integer
int i; // 2-value, 32-bit signed integer
shortint s;// 2-value, 16-bit signed integer
longint l; // 2-value, 64-bit signed integer

Make your own types using typedef

Use typedef to get C compatibility
typedef shortint short;
typedef longint longlong;
typedef real double;
typedef shortreal float;

SystemVerilog Introduction (11)

Packed And Unpacked Arrays
unpacked bit a [3:0];
array of
bits

packed
array of bit [3:0] p;
bits

bit [15:0] memory [1023:0];

1k 16 bit memory[i] = ~memory[i+1];
unpacked memory[i] [15:8] = 0;
memory
Packed indexes
can be sliced

1k 16 bit Can operate on

bit [15:0] [1023:0] Frame;
packed entire memory
always @ (posedge inv)
memory Frame = ~Frame;

SystemVerilog Introduction (12)

Data Organization
• Signals are Meaningful In Groups
– Instructions: Operation, Operands
• Verilog Provides Only Informal Grouping
reg [47:0] PktSrcAdr; reg [31:0] Instruction;
reg [47:0] PktDstAdr; `define opcode 31:16
reg [7:0] InstOpCde; Instruction[`opcode]
reg [7:0] InstOpRF [127:0];

By Name By Vector Location

• Better to organize data in explicit, meaningful

relationships between data elements
• SystemVerilog Structs, Unions & Arrays alone or
combined better capture design intent

SystemVerilog Introduction (13)

Data Organization - Structures
struct {
addr_t SrcAdr; • Structs Preserve
addr_t DstAdr; Logical Grouping
data_t Data;
} Pkt; • Reference to Struct
facilitates more
Pkt.SrcAdr = SrcAdr; meaningful code
if (Pkt.DstAdr == Node.Adr)
Like
LikeininCCbut
butwithout
without
the
theoptional
optionalstructure
structure
tags
tagsbefore
beforethe
the{{
typedef struct { bit [7:0] opcode;
bit [23:0] addr;
} instruction; // named structure type

instruction IR; // define variable

IR.opcode = 1; // set field in IR

SystemVerilog Introduction (14)

 Data Organization - Packed Structures
Consists of bit fields, which are packed together in memory without gaps
– They are easily converted to and from bit vectors.

struct packed { `define Valid 24

bit Valid; `define Tag 23:16
byte Tag; `define Addr 15:0
bit [15:0] Addr;
} Entry; iTag = Entry[`Tag];
iTag = Entry.Tag; iAddr = Entry[`Addr];
iAddr = Entry.Addr; iValid = Entry[`Valid]
iValid = Entry.Valid
32 0
2
unpacked Valid
1 Tag
packed
packedstruct
structmay
may struct
0 Addr
contain
containother
otherpacked
packed
structs
structsor
orpacked
packedarrays
arrays
24 23
Valid Tag
1615
Address
0

packed
struct

SystemVerilog Introduction (15)

 Data Organization - Type Casting
int'(2.0 * 3.0) A data type can be changed
shortint' {8’hFA, 8’hCE} by using a cast (‘) operation
17 ' (x – 2)

Any aggregate bit-level object can be reshaped Objects

Objectsmust
musthave
have
Packed ⇔ Unpacked, Array ⇔ Structure identical
identicalbit
bitsize
size
typedef struct {
bit [7:0] f1;
f1 A
bit [7:0] f2;
bit [7:0] f3[0:5]; f2
} Unpacked_s;
typedef struct packed { f30 f31 f32 f33 f34 f35
bit [15:0][0:2] f1;
bit [15:0] f2;
} Packed_s; B
Unpacked_s A;
Packed_s B; f10 f11 f12 f2
…
A = Unpacked_s’(B);
B = Packed_s’(A);

SystemVerilog Introduction (16)

 Data Organization - Unions
typedef union { typedef union {
union
int n; byte [5:0] bytes;
real f; provide storage for real rlevel;
} u_type; either int or real integer ilevel;
} Data_u_t;
u_type u;
struct {
structs and unions can be assigned as a Data_u_t Data;
whole logic isBytes;
can contain fixed size packed or unpacked logic isReal;
arrays logic isInteger;
} DPkt;
Unpacked Unions Enable Single Variable DPkt.Data = 3.124;
to Contain Data from Multiple Types DPkt.IsReal = 1;
Data Read from Unpacked Union Must Be if (DPkt.IsReal)
from Last Field Written realvar = DPkt.rlevel;

Requires Type Awareness

SystemVerilog Introduction (17)

Data Organization – Packed Unions
• Packed Unions Enable • Packed Unions Enable
Multiple Namespaces for Many Convenient Name
Same-Sized, Integer Data References

typedef logic [7:0] byte_t; inst.fields.opcode = 16’hDEAD;

typedef struct packed { inst.bytes[1] = 8’hBE;
logic [15:0] opcode; inst[7:0] = 8’hEF;
logic [1:0] Mod;
… inst == 32’hDEADBEEF;
logic [2:0] Base;
} Instruction_t;
typedef union packed {
byte_t [3:0] bytes;
Instruction_t fields;
• No Need To Test Type
} Instruction_u; • Data Maps To All
Instruction_u inst; Members

SystemVerilog Introduction (18)

 Data Organization – Tagged Unions
• Provide type-safety and brevity
• Improve correctness
• Improve ability to reason about programs for FV
typedef tagged union {
struct {
bit [4:0] reg1, reg2, regd;
} Add;
Instr
Instr
tagged instr;
instr;
union {
...
bit [9:0] JmpU;
...
case
case
struct(instr)
(instr)
{ matches
matches
tagged
tagged Add {r1,r2,rd}:
bit [1:0]
Add {r1,r2,rd}: rf[rd]
cc, rf[rd] == rf[r1]
rf[r1] ++ rf[r2];
rf[r2];
tagged
tagged Jmp j:
Jmp
bit [9:0] j:
addr; case (j)
case matches
(j) matches
} JmpC; tagged JmpU
tagged JmpU aa :: pc
pc == pc
pc ++ a;
a;
} Jmp; tagged JmpC
tagged JmpC {c,a}:
{c,a}:
} Instr; if (rf[c])
if (rf[c]) pc pc == a;
a;
endcase
endcase
endcase
endcase

SystemVerilog Introduction (19)

 Data Organization – Enum
typedef enum {red, green, blue, yellow,
white, black} Colors;
a=2*3=6
Colors col; col=3
integer a, b; b=3+1=4
a = blue * 3;
col = yellow;
b = col + green;

• Finite State Machines

typedef enum logic [2:0] {idle, – Currently a List of Parameters
init, decode …} fsmstate;
fsmstate pstate, nstate; – Why Not A Real List of
Values?
case (pstate)
idle: if (sync) – Enumerate formally defines
symbolic set of values
nstate = init;
init: if (rdy) • Enumerates are strongly typed
nstate = decode; to ensure assignment to value
… in set
endcase
typedef enum {lo,hi} byteloc; • Symbolic Indexes to Make
memory[addr][hi] = data[hi]; Array References More
Readable

SystemVerilog Introduction (20)

 Design Intent – always_*
• In Verilog, always blocks do not
//forgot Else but it’s
guarantee capture of intent //only a synthesis warning
– If not edge-sensitive then only a always @ (a or b)
if (b) c = a;
warning if latch inferred

• SystemVerilog introduces always_comb

three new logic specific a = b & c;
processes
– Combinational Coding Style
– Latch Coding Style always_latch
if (en) q <= d
– Sequential Logic

always_ff @(posedge clk, negedge rst_n)

Allows
Allowssimulation
simulationto
to if (!rst_n) q <= 0;
perform
performsome
someDRCDRC else q <= d;

SystemVerilog Introduction (21)

 Design Intent – always_*
• Compiler Now Knows User Intent and can flag errors

always_comb ERROR: combinational logic requested

if (en) q <= d; but latch was inferred

always_ff @ (clk, rst_n) ERROR: incorrect sensitivity list

if (!rst_n) q <= 0; flip flop not inferred
else q <= d;

• Both always @* and always_comb

– Ensures synthesis-compatible sensitivity
– Helps reduce “spaghetti code”
– But, always_comb infers the sensitivity list from within functions called in
the always block

SystemVerilog Introduction (22)

 Design Intent – Unique/Priority
• Verilog synthesis pragmas are “full_case” & “parallel_case”
– Pass different information to synthesis and simulator
– May cause pre- & post-synthesis simulations differences
• SystemVerilog introduces Unique and Priority
– Passing the same information to the simulator and synthesis tool
– Enables Simulation, Synthesis and FV to behave consistently
bit [2:0] a; priority casez (a)// values 4,5,6,7
unique case (a) // values 3,5,6,7 cause // cause run time
// run time warning // warning
0,1: $display(“0” or “1”); 3’b00?: $display(“0” or “1”);
2: $display(“2”); 3’b0??: $display(“2” or “3”);
4: $display(“4”); endcase
endcase

tests
testseach
eachcase
casecondition
conditionininorder
orderand
and
tests
testsall
allcase
caseconditions
conditionsand
andmakes
makessure
sure makes sure there is at least one branch
makes sure there is at least one branch
that
thatone
oneand
andonly
onlyone
onecondition
conditionmatches
matches taken
taken

SystemVerilog Introduction (23)

 Design Intent – nets vs. variables
• In Synthesized Design most nets • Multiply Driven, Variable-Strength
have a single driver Nets generally take great care to
design. Would like these nets to
stand out in the design.
• Use Net Types to Distinguish
trireg [1:0] dbus;
assign dbus = wen[0] ? cff : ‘z;
• Combination of SystemVerilog assign dbus = wen[1] ?
variables and processes can enforce {cff[0],cff[1]} : ‘z;
single driver/avoid multiple drivers
• Variables may be driven by only one logic [1:0] n0,n1,n2,n3,n4;
assign n0 = {ina,inb};
of the following always_comb
– continuous assignment if (sela) n1 = ina;
– always_comb else n1 = inb;
always_latch
– always_latch if (sela) n2 <= ina;
– always_ff always_ff @(posedge ck)
n3 <= ina;
– module port sbuf buf1 (.di(n1),.do(n4));
• Compilers Can Catch Your Mistakes sbuf buf2 (.di(n2),.do(n4));

SystemVerilog Introduction (24)

Powerful Syntax – .* Port Connections
• Creating netlists by hand module top();
is tedious logic rd,wr;
• Generated netlists are tri [31:0] dbus,abus;
unreadable tb tb1(.*);
dut dut1(.*);
– Many signals in
instantiations endmodule
– Instantiations cumbersome
to manage
• Implicit port connections
dramatically improve module top();
readability logic rd,wr;
tri [31:0] dbus,abus;
• Use same signal names tb tb(.*, .ireset(start),
up and down hierarchy .oreset(tbreset));
where possible dut d1(.*,.reset(tbreset[0]));
dut d2(.*,.reset(tbreset[1]));
• Emphasize where port endmodule
differences occur

SystemVerilog Introduction (25)

 Familiar C Features
do continue starts
begin next loop iteration works with:
for
if ( (n%3) == 0 ) continue;
while
if (foo == 22) break; forever
end break exits repeat
while (foo != 0); the loop do while
…
Blocking Assignments Extra parentheses
if ( (a=b) ) … required to distinguish
as expressions while ((a = b || c)) from if(a==b)

Auto increment/ x++;

decrement operators if (--c > 17) c=0;
Assignment Operators
a += 3; Semantically equivalent
s &= mask; to blocking assignment
Wildcard Comparisons f <<= 3;
X and Z values act as
a =?= b
wildcards
a !?= b

SystemVerilog Introduction (26)

 SystemVerilog for Verification
• SystemVerilog extends the language to include
Verification and Test-Bench modeling constructs

• Extended Data Types • Object Oriented Programming

– Dynamic Arrays – Class; Object; Methods
– Associative Arrays • Communication Encapsulation
• Process Synchronization – Interfaces
– Semaphors and Event • Assertion Based Design
Variables
– Assertions Constructs
– Mailbox queues
– Usage
– Processes and Threads

SystemVerilog Introduction (27)

Dynamic Arrays
Declaration syntax bit[3:0] fix[0:3];
<type> <identifier> [ ];
bit[3:0] dyn[ ];
A
B
Initialization syntax C
<array> = new[<size>];
dyn D
dyn = new[4];
Size method A
function int size(); B
int j = dyn.size;//j=4 C
Resize syntax D
<array> = new[<size>](<src_array>);
dyn = new[j * 2](fix);

SystemVerilog Introduction (28)

Dynamic Arrays
Declaration syntax
<type> <identifier> [ ];
bit[3:0] dyn[ ];
Initialization syntax
<array> = new[<size>];
dyn = new[4];
dyn
Size method A
function int size(); B
int j = dyn.size;//j=4 C
Resize syntax D
<array> = new[<size>](<src_array>);
dyn = new[j * 2](fix);
Delete method
function void delete();
dyn.delete; // dyn is now empty

SystemVerilog Introduction (29)

 Associative Arrays
• Excellent for Sparse Storage
• Elements Not Allocated Until Used
• Index Can Be of Any Packed Type, String or Class

Declaration syntax
<type> <identifier> [<index_type>];
<type> <identifier> [*]; // “arbitrary” type

int imem[*]; struct packed {int a; logic[7:0] b}

imem[ 2’b3 ] = 1; mystruct;
imem[ 16’hffff ] = 2; int myArr [mystruct];
imem[ 4b’1000 ] = 3; //associative array indexed by mystruct

Built-in Methods
num(), delete([index]), exists(index);
first/last/prev/next(ref index);
Ideal
Idealfor
forDealing
Dealingwith
withSparse
SparseData
Data
SystemVerilog Introduction (30)
Object-Oriented Programming
• Organize programs in the • Class – A blueprint for a house
same way that objects – Program element “containing”
related group of features and
are organized in the real functionality.
world – Encapsulates functionality
• Break program into – Provides a template for building
objects
blocks that work together
• Properties – It has light switches
to accomplish a task,
– Variables specific to the class
each block has a well
• Methods – Turn on/off the lights
defined interface
– Tasks/functions specific to the
• Focuses on the data and class
what you are trying to do • Object – The actual house
with it rather than on – An object is an instance of a
class
procedural algorithms

SystemVerilog Introduction (31)

OOP - Class Definition
Definition Syntax
class name;
<data_declarations>; class Packet;
<task/func_decls>; bit[3:0] cmd;
endclass int status;
myStruct header;
extern keyword allows function int get_status();
for out-of-body method return(status);
declaration endfunction
extern task set_cmd(input bit[3:0] a);
endclass

“::” operator links

method declaration to
task Packet::set_cmd(input bit[3:0] a);
Class definition
cmd = a;
endtask

Class
Classdeclaration
declarationdoes
doesnot
not allocate
allocate
any
anystorage
storage
SystemVerilog Introduction (32)
 OOP - Class Instantiation
• Objects Allocated Packet myPkt = new;

and Initialized Via myPkt

Call to the new class Packet; cmd IDLE
Constructor ... status 5
function new();
Method cmd = IDLE;
header

– All objects have endfunction

endclass
built-in new method
Packet myPkt = new;
• No arguments
• Allocates storage class Packet;
...
for all data
function new(input int a);
properties
cmd = IDLE;
– User-defined new status = a;
method can endfunction
initialize and/or do endclass
other things Packet myPkt = new(5);
// myPkt.status = 5

SystemVerilog Introduction (33)

OOP - Class Inheritance & Extension
• Keyword extends
class ErrPkt extends Packet;
Denotes Hierarchy of bit[3:0] err;
Definitions function bit[3:0] show_err();
– Subclass inherits return(err);
properties and methods endfunction
from parent task set_cmd(input bit[3:0] a);
cmd = a+1;
– Subclass can redefine
endtask // overrides Packet::set_cmd
methods explicitly
endclass

Packet: ErrPkt:
cmd cmd
status get_status status get_status

show_err
header header
set_cmd set_cmd
cmd = a; err cmd = a+1;

Allows
AllowsCustomization
CustomizationWithout
WithoutBreaking
Breakingor
orRewriting
Rewriting
Known-Good
Known-GoodFunctionality
Functionalityininthe
theParent
ParentClass
Class

SystemVerilog Introduction (34)

 Process Synchronization
• SystemVerilog adds a powerful and easy-to-use set of
synchronization and communication mechanisms
– Which can be created and reclaimed dynamically
– Dynamic parallel processes using fork/join_any and fork/join_none

fork fork fork

join join_any join_none

• SystemVerilog adds
– a semaphore built-in class - for synchronization and mutual exclusion
to shared resources
– a mailbox built-in class - communication channel between processes
– event data type to satisfy system-level synchronization requirements

SystemVerilog Introduction (35)

 Process Synchronization –
Semaphores & Event Variables
• Events – enhanced from V2K
– Events are variables – can be copied, passed to tasks, etc.
– event.triggered; // persists throughout timeslice, avoids races
• Semaphore – Built-in Class
– Synchronization for arbitration of shared resources, keys.
– Mutual Exclusivity control
– Built-in methods: new, get, put, try_get
KEYS
// main program …..
semaphore shrdBus =new; shared bus // usage, forking parallel
... // threads for cpu access
task go_cpu(id, event ev…) event ev1,ev2;

semaphores
begin ... ...
@(ev) shrdBus.get () fork
...//access granted go_cpu(cpu1,ev1);
...//activity on the cpu bus go_cpu(cpu2,ev2);
shrdBus.put() ...
CPU1 CPU2 join
... Cache Cache ...
endtask

Guarantees
GuaranteesRace-Free
Race-FreeSynchronization
Synchronization
Between
BetweenProcesses
Processes
SystemVerilog Introduction (36)
Process Synchronization - Mailbox
• Mailbox features
– FIFO message queue: passes data between threads
– Can suspend thread, used for data checking
• Mailbox built-in methods
– new(), num(), put(), try_put(), get(), try_get(), peek(), try_peek()

Testbench compares the actual output with expected output [Packets]

mailbox pktMbx = new;
pktMbx.put(inPkt1); pktMbx.get(outPkt);
compare_twoPackets;
Packet 2

Packet 3
Packet 1

Packet 4
Packet
Stimulus

Compare
DUT output
Input to
Design

SystemVerilog Introduction (37)

Process Synchronization - Example
program • Threads are created via
fork fork…join
a b c a;b;c; • Threads execute until a
join
blocking statement
fork a;b;c;
a b c join_any
– mailbox, semaphore, etc
• “wait fork”; “disable fork”
fork a;b;c; are introduced
a b c join_none
• $exit terminates the main
fork a;b;c; program thread
a b c join_any
disable fork; // kill all child processes

fork a;b;c;
a c join_any
b
wait fork; // wait for children to complete
#10;
$exit

SystemVerilog Introduction (38)

Interface
• An Interface Provides a new hierarchical structure
– Encapsulates communication
– Captures Interconnect and Communication
– Separates Communication from Functionality
– Eliminates “Wiring” Errors
– Enables abstraction in the RTL

int i; int i;
logic [7:0] a; wire [7:0] a;

interface intf;
typedef struct { At
Atthethesimplest
simplest int i;
int i; level an interface
logic [7:0] a; level an interface wire [7:0] a;
isistotoaawire
wire endinterface : intf
} s_type;
what
whataastruct structisis
totoaavariable
variable

SystemVerilog Introduction (39)

How Interfaces work
interface intf;
bit A,B;
byte C,D; modA intf modB
logic E,F;
endinterface
Instantiate
module top ( ); Interface An interface is similar to a module
intf w; straddling two other modules

modA m1(w);
modB m2(w); An
Aninterface
interfacecan
cancontain
contain
endmodule anything
anythingthat
thatcould
couldbebeininaa
module
moduleexcept
exceptother
other
module modA (intf i1);
endmodule module
moduledefinitions
definitionsor
or
module modB (intf i1); instances
instances
endmodule

Allows structuring the information flow between blocks

SystemVerilog Introduction (40)

 Example without Interface
module top;
module memMod(input logic req,
logic req,gnt,start,rdy;
bit clk, bit clk = 0;
logic start, logic [1:0] mode;
logic[1:0] mode, logic [7:0] addr,data;
logic[7:0] addr,
inout logic[7:0] data, memMod mem(req,clk,start,mode,
output logic gnt, addr,data,gnt,rdy);
logic rdy); cpuMod cpu(clk,gnt,rdy,data,
always @(posedge clk) req,start,addr,mode);
gnt <= req & avail; endmodule
endmodule

module cpuMod(input bit clk,

logic gnt,
logic rdy,
inout logic [7:0] data,
output logic req,
logic start,
logic[7:0] addr,
logic[1:0] mode);
endmodule

SystemVerilog Introduction (41)

Example Using Interfaces
Bundle signals interface
interface simple_bus; module top; instance
in interface
logic req,gnt; bit clk = 0;
logic [7:0] addr,data; simple_bus sb_intf; Connect
logic [1:0] mode; interface
logic start,rdy; memMod mem(sb_intf, clk);
endinterface: simple_bus
cpuMod cpu(.b(sb_intf),
Use interface .clk(clk));
keyword in port list endmodule
module memMod(interface a,
input bit clk);
logic avail;
always @(posedge clk)
a.gnt <= a.req & avail;
endmodule
Refer to intf
signals
module cpuMod(interface b,
input bit clk);
endmodule

SystemVerilog Introduction (42)

 Interface Verification Benefits
• Interfaces provide
• Pre- tbI
tbA tbB
reusable
Integration I I
components
I
• tbA and tbB are
A B ‘linked’
Test interface
in isolation • Interface is an
executable spec
tbS • Wiring up is simple
and not error
S
• Post-Integration prone
A I
B • Interfaces can
contain protocol
checkers and
coverage counters
Protocol bugs
already flushed out

SystemVerilog Introduction (43)

SystemVerilog Assertions
• A concise description of desired / undesired behavior
• Supports Assertion Based Verification methodology
– White-box (inside block) assertions
– Black-box (at interface boundaries) assertions
• Usability
– Easy to code, understand and use by Design and Verification
Engineers
• Monitoring the design
– Concurrent (“standalone”) assertions
– Procedural (“embedded”) assertions
• Formalism
– Formal semantics to ensure correct analysis
– Consistent semantics between simulation and formal design
validation approaches

SystemVerilog Introduction (44)

Assertion Types
• Two kinds of Assertions: Immediate and Concurrent
• Immediate Assertions:
– Appears as a procedural statement
– Follows simulations semantics, like an “if”
assert ( expression ) action_block;
– Action block executes immediately and can contain system tasks
to control severity, for example: $error, $warning
• Concurrent Assertions:
– Appears outside/inside procedural context
– Follows cycle semantics using sampled values
assert property ( property_instance_or_spec )
action_block;
– Action block executes in reactive region and can contain system
tasks to control severity, for example: $error, $warning

SystemVerilog Introduction (45)

 Assertions Example
“After request signal is asserted, acknowledge signal must come 1 to
3 cycles later”
property req_ack;
@(posedge clk) req ##[1:3] $rose(ack);
SVA Assertion endproperty
as_req_ack: assert property (req_ack);

always @(posedge req)

begin
repeat (1) @(posedge clk);
fork: pos_pos
0 1 2 3 4 5 begin
@(posedge ack)
req $display("Assertion Success",$time);
disable pos_pos;
end
ack begin
Example intended behavior repeat (2) @(posedge clk);
$display("Assertion Failure",$time);
disable pos_pos;
end
join
V2K Assertion end // always

SystemVerilog Introduction (46)

 Assertions Usage @Intel
• RTL assertions are a powerful validation tool, and have been used in
Intel for over a decade
• Basic combinational assertions
– Most are either FORBIDDEN or MUTEX
• Sequential assertions improve the ability to capture design intent.
Used to capture:
– Assumptions on the interface
– Expected output
– Local relations
• Template Library: consists of dozens of temporal and combinatorial
properties for:
– Safety Properties: expresses that "something bad will not happen"
during a system execution
– Liveness Properties: expresses that "something good must happen"
during an execution

SystemVerilog Introduction (47)

Assertions Usage @Intel
• Easier for designers to write assertions using the template
library
– No need to ramp-up on a formal specification language
– Hides the subtle implementation details
• RTL assertions caught >25% of all bugs!
• High in bug hunting in CTE – right after designated CTE checkers
• Very high in bug hunting at the FC level
• RTL assertions were the first to fail
• They were more local than checkers and mostly combinatorial
• RTL assertions shortened the debug process
• Assertions point directly at the bug

SystemVerilog Introduction (48)

SystemVerilog DPI – WHY?
Direct Programming Interface
• Users need a simple way of invoking foreign functions
from Verilog and getting results back
• VPI and PLI are not easy to use
– Even trivial usage requires detailed knowledge
– Many users don’t need the sophisticated capabilities
– Verilog can invoke C functions but C functions can’t invoke Verilog
functions
• SystemVerilog includes assertions. These were not
addressed by any prior Verilog API
• DPI and VPI extensions are based on Direct-C donation
from Synopsys

SystemVerilog Introduction (49)

SystemVerilog DPI - Overview
• DPI is a natural inter-language function call interface
between SystemVerilog and C/C++
– The standard allows for other foreign languages in the future
• DPI relies on C function call conventions and semantics
• On each side, the calls look and behave the same as
native function calls for that language
– On SV side, DPI calls look and behave like native SV functions
– On C side, DPI calls look and behave like native C functions
• Binary or source code compatible
– Binary compatible in absence of packed data types (svdpi.h)
– Source code compatible otherwise (svdpi_src.h)

SystemVerilog Introduction (50)

The QUIZ
Question: How do you get 20 Elephants
into a Volkswagen beetle?

I don’t know! BUT …

SystemVerilog Introduction (51)

QUIZ How do you get
20 lines of
Verilog into 4
! ! ! "
# cm?
#
! ! ! #
#
! ! ! #
$
" " #
! %& #
! %& # !"
#
! %& #
!%& #

SystemVerilog Introduction (52)

QUIZ How do you get
20 lines of
Verilog into 4
! ! ! "
# cm?
#
! ! ! #
#
! ! ! #
$
" " #
! %& #
! %& # !"
#
! %& #
!%& #

SystemVerilog Introduction (53)

Conclusions
• SystemVerilog was demonstrated as:
– The next generation of HW Design Language
– Provides a comprehensive language coverage for
Modeling and Verification (HDVL)
– Enables design abstraction; more accurate modeling
and capture of designer intent
– Integrates to external languages
– Has wide and increasing support in the EDA
– Being used on real life complex design projects
– Being standardized under IEEE P1800 with the goal
of convergence with Verilog

SystemVerilog Introduction (54)

Q&A

SystemVerilog Introduction (55)

SystemVerilog & SystemC
ALG

ev e l
System Verilog System C f o r S ys te m L
Use
Design Architecture

T L Design Abstract RTL

R
Use for

Netlist RTL
System
System Verilog
Verilog&&System
System CCComplement
ComplementEach Each
Other
Otherin
inARCH
ARCH Physical
Physical Design
Design Flow
Flow
SystemVerilog Introduction (56)