ESD Protection Circuits: Basics

to nano-metric ASICs

Manoj Sachdev
University of Waterloo
[email protected]

September 2007

1
Outline
† Group Introduction
† ESD Basics
† Basic ESD Protection Circuits
† Nano-metric ESD Challenge
† ESD circuits for nano-metric regime

2
 Group Introduction
† 5 PhDs, 2 masters and
2 PDFs
„ Applied, industrially
driven research
„ Generous funding levels
† Core strengths in circuit
design, testing, quality
and reliability

3
Group: Low Power Research
† Driven by low power signal
processing & bio-implantable
applications
† Research focus
„ Active power reduction, clocking
strategies
„ Dynamic voltage scaling
architecture for portable app.
„ Leakage power reduction:
Investigation of RBB effectiveness
with scaling 4
Group: High Performance Circuits
† Driven by high speed
arithmetic circuits (Adders,
register files, ALU), and CDRs
† Research focus
„ To build timing diagnostics into
multi-GHz ALUs
„ Leakage and active power
reduction
„ Clock de-skewing
„ Thermal issues in high
performance circuits 5
 Group: Memory Research
† Driven by embedded SRAMs
and Soft Error Robustness
† Research Focus
„ SRAM cell stability & ckt
techniques for detection
„ Low power embedded SRAMs
„ Soft Error Robust memories &
flip-flops
„ Error Correction Circuit’s for
soft error mitigation
6
 Group: ESD Research
† Driven by reducing chip failures
due to ESD
† Research Focus
„ ESD strategies for multiple supply
domains
„ ESD protection circuits for High
speed I/Os
„ Fast response ESD protection
circuits

7
Outline
† Group Introduction
† ESD Basics
† Basic ESD Protection Circuits
† Nano-metric ESD Challenge
† ESD circuits for nano-metric regime

8
ESD Basics :Motivation

† Electrostatic Discharge (ESD) is responsible for up to 70%

of failures in semiconductor industry
† An ESD event creates high currents and electric fields in
semiconductor devices
† High currents may lead to thermal runaway

† High electric fields cause dielectric breakdown

9
ESD Basics
† When two dissimilar materials are separated an
ESD charge may develop
† Caused by the removal of electrons from surface
atoms of materials
† Factors
„ Magnitude of static charge
„ Contact quality
„ Rate of separation

10
Human Body Model (HBM)
R A B Rb=1.5k

V
DUT
Cb=100pF

† Mimics the human touching of the Device

Under Test (DUT)
† Voltages as high as 10kV can be developed
† HBM modeled by series resistance (Rb = 1.5kΩ)
and capacitance (Cb = 100pF)
11
Machine Model (MM)
R A B 0.5uH

V
DUT
200pF

† Represents the damage caused by charged

machine touching the DUT
† Voltages as high as 100-500V can be generated
† MM is modeled by capacitance (C = 200pF) and
series inductance of machine (0.μ5H) 12
Charge Device Model (CDM)
R A B

V DUT

Cap

† Discharge event between charged DUT and grounded

conductor
† Modeled by Capacitor (Cap) in series with DUT
† Total Capacitance (Cap) is dependant on Device,
package impedance 13
 ESD Stress Comparison

† HBM rise time ~ 2-10ns, decay time 130-170ns

† CDM very high amplitude , occurs for 500ps-1000ps

† CDM failures on rise due to automated manufacturing

14
Zapping Modes
† Positive ESD with † Negative ESD with
respect to VSS respect to VSS
(PS-mode) (NS-mode)

VDD VDD

VESD VESD

VSS VSS

15
Zapping Modes
† Positive ESD with † Negative ESD with
respect to VDD respect to VDD
(PD-mode) (ND-mode)

VDD VDD

VESD VESD

VSS VSS

16
 HBM / MM / CDM Testers
† HBM/MM/CDM testers apply
ESD stress to the DUT
† Magnitude/polarity of the stress
set by the user
† Test can be destructive
„ Results in pass or fail

ICMS-700 HBM/MM tester

† The device fails when leakage
is increased significantly
17
 TLP Tester
† Transmission Line Pulse
(TLP) is becoming popular
„ Measures I-V characteristic of the
DUT
„ Non-destructive
† Programmable current pulse
of 100ns are applied to the
DUT
† 2nd breakdown current
Barth 4002 TLP tester
determines the ESD
robustness
18
Outline
† Group Introduction
† ESD Basics
† Basic ESD Protection Circuits
† Nano-metric ESD Challenge
† ESD circuits for nano-metric regime

19
ESD Protection Methods
† Snapback-based † Non-snapback-based
„ Turn on before oxide „ Trigger and conduct during
breakdown the whole ESD event
„ Minimum parasitics „ Do not trigger under
normal power-up

20
Diode Under ESD Conditions
† Forward biased:
„ Low trigger voltage
„ Low on resistance

† Reverse biased:
„ High trigger voltage
„ High on resistance

21
MOS Under ESD Conditions
† Has a parasitic bipolar transistor
„ Avalanche breakdown gives Igen and Isub
„ When Vbase = 0.7V, npn turns on Æ Snapback
„ When I(drain) = It2 , npn can be destroyed
Drain

n+ Igen n+

Vbase Isub
Rsub

p-sub 22
Snapback Protection: MOSFET
† MOSFET is used in
Grounded- Gate VDD
PAD
configuration
(GGNMOS)
PreDriver

„ Substrate and Gate I/O

PAD

triggering is often GGNMOS

PreDriver
needed
VSS
PAD
ESD Protection Buffer stage
Device

23
ESD Protection Wish List
† Vt1 < Oxide breakdown
„ To trigger NMOS before oxide breaks down
† Vt2 > Vt1
„ To ensure uniform triggering of all fingers
† Vh > VDD
„ To enhance latch-up immunity (VDD + 10%)
† It2 as high as possible
„ Increase current carrying capability Æ ↑ESD

† A GGNMOS cannot meet all the above

requirements for contemporary technologies
24
SCR Under ESD Conditions
† SCR is a pnpn device
„ In CMOS the junctions are: p+-nwell-psub-n+

VDD
Anode PAD

PreDriver

n+ p+ n+ p+ I/O
PAD
n-well p+
n-
PreDriver
p-
n+
VSS
p-sub PAD
ESD Protection Buffer stage
Device
25
 SCR Characteristic
† Avalanche breakdown of nwell-psub ↑ IRnwell and IRpsub
† When VBE reaches 0.7V, npn (or pnp) turns on
† Positive feedback turns on the pnp (or npn) Æ Snapback

Anode
I(anode)
Rn-well
(Vt2, It2)

(Vh, Ih)
(Vt1, It1)
Rp-sub
V(anode)
26
 ESD Devices: Comparison
† Protection level:
„ SCR and FB diode are the
best
† Trigger voltage:
„ FB Diode is too low
„ NMOS is the best
„ SCR should be modified
† Holding voltage:
„ NMOS is ok
„ SCR should be modified
† Figure of merit
„ Protection level/Capacitance
27
Non-Snapback Protection: Clamps
† ESD event Æ V(1) rises
turning on M0
† RCCC + inverters should
keep M0 “on” to discharge
all ESD energy
† Advantages ESD event:
„ Protect against different tr: between 100ps and 60ns
zapping conditions duration: up to 1μs
Regular power-up:
† Disadvantages
In millisecond range
„ Can turn on during normal
Hot plug app. power-up
power-up
as low as 1μs
28
Outline
† Group Introduction
† ESD Basics
† Basic ESD Protection Circuits
† Nano-metric ESD Challenge
† ESD circuits for nano-metric regime

29
 Challenges with Scaling

† Breakdown Voltage of CMOS devices is decreasing

„ Traditional ESD structures not scaling with technology scaling
† Larger ULSI, thinner metallization, shallower junctions
„ Increasingly difficult to provide low impedance, low capacitance
discharge path
30
Challenges: Charged Device Model
14
12 HBM
MM
10
CDM
8
6
Current (A) 4

2
0
-2
-4
-6
0 20 40 60 80 100 120
Time (ns)

† Lower Technologies (90nm , 65nm) damage occur at lower voltages

„ Traditional ESD circuits trigger slower
† High speed chips Æ larger package decoupling cap
„ Higher CDM discharge current!!
† CDM failures on rise due to automated manufacturing
31
Challenges: Multiple Supply Domains

† Multiple supply domains in SoC’s

„ Pin to pin ESD protection requirement
„ Multiple zapping modes
† Challenge to Overcome Noise Coupling & ground-
bouncing issues between analog & digital supplies
32
Challenges: Multiple Chip Module

† Resistance of the path can be very high (Multiple Chip Module)

† Minimization of Parasitic Capacitance attributed to the High Speed
I/O’s due to ESD Circuit

33
Outline
† Group Introduction
† ESD Basics
† Basic ESD Protection Circuits
† Nano-metric ESD Challenge
† ESD circuits for nano-metric regime

34
Strategy – Device Simulation
† MOS models, circuit simulators are not designed
to handle snapback behavior
† ESD circuits are designed with device simulators
(Medici and Sequoia)
„ Device cross section is created in the simulator
„ Quasi-DC simulation predicts DC characteristic, i.e. Vt1
and Vh
„ It2 is estimated using thermal simulation and monitoring
maximum temperature of the ESD protection device

35
 Design Steps
1. Calibrate the device simulator with the
desired technology
„ Junction depth and substrate doping are
available from technology documents
2. Verify the technology model by simulating a
MOS transistor
„ Trial and error is used to achieve the typical
I(on), Vth, current gain and
3. Draw the cross-section of the ESD device
36
Design Example #1 – LVTSCR
p-type
n-type
contact
oxide

† Mesh of the Low-Voltage-Triggered SCR

(LVTSCR) created in Medici
† Reducing grid spacing increases accuracy and
simulation time
37
 Snapback Protection Requirements
† Reduce first breakdown voltage
„ SCR has higher Vt1 compared to MOS
„ Vt1 of both MOS and SCR are higher than oxide breakdown voltage
† Latch-up immunity
„ Very important in SCR devices
† Increasing second breakdown current
„ SCR has higher It2 per width
† Reducing parasitic capacitance
† SCR provides protection with less capacitance
I(anode)
(Vt2, It2)

(Vh, Ih)
(Vt1, It1)
38
V(anode)
Gate-Coupling
† ↑Vgs Æ ↑Isub Æ npn triggers faster Æ ↓Vt1
† For higher Vgs (strong inversion region): impact
ionization is decreased Æ Vt1 increases

4.8

4.6

4.4
Vt1 (V)
4.2

3.8

3.6

3.4
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
39
V(Gate) (V)
Substrate Triggering
† ↑Vsub Æ Transistor triggers with lower ↓Vt1

Drain
4.5

4
+ +
n n Vt1 (V)

3.5

3
p-sub
2.5

Sub 2
0 0.25 0.5 0.75 1 1.25 1.5
V(Sub) (V)
40
 GST-LVTSCR
† SCR is modified by adding a
gate electrode to reduce Vt1
(LVTSCR)
† MG provides gate triggering
„ Can be as small as 5μm
† MS provides substrate
triggering
† Simulation results
„ Vt1 reduces from 12V to 4.85V

41
Semenov et. al., Microelectronics Reliability, 2005
GST-LVTSCR (Measurement)
† GST-LVTSCR was
fabricated in 0.13μm
Leakage (A)

1.00E-12 1.00E-10 1.00E-08 1.00E-06 1.00E-04

CMOS technology 2.50E+00

† TLP measurements 2.00E+00

„ Vt1 = 5V Current (A)

1.50E+00

„ It2 = 1.8A 1.00E+00

HBM measurements
TLP I-V
† 5.00E-01 TLP Leakage

„ Device passes ±3kV 0.00E+00

0 2 4 6 8 10
Voltage (V)

42
 Example #2 – Increasing Vh
Anode
† In holding region both Q1 and I1
Rn-well
Q2 are in saturation
Q1
† SCR
Q2
Vh= VEB1+ VCE2(sat)
Rp-sub
† High Vh SCR (RE is added) RE I2

Cathode
Vh = VEB1+ VCE(sat) + REI1 Anode RE Cathode
Vh = VEB1 + VCE(sat)+ VEB1RE/Rn-well
† RE↑ → Vh↑ n+ p+ n+ p+

n-well

p-sub
Semenov et. al., ISQED, 2004 43
 Increasing Holding Voltage
V(anode) (V)

Simulation results
0 5 10 15 20 25

† 1

„ Applied to SCR 0.01

Vh is increased without an
0.0001
„
increase in Vt1 Log I(anode) (A) 1E-06

RE is implemented with diode

1E-08 SCR
† R=2k
1E-10

and MOS and applied to

R=5k

1E-12

LVTSCR 1.20E-01
LVTSCR

TLP Measurement results

HighVhMOS

† 1.00E-01 HighVhDiode

„ Vh is increased from 2.29V to 8.00E-02

3.49V and 4.55V I(anode) (A) 6.00E-02

„ Increase in Vt1 is less than 8% 4.00E-02

2.00E-02

0.00E+00
0 1 2 3 4 5 6
447 8

V(anode) (V)
Example #3 – ESD Clamps

† To solve false triggering, the triggering circuit is divided

into rise time detector and delay element
† Time constant is approximately 40ns
† Delay of the delay element should be more than 1μs
45
Thyristor-Based Clamp
VDD

CC M1 M4

1 2 3
M0

RC M2 M3 R1

VSS

Rise Time Delay Element

Detector

† CMOS thyristor is used to create the delay

element
† RCCC= 40ns
† R1 to keep M0 off under normal conditions
46
Hossein et. al., ESD Symposium 2007
Circuit-Level Simulation
† The clamp is circuit
simulated with 2kV HBM
stress
7
VDD
6 V(1)

V(3) shows that clamp

V(3)
† 5

4
turns off after 1μs

Voltage (V)
3

† Peak voltage of the clamp 2

1
is less than 6V 0

-1
0E+0 3E-7 5E-7 8E-7 1E-6 1E-6 2E-6
Time (s)

47
Device-Level Simulation
† Device simulation is
done with Sequoia
† Peak temperature is in
transistor M0
† During a 2kV HBM
stress Tmax of the clamp
is 375K
† Hot-spot is in the gate-
drain boundary
48
Measurements
† Clamp was fabricated in
0.18μm technology Log Leakage (A)
1E-09 0.0000001 0.00001 0.001 0.1 10

† HBM test 2.5

„ Clamp passes 3kV stress 2

and fails at 3.5kV

Current (A)
1.5

† TLP test 1

„ Leakage current is 7nA 0.5

TLP I-V

„ Second breakdown 0
TLP Leakage

current is 1.8A 0 5
Voltage (V)
10 15

49
Example #4 – CML Driver Design

† Two stage 3Gbps CML driver Diff. Input 400mV

is designed in 0.13μm CMOS
Diff. Output 800mV
tech.
† Bias of the driver is provided Rise/fall time 150ps
through an external resistor Jitter 1ps

50
 Measured Results
5000

Vout tr Jitter 4000

3000

CML Jitter (fs)

850mV 116ps 229fs 2000
(simulation)
1000
CML+MOS
500mV 315ps 3.7ps
(measured) 0
0 100 200 300 400 500 600 700
ESD Capacitance (fF)
CML+LVTSCR
700mV 148ps 700fs
(measured) † Beyond
CESD=150fF
† Both Protection schemes jitter increases
achieved 3kV HBM protection significantly
51
Hossein et. al., CICC 2007
Conclusion
† ESD remains major cause of chip failures
„ ESD affects entire manufacturing from
devices Æ systems
† Significant challenges for nano-metric
technologies
† ESD circuit design is an art
„ Device simulator are useful in design process

52
Acknowledgement
† Help of Hossein Sarbishaei, Sumanjit
Singh, and Oleg Semenov is greatly
appreciated for this presentation

53