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Toshiba Mos Memory Product: TC5561 P-55 TC5561 P-70

The document describes a 65,536 bit CMOS static RAM chip from Toshiba. It provides high speed access of 55ns or 70ns and low power consumption of 100mA while operating or 100uA in standby mode. The chip uses ion implanted silicon gate MOS technology and has features like automatic standby mode and TTL compatibility.
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0% found this document useful (0 votes)
115 views

Toshiba Mos Memory Product: TC5561 P-55 TC5561 P-70

The document describes a 65,536 bit CMOS static RAM chip from Toshiba. It provides high speed access of 55ns or 70ns and low power consumption of 100mA while operating or 100uA in standby mode. The chip uses ion implanted silicon gate MOS technology and has features like automatic standby mode and TTL compatibility.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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TOSHIBA MOS MEMORY PRODUCT

65,536 WORD X 1 BIT CMOS STATIC RAM TC5561 P-55


SILICON GATE CMOS
TC5561 P-70
DESCRIPTION
The TC5561 P is a 65,536 bit high speed static operating current is reduced from 1OOmA to 100JLA.
random access memory organized as 65,536 words The TC5561 P is suitable for use in main memory
by 1 bit using CMOS technology, and Operated from of high speed computer and pattern memory, where
a single 5-volt supply. high speed/low power/high density are required.
Toshiba's high performance device technology The TC5561 P is moulded in a 22 pin standard
provides both high speed and low power features plastic package with 0.3 inch width for high density
with a maximum access time of 55ns/70ns and assembly.
maximum operating current of 100mA at minimum The TC5561 P is' fabricated with ion implanted
cycle time. COMS silicon gate MOS technology for high per-
The TC5561 P also features an automatic stand-by formance and high reliability.
mode. When deselected by Chip Enable (CE), the

FEATURES
• Fast access time: TC5561 P-55 55ns(MAX.) o Fully static operation
TC5561 P-70 70ns(MAX.) • Directly TTL compatible: All Input and Output
"Low power dissipation: Operation 1OOmA(MAX.) o I/O separate
Standby1 OOJLA(MAX.) • Package: 22 pin standard plastic package,
e 5V single power supply 300mil width

PIN CONNECTION (TOP VIEW) BLOCK DIAGRAM

TC5 ~ti iF AD o-t-DlIJ


--0 v DD
AU VDL' MEMORY C~LL ---0 aND
A, Alb
A3O-+Da:J ARHAY
II.".? 11.14 A4~.L..r"<"'--'
A3 11.13
A4 11.1;0
11.5 .\11
A6 AI0
A7 A" SENSI': AMP.
DOUT II Ab
'NE DIN
OND ITI;'

(3UOmi 1 DIP)

PIN NAMES

I Address Inputs
I· Data Input
DOUT Data Output
CE --------,~~--C-h-IP-En-a-bl-e-lr-1p-u-'t----------1

-E: l ~~~~~~n;~~tPut --~


- C-57 -
TC5561 P-55
TC5561 P-70
MAXIMUM RATINGS
SYMBOL ITEM RATING UNIT
Voo Power Supply Voltage -0.3-7.0 V
VIN Input Voltage -2.0-7.0 V
VOUT Output Voltage -0. 5-Voo+0. 5 V
Po Power Dissipation 650 mW
TSOLOEA Soldering Temperature 260·10 ·C·sec
TSTG Storage Temperature -65-150 'C
TOPA Operating Temperature 0-70 'C

D. C.RECOMMENDEDOPERATINGCONDITIONS'
J . ," •

SYMBOL PARAMETER MIN. TYP. MAX. UNIT


Voo Power Supply Voltage 4.5 5.0 5.5 V
VIH Input High Voltage 2.2 - Voo+0.3 V
VIL Input Low Voltage -3.0 - 0.8 V
VOH Data Retention Supply Voltage 2.0 - 5.5 V

~. C. and OPE.R~TING, CHARAC!ER.'STICS (Ta=0-70'C, Voo=5V± 10%)

SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT


IlL Input Leakage Current VIN=O-VOO - - ±1.0 J.lA
10H Output High Current VOH=2.4V -8 - - mA
10L Output Low Current VOL=0.4V 8 - - mA

ILO Output Leakage Current CE=VIH or WE=VIL - - ±1.0 J.lA


VOUT=O-VOO
Voo=5.5V, tcycle=Min cycle,
1000 Operating Current CE=VIL - - 100 mA
Other Input=VIH/VIL
100S1 CE=VIH - - 2 mA
Standby Current
100s2 CE=Voo-0.2V - - 100 J.lA

CAPACITANCE (Ta=25'C)

SYMBOL PARAMETER TEST CONDITION MAX. UNIT


CIN Input Capacitance VIN=GND 10 pF
COUT Output Capacitance Vour=GND 10 pF

Note: This parameter periodically sampled is not 100% tested.

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TC5561 P-55
TC5561 P-70
A. C. CHARACTERISTICS . (Ta=0-70'C, Voo=5V±10%)

Read Cycle

TC5561 P-55 TC5561 P-70


SYMBOL PARAMETER UNIT
MIN. MAX. MIN. MAX.
tRC Read Cycle Time 55 - 70 -
tACC Address Access Time - 55 - 70
teo Chip Enable Access Time - 55 - 70
ns
tCOE Chip Enable to Output in Low-Z 5 - 5 -
teoo Chip Disable to Output in High-Z - 30 - 30
tOH Output Data Hold Time 5 - 5 -

Write Cycle
TC5561 P-55 TC5561 P-70
SYMBOL PARAMETER UNIT
MIN. MAX. MIN. MAX.
twc Write Cycle Time 55 - 70 -
twp Write Pulse Width 35 - 35 -
tcw Chip Enable to End of Write 35 - 35 -
tAs Address Set up Time 0 - 0 -
tWR Write Recovery Time 0 - 0 - ns
tOEW WE to Output Low-Z 0 - 0 -
toow WE to Output High-Z - 30 - 30
tos Data Set up Time 35 - 35 -
tOH Data Hold Time 0 - 0 -


A. C. TEST CONOrrlONS
~ > , ,.,.),
48011

Input Pulse Levels 2.4V/0.6V t---_--+-----{) DOUT


Input Rise and Fall Times 5ns
Input and Output Timing
1.5V
Reference Levels
Output Load See Fig. 1

Fig.l Output Load

- C-59 -
TC5561 P-55
TC5561 P-70

TIMING WAVEFORMS
• READ CYCLE (1)

Address

DOUT

• WRITE CYCLE 1 (WE Controlled Write)

Address

DOUT

• WRITE CYCLE 2· (CE Controlled Write)

Address

Note:
1. WE is High for Read Cycle.
2. Assuming that CE Low transition occurs coincident with or aher WE Low transition. Outputs remain in a high
impedance state.
3. Assuming that CE High transition occurs coincident with or prior to WE High transition. Outputs remain in a high
impedance state.
4. The operating temperature(Ta) is guaranteed with transverse air flow exceeding 400 linear feet per minute.

- C-60 -
TC5561 P-55
TC5561 P-70
DATA RETENTION CHARACTERISTICS (Ta= -40-50'C)

SYMBOL PARAMETER MIN. TYP. MAX. UNIT


VOH Data Retention Supply Voltage 2.0 - 5.5 V

Standb¥ Supply Current


I Voo=3.0V - - 50 J.lA
loos2
I Voo=5.5V - - 100 J.lA
teoH Chip Deselection to Data Retntion Mode 0 - - J.ls
tR Recovery Time tRc( 1) - - J.ls

vnD Data Retention Mode

4. 5V -------------

tCDR VDD-O.2V

GND

5. If the VIH of ~is 2. 2V in operation. IODSl current flows the period that VDD voltage is going down from 4. 5V to 2.
5V.

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TC5561 P-55
TC5561 P-70
OUTLINE DRAWINGS

Unit in rom

7.62TYP
27.3MAX
--------------~~

(No te )
2.54 ~O.~j O.5± J.07

1.4±J.07

Note: Each lead pitch is 2. 54mrn.


All leads are located within O. 25mm of the true longitudinal position with respect to No.1 and No. 22 leads.

Note: Toshiba does not assume any responsibility for use of any circuitry descnbed ; no Circuit patent licenses are Implied. and Toshiba reserves the nght. at any time
without notice. to change said circuitry. -
©May_. '986 Toshiba Corporation

- C-62 -

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