554 IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO.

5, MAY 2014

High Mobility Solution-Processed Hafnium Indium

Zinc Oxide TFT With an Al-Doped
ZrO2 Gate Dielectric
Yana Gao, Xifeng Li, Longlong Chen, Jifeng Shi, Xiao Wei Sun, and Jianhua Zhang

Abstract— In this letter, we report a solution-processed including smooth surface and amorphous structure [6]–[8].
hafnium indium zinc oxide (HIZO) thin-film transistors (TFTs) Thus, doping Al into ZrO2 is an effective method to suppress
with an Al-doped ZrO2 (AZO) gate dielectric. The AZO thin crystallization of ZrO2 . To our knowledge, though there are
films were identified as an amorphous phase up to the annealing
temperature of 600 °C and had a smooth surface with root-mean- quite a few reports on Al2 O3 -ZrO2 composite by solution
square roughness of <0.35 nm. The relative dielectric constant of process [9], [10], the application of such films as gate dielectric
AZO thin film annealed at 400 °C is 19.67. And HIZO TFTs with layer is rare [4], only Yang et al. [4] had studied the TFTs with
AZO gate oxide exhibited a high saturation field-effect mobility solution processed Zr-doped AlOx dielectric which owned a
of 18.1 cm2 /Vs, a small subthreshold swing of 0.4 V/decade, and low relatively dielectric constant (8.4 ∼ 11.8) compared with
a high ON / OFF ratio of 107 , which can satisfy the backplate
requirements for flat panel displays. ZrO2 . Therefore, it is very interesting to pursue the solution
processed amorphous Al-doped ZrO2 (AZO) with relative high
Index Terms— Al-doped ZrO2 , amorphrous, high mobility, permittivity. In this letter, we report a high dielectric constant
solution, thin film transistor (TFT).
amorphous phase AZO derived from solution. With this gate
I. I NTRODUCTION dielectric, we fabricated hafnium indium zinc oxide (HIZO)
TFTs with high mobility, small subthreshold swing and high
A MORPHOUS oxide semiconductor thin film transistors
(TFTs) have attracted much attention with distinguished
features of high optical transparency, high mobility, and good
on-off current ratio, fulfilling current industrial requirements.

compatibility with traditional a-Si TFT process [1]. On the II. E XPERIMENTAL D ETAILS
other hand, solution-process fabricated TFTs are attracting
A 0.3 M AZO precursor was prepared by dissolving
increased interest due to the advantages of low cost and high
zirconyl chloride octahydrate (Cl2 OZr · 8H2O) and aluminum
throughput compared to conventional vacuum techniques [2].
tri-sec-butoxide (C12 H27 AlO3 ) in 2-methoxyethanol (2-MOE).
Meanwhile, with high dielectric constants as well as the coher-
The Zr:Al molar ratio of the AZO precursor solution was 2:1.
ent interface formation with oxide semiconductors, high-k gate
For HIZO solution, hafnium chloride (HfCl4 ), zinc acetate
dielectrics such as Al2 O3 , HfO2 , ZrO2 , Y2 O3 and TiO2 have
dihydrate (Zn(CH3 COO)2 · 2H2 O) and indium nitrate hydrate
been widely applied for oxide TFTs [3]–[5]. Among them,
(In(NO3)3 · xH2 O) was mixed with 2-methoxyethanol
ZrO2 is one of the most promising candidates owing to the
(2-MOE) first and then monoethanolamine (MEA) was
high dielectric constant (∼25) [5]. However, the solution-
added as a sol stabilizer. The concentration of HIZO
fabricated ZrO2 dielectric tends to exhibit a low breakdown
precursor was 0.3 M, and the In:Zn:Hf molar ratio was
voltage and a higher leakage current density [4]. In con-
3:2:0.3. Both solutions were magnetically stirred at room
trast, Al2 O3 has a wide band gap (∼9eV), a low leakage
temperature for more than 24 hours before spin-coating.
current density, low interface trap charges, and good inter-
The solution-processed HIZO TFTs with bottom-gate
face characteristics [3]. Several research groups have studied
structure were fabricated on a glass substrate. A 100 nm
composite dielectric layers formed by e-beam co-evaporation
thick indium tin oxide (ITO) bottom-gate electrode and
co-sputter, and atom layer deposition through mixing one
50 nm thick source/drain electrodes were deposited on
high-k material with Al2 O3 , which shown higher performance
glass substrates by sputtering. We used the same process
Manuscript received February 17, 2014; revised March 3, 2014; accepted (spin-coating at a rotation speed of 3000 rpm for 50 s,
March 3, 2014. Date of publication March 14, 2014; date of current version followed by a step of annealing at 300 °C for 30 min in
April 22, 2014. This work was supported in part by the National Natural
Science Foundation of China under Grant 61006005, in part by the Shanghai air) for both AZO and HIZO films, the thickness of which
Science and Technology Commission under Grant 13520500200, and in part were about 110 and 30 nm [from cross-sectional scanning
by the Shanghai Visiting Oriental Scholar Program. The review of this letter electron microscopy (SEM)], respectively. The spin-coating
was arranged by Editor S. Hall.
The authors are with the Key Laboratory of Advanced Display and System process was repeated five and two times to achieve the
Applications, Ministry of Education, Shanghai University, Shanghai 200072, above thicknesses for AZO and HIZO respectively. The
China (e-mail: [email protected]; [email protected]). capacitance value was extracted from a metal–insulator–metal
Color versions of one or more of the figures in this letter are available
online at http://ieeexplore.ieee.org. (MIM) capacitor structure, which was constructed by firstly
Digital Object Identifier 10.1109/LED.2014.2310120 spin-coating an AZO thin film onto ITO/glass substrates
0741-3106 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
GAO et al.: HIGH MOBILITY SOLUTION-PROCESSED HIZO TFT 555

Fig. 1. Optical transmittance spectrum of all the four layer films Fig. 3. Transfer characteristics of HIZO TFTs with AZO gate dielectric
(ITO/AZO/ITO/HIZO). Insets are top view of a photograph of the trans- annealed at the indicated temperatures from 300 to 500 °C. Inset is the
parency devices on the glass substrate placed on an image (left) and a typical capacitance of AZO film annealed at 400 °C.
HIZO TFT with a AZO gate dielectric taken by optical microscopy (right).

after annealing at 300 °C. When the annealing temperature

exceeded 400 °C, there was little change of the film thickness.
Fig. 2(c) and (d) show the atomic force microscopy (AFM)
images of as-coating and annealing (400 °C) AZO films. The
film became dense and homogenous after annealing. As shown
in Fig. 2(b), the root-mean-square (RMS) surface roughness is
very close and less than 0.35 nm which indicate that the film
surface was very smooth. In addition, the RMS value of AZO
was much smaller than our previous reported result of ZrO2
(> 1 nm) [11].
It is known that the ZrO2 films start to crystallize when
annealing temperature exceeds 400 °C [11]. Considering the
XRD results, the crystallization of ZrO2 films was suppressed
owing to the Al doping. The smooth surface of AZO films
Fig. 2. (a) XRD patterns of solution-processed AZO thin films with different
annealing temperatures (300-600 °C). (b) The thickness and RMS value of help to reduce the defect density and suppress the charge trap
as-coating and annealing AZO films. (c) and (d) AFM images of as-coating in the interfaces between the channel and gate dielectric [12].
and annealing (400 °C) AZO films. The improved interface quality would suppress roughness
induced leakage current and improve electrical properties [13].
And an amorphous phase is known to be advantageous over
(ITO acts as the bottom-electrode) and then thermally a crystalline phase owing to its low leakage current and high
evaporating a circular Al top-electrode via a shadow mask breakdown voltage [14]. All these results demonstrated that
(radius = 0.5 mm). The thickness of AZO film after post- the doping of Al played a prominent role in improving film
annealing at 400 °C in a MIM structure was 133 nm (from properties and getting better insulating properties. Thus, the
cross-sectional SEM). solution-processed AZO films are adequate for use as a gate
insulator.
III. R ESULT AND D ISCUSSION Fig. 3 shows the transfer characteristics of the fabricated
The TFT is optically transparent over the whole visi- TFTs (Width/Length (W/L) = 5 and L = 3 um) annealed at
ble spectrum, and the optical transmittance of all the four different temperatures (300-500 °C). The drain voltage was
layer films, ITO/AZO/ITO/HIZO, was more than 80% in the set at 1.0 V, and the gate voltage scanned from −10 V
wavelength range from 380 nm to 800 nm (Fig. 1). Insets in to +10 V. TFTs based on AZO gate dielectrics annealed at
Fig. 1 show the transparent final devices on the glass substrate 400 °C exhibited the best electrical characteristics with high
placed on a background image (left) and a typical HIZO TFT field-effect mobility (µFE ), low subthreshold swing (S.S), high
with a AZO gate dielectric taken by optical microscopy (right). on-off current ratio (Ion /Ioff ) and low threshold voltage (VT )
X-ray diffraction (XRD) patterns of AZO thin films of 18.1 cm2 /Vs, 0.4 V/decade, 107 and 0.56 V respectively.
annealed with different temperatures (300-600 °C) are shown The inset of Fig. 3 shows the capacitances (measured at
in Fig. 2(a). No distinguishable diffraction peaks were 100 kHz) of AZO film annealed at 400 °C. The capacitance
observed which revealed that AZO thin films are still in an measured through the MIM structure was about 1.03 nF, and
amorphous phase up to the annealing temperature of 600 °C. the calculated capacitance per unit area was 131 nF/cm2 . The
And as shown in the Fig. 2(b), the thickness of as-coating extracted relative dielectric constant was 19.67, which is much
AZO films was 175 nm, and the value decrease to 149 nm higher than that of Al2 O3 (9).
556 IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 5, MAY 2014

The smooth surface of amorphous AZO film attributed to

decreasing the charge trapping sates in the interface and then
improving the device electrical performance. The TFTs with
a short channel length annealed at 400 °C exhibit competitive
device electrical characteristics, including a high µFE, a high
Ion /Ioff , a low S.S, and low VT . The solution-processed oxide
TFTs described in this letter could be applicable to the
backplanes of future flat panel displays.

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