Pipeline Datapaths

By
Dr. L.Ranathunga

Lecture 10

Pipelined datapath and control

• The basic implementation of a pipelined processor is
– the datapath and control unit share similarities with
both the single-cycle and multicycle implementations

1
 Five stages pipeline
• Five-stage pipelined datapath
• IF : Instruction fetch
• ID : Instruction decode and register file read
• EX : ALU execution
• MEM: Data memory access
• WB : Write back
• Since at most five instructions can be in the datapath
at the same time, we need to save information needed
by each instructions
• if we did not save one instruction bits, the following
instruction entering the datapath will re-write the
previous instruction
• All the information for the previous one will be lost.

Pipelining concepts
• A pipelined processor allows multiple instructions
to execute at once, and each instruction uses a
different functional unit in the datapath.
• This increases throughput, so programs can run
faster.
– One instruction can finish executing on every
clock cycle, and simpler stages also lead to
shorter cycle times.
Clock cycle
1 2 3 4 5 6 7 8 9
lw $t0, 4($sp) IF ID EX MEM WB
sub $v0, $a0, $a1 IF ID EX MEM WB
and $t1, $t2, $t3 IF ID EX MEM WB
or $s0, $s1, $s2 IF ID EX MEM WB
add $t5, $t6, $0 IF ID EX MEM WB

2
 Pipelined Datapath
• The whole point of pipelining is to allow multiple instructions to
execute at the same time.
• We may need to perform several operations in the same cycle.
– Increment the PC and add registers at the same time.
– Fetch one instruction while another one reads or writes data.

• Thus, like the single-cycle datapath, a pipelined processor will

need to duplicate hardware elements that are needed several
times in the same clock cycle.
Clock cycle
1 2 3 4 5 6 7 8 9
lw $t0, 4($sp) IF ID EX MEM WB
sub $v0, $a0, $a1 IF ID EX MEM WB
and $t1, $t2, $t3 IF ID EX MEM WB
or $s0, $s1, $s2 IF ID EX MEM WB
add $t5, $t6, $0 IF ID EX MEM WB

One register file is enough

Read Read
register 1 data 1
Read Read
register 2 data 2
Write
register
Registers
Write
data

• We need only one register file to support both

the ID and WB stages.
• Reads and writes go to separate ports on the
register file
• We already took advantage of this property in our
single-cycle CPU

3
 Single-cycle datapath
1

PCSrc

4
Add
P Add
C Shift
RegWrite left 2

Read Read
register 1 data 1 MemWrite
ALU
Read Instruction Zero
Read Read
address [31-0] 0
register 2 data 2 Result Address
Write
1 Data
Instruction register MemToReg
memory
memory Registers ALUOp
Write
data ALUSrc Write Read
1
data data
Instr [15 - 0] Sign
RegDst
extend MemRead
0
Instr [20 - 16]
0
Instr [15 - 11]
1

Five stages pipeline …

• PC (program counter) passes the instruction
address from one clock cycle to the next
clock cycle, we can insert registers between
two stages
• IF/ID registers: PC address, instruction
• ID/EX registers: PC address, Read Data 1,
Read Data 2, sign-extended offset
• EX/MEM registers: branch address, Zero
signal, ALU result, Read Data 2
• MEM/WB registers: Read Data from Data
Memory, ALU result

4
 Five stages

Pipelined Datapath

5
 Instruction Fetch
• The instruction is read from memory using the
address in the PC and then placed in the IF/ID
pipeline register.
• The PC address incremented by 4 and then
written back into the PC to be ready for the
next clock cycle. This address is also saved in
the IF/ID pipeline register in case it is needed
later.
• The computer cannot know what type of
instruction is being fetched. => prepare for any
instruction.

Instruction Decode and Register

File Read
• Instruction portion of the IF/ID pipeline
register supplies the 16-bit immediate
field and the register numbers to read.
• All three values are stored in the ID/EX
pipeline register along with the
incremented PC address.

6
 Execute or Address
Calculation

• The load instruction reads the

contents of register 1 and the sign-
extended immediate from the ID/EX
pipeline register and adds them using
the ALU.
• The sum is placed in the EX/MEM
pipeline register.

Memory Access

• The load instruction reads the data

memory using the address from the
EX/MEM pipeline register.
• The instruction loads the data into
the MEM/WB pipeline register.

7
 Write Back

• The instruction reads the data from

the MEM/WB pipeline register and
writes it into the register file.

Registers added to the multi-

PCWrite
cycle
PC ALUSrcA
IorD
0
RegDst RegWrite M
MemRead u
0 0
Read Read x
M A ALU M
u Address register 1 data 1 1 u
Zero
x ALU x
IRWrite Read Result
1 Memory register 2 Read B Out 1
0 0
data 2
[31-26] M Write 4 1 PCSource
Write Mem u register
[25-21] 2 ALUOp
data Data x
[20-16] Write Registers 3
[15-11] 1 data
MemWrite [15-0]
Instruction 0 ALUSrcB
register M
u Sign Shift
Memory x extend left 2
data
1
register

MemToReg

8
 Pipeline registers
• Add intermediate registers to pipelined datapath
• There’s a lot of information to save, however. We’ll
simplify our diagrams by drawing just one big pipeline
register between each stage.
• The registers are named for the stages they
connect.

IF/ID ID/EX EX/MEM

MEM/WB

• No register is needed after the WB stage, because

after WB the instruction is done.

Pipelined datapath
1

PCSrc

IF/ID ID/EX EX/MEM MEM/WB

4
Add
P Add
C Shift
RegWrite left 2

Read Read
register 1 data 1 MemWrite
ALU
Read Instruction Zero
Read Read
address [31-0] 0
register 2 data 2 Result Address
Write
1 Data
Instruction register MemToReg
memory
memory Registers ALUOp
Write
data ALUSrc Write Read
1
data data
Instr [15 - 0] Sign
RegDst
extend MemRead
0
Instr [20 - 16]
0
Instr [15 - 11]
1

9
 The destination register
1

PCSrc

IF/ID ID/EX EX/MEM MEM/WB

4
Add
P Add
C Shift
RegWrite left 2

Read Read
register 1 data 1 MemWrite
ALU
Read Instruction Zero
Read Read
address [31-0] 0
register 2 data 2 Result Address
Write
1 Data
Instruction register MemToReg
memory
memory Registers ALUOp
Write
data ALUSrc Write Read
1
data data
Instr [15 - 0] Sign
RegDst
extend MemRead
0
Instr [20 - 16]
0
Instr [15 - 11]
1

Notes about the diagram

• The control signals are grouped together in the
pipeline registers
• Not all of the registers have a write enable signal
– Because the datapath fetches one instruction
per cycle, the PC must also be updated on each
clock cycle. Including a write enable for the PC
would be redundant
– Similarly, the pipeline registers are also
written on every cycle, so no explicit write
signals are needed

10
 An example execution sequence
• Here’s a sample sequence of instructions to execute.

addresses 1000: lw $8, 4($29)

in decimal 1004: sub $2, $4, $5
1008: and $9, $10, $11
1012: or $16, $17, $18
1016: add $13, $14, $0

• We’ll make some assumptions, just so we can show actual data values.
– Each register contains its number plus 100. For instance, register
$8 contains 108, register $29 contains 129, and so forth.
– Every data memory location contains 99.
• Our pipeline diagrams will follow some conventions.
– An X indicates values that aren’t important, like the constant field
of an R-type instruction.
– Question marks ??? indicate values we don’t know, usually resulting
from instructions coming before and after the ones in our
example.

Cycle 1 (filling)
IF: lw $8, 4($29) ID: ??? EX: ??? MEM: ??? WB: ???

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB
4
Add
P 1004
Add
C Shift
RegWrite (?) left 2

??? ??? ???

1000 Read Read
register 1 data 1 MemWrite (?)
ALU
Read Instruction ??? ??? Zero
Read Read ??? ???
address [31-0] 0
register 2 data 2 Result Address
??? Write ??? MemToReg
1 Data
Instruction register (?)
memory
memory ??? Registers ALUOp (???)
Write
???
data ALUSrc (?) ??? Write Read
1
data data
??? Sign ???
RegDst (?)
extend MemRead (?) ???
0
??? ???
0 ??? ??? ???
??? ???
1

???

11
 Cycle 2
IF: sub $2, $4, $5 ID: lw $8, 4($29) EX: ??? MEM: ??? WB: ???

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB
4
Add
P 1008
Add
C Shift
RegWrite (?) left 2

29 129 ???
1004 Read Read
register 1 data 1 MemWrite (?)
ALU
Read Instruction X X ??? Zero
Read Read ???
address [31-0] 0
register 2 data 2 Result Address
??? Write ??? MemToReg
1 Data
Instruction register (?)
memory
memory ??? Registers ALUOp (???)
Write ???
data ALUSrc (?) ??? Write Read
1
data data
4 Sign ???
RegDst (?) ???
extend MemRead (?)
0
8 ???
0 ??? ??? ???
X ???
1

???

Cycle 3
IF: and $9, $10, $11 ID: sub $2, $4, $5 EX: lw $8, 4($29) MEM: ??? WB: ???

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB
4
Add
P 1012
Add
C Shift
RegWrite (?) left 2

4 104 129
1008 Read Read
register 1 data 1 MemWrite (?)
ALU
Read Instruction 5 X Zero
Read Read 105 ???
address [31-0] 0
register 2 data 2 Result Address
4
??? Write 133 MemToReg
1 Data
Instruction register (?)
memory
memory ??? Registers ALUOp (add)
Write
??? Write ???
data ALUSrc (1) Read
1
data data
X Sign 4
RegDst (0)
extend MemRead (?) ???
0
X 8
0 8 ??? ???
2 X
1

???

12
 Cycle 4
IF: or $16, $17, $18 ID: and $9, $10, $11 EX: sub $2, $4, $5 MEM: lw $8, 4($29) WB: ???

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB
4
Add
P 1016
Add
C Shift
RegWrite (?) left 2

10 110 104
1012 Read Read
register 1 data 1 MemWrite (0)
ALU
Read Instruction 11 105 Zero
Read Read 111 133
address [31-0] 0
register 2 data 2 Result Address
–1
??? Write MemToReg
1 Data
Instruction register (?)
memory
memory ??? Registers ALUOp (sub)
Write
99 ???
data ALUSrc (0) X Write Read
1
data data
X Sign X
RegDst (1)
extend MemRead (1) ???
0
X X
0 2 8 ???
9 2
1

???

Cycle 5 (full)
IF: add $13, $14, $0 ID: or $16, $17, $18 EX: and $9, $10, $11 MEM: sub $2, $4, $5 WB:
lw $8, 4($29)
1

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB
4
Add
P 1020
Add
C Shift
RegWrite (1) left 2

17 117 110
1016 Read Read
register 1 data 1 MemWrite (0)
ALU
Read Instruction 18 111 Zero
Read Read 118 -1
address [31-0] 0
register 2 data 2 Result Address
8 Write 110 MemToReg
1 Data
Instruction register (1)
memory
memory 99 Registers ALUOp (and)
Write X 99
data ALUSrc (0) 105 Write Read
1
data data
X Sign X
RegDst (1)
extend MemRead (0) 133
0
X X
0 9 2 8
16 9
1

99

13
 Cycle 6 (emptying)
IF: ??? ID: add $13, $14, $0 EX: or $16, $17, $18 MEM: and $9, $10, $11 WB: sub
$2, $4, $5
1

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB
4
Add
P ???
Add
C Shift
RegWrite (1) left 2

14 114 117
1020 Read Read
register 1 data 1 MemWrite (0)
ALU
Read Instruction 0 0 118 Zero
Read Read 110
address [31-0] 0
register 2 data 2 Result Address
2 Write 119 MemToReg
1 Data
Instruction register (0)
memory
memory -1 Registers ALUOp (or)
Write
X
data ALUSrc (0) 111 Write Read
1
data data
X Sign X
RegDst (1)
extend MemRead (0)
0
X X
0 16 9
13 16
1

Cycle 7
IF: ??? ID: ??? EX: add $13, $14, $0 MEM: or $16, $17, $18 WB: and
$9, $10, $11
1

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB
4
Add
P ???
Add
C Shift
RegWrite (1) left 2

??? ??? 114

??? Read Read
register 1 data 1 MemWrite (0)
ALU
Read Instruction ??? 0 Zero
Read Read ??? 119
address [31-0] 0
register 2 data 2 Result Address
9 Write 114 MemToReg
1 Data
Instruction register (0)
memory
memory 110 Registers ALUOp (add)
Write
X X
data ALUSrc (0) 118 Write Read
1
data data
??? Sign X
RegDst (1)
extend MemRead (0) 110
0
??? X
0 13 16 9
??? 13
1

110

14
 Cycle 8
IF: ??? ID: ??? EX: ??? MEM: add $13, $14, $0 WB: or $16,
$17, $18
1

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB
4
Add
P ???
Add
C Shift
RegWrite (1) left 2

??? ??? ???

??? Read Read
register 1 data 1 MemWrite (0)
ALU
Read Instruction ??? ??? Zero
Read Read ??? 114
address [31-0] 0
register 2 data 2 Result Address
16 Write ??? MemToReg
1 Data
Instruction register (0)
memory
memory 119 Registers ALUOp (???)
Write
X X
data ALUSrc (?) 0 Write Read
1
data data
??? Sign ???
RegDst (?)
extend MemRead (0) 119
0
??? ???
0 ??? 13 16
??? ???
1

119

Cycle 9
IF: ??? ID: ??? EX: ??? MEM: ??? WB: add
$13, $14, $0
1

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB
4
Add
P ???
Add
C Shift
RegWrite (1) left 2

??? ??? ???

??? Read Read
register 1 data 1 MemWrite (?)
ALU
Read Instruction ??? ??? Zero
Read Read ??? ???
address [31-0] 0
register 2 data 2 Result Address
13 Write ??? MemToReg
1 Data
Instruction register (0)
memory
memory 114 Registers ALUOp (???)
Write X X
data ALUSrc (?) ? Write Read
1
data data
??? Sign ???
RegDst (?)
extend MemRead (?) 114
0
??? ???
0 ??? ??? 13
??? ???
1

114

15
 Visualizing Pipelining
Time (clock cycles)

ALU
I Mem Reg Mem Reg
n
Load
s

ALU
Mem Reg Mem Reg
t Instr 1
r.

ALU
Mem Reg Mem Reg
O Instr 2
r

ALU
d Mem Reg Mem Reg
e
Instr 3
r

ALU
Mem Reg Mem Reg
Instr 4

• Questions?

16